1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include "pp_debug.h"
24 #include "smumgr.h"
25 #include "smu_ucode_xfer_vi.h"
26 #include "vegam_smumgr.h"
27 #include "smu/smu_7_1_3_d.h"
28 #include "smu/smu_7_1_3_sh_mask.h"
29 #include "gmc/gmc_8_1_d.h"
30 #include "gmc/gmc_8_1_sh_mask.h"
31 #include "oss/oss_3_0_d.h"
32 #include "gca/gfx_8_0_d.h"
33 #include "bif/bif_5_0_d.h"
34 #include "bif/bif_5_0_sh_mask.h"
35 #include "ppatomctrl.h"
36 #include "cgs_common.h"
37 #include "smu7_ppsmc.h"
38
39 #include "smu7_dyn_defaults.h"
40
41 #include "smu7_hwmgr.h"
42 #include "hardwaremanager.h"
43 #include "ppatomctrl.h"
44 #include "atombios.h"
45 #include "pppcielanes.h"
46
47 #include "dce/dce_11_2_d.h"
48 #include "dce/dce_11_2_sh_mask.h"
49
50 #define PPVEGAM_TARGETACTIVITY_DFLT 50
51
52 #define VOLTAGE_VID_OFFSET_SCALE1 625
53 #define VOLTAGE_VID_OFFSET_SCALE2 100
54 #define POWERTUNE_DEFAULT_SET_MAX 1
55 #define VDDC_VDDCI_DELTA 200
56 #define MC_CG_ARB_FREQ_F1 0x0b
57
58 #define STRAP_ASIC_RO_LSB 2168
59 #define STRAP_ASIC_RO_MSB 2175
60
61 #define PPSMC_MSG_ApplyAvfsCksOffVoltage ((uint16_t) 0x415)
62 #define PPSMC_MSG_EnableModeSwitchRLCNotification ((uint16_t) 0x305)
63
64 static const struct vegam_pt_defaults
65 vegam_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
66 /* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
67 * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT */
68 { 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
69 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
70 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } },
71 };
72
73 static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] = {
74 {VCO_2_4, POSTDIV_DIV_BY_16, 75, 160, 112},
75 {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
76 {VCO_2_4, POSTDIV_DIV_BY_8, 75, 160, 112},
77 {VCO_3_6, POSTDIV_DIV_BY_8, 112, 224, 160},
78 {VCO_2_4, POSTDIV_DIV_BY_4, 75, 160, 112},
79 {VCO_3_6, POSTDIV_DIV_BY_4, 112, 216, 160},
80 {VCO_2_4, POSTDIV_DIV_BY_2, 75, 160, 108},
81 {VCO_3_6, POSTDIV_DIV_BY_2, 112, 216, 160} };
82
vegam_smu_init(struct pp_hwmgr * hwmgr)83 static int vegam_smu_init(struct pp_hwmgr *hwmgr)
84 {
85 struct vegam_smumgr *smu_data;
86
87 smu_data = kzalloc(sizeof(struct vegam_smumgr), GFP_KERNEL);
88 if (smu_data == NULL)
89 return -ENOMEM;
90
91 hwmgr->smu_backend = smu_data;
92
93 if (smu7_init(hwmgr)) {
94 kfree(smu_data);
95 return -EINVAL;
96 }
97
98 return 0;
99 }
100
vegam_start_smu_in_protection_mode(struct pp_hwmgr * hwmgr)101 static int vegam_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
102 {
103 int result = 0;
104
105 /* Wait for smc boot up */
106 /* PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */
107
108 /* Assert reset */
109 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
110 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
111
112 result = smu7_upload_smu_firmware_image(hwmgr);
113 if (result != 0)
114 return result;
115
116 /* Clear status */
117 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
118
119 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
120 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
121
122 /* De-assert reset */
123 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
124 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
125
126
127 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
128
129
130 /* Call Test SMU message with 0x20000 offset to trigger SMU start */
131 smu7_send_msg_to_smc_offset(hwmgr);
132
133 /* Wait done bit to be set */
134 /* Check pass/failed indicator */
135
136 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, SMU_STATUS, SMU_DONE, 0);
137
138 if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
139 SMU_STATUS, SMU_PASS))
140 PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);
141
142 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
143
144 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
145 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
146
147 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
148 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
149
150 /* Wait for firmware to initialize */
151 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
152
153 return result;
154 }
155
vegam_start_smu_in_non_protection_mode(struct pp_hwmgr * hwmgr)156 static int vegam_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
157 {
158 int result = 0;
159
160 /* wait for smc boot up */
161 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
162
163 /* Clear firmware interrupt enable flag */
164 /* PHM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */
165 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
166 ixFIRMWARE_FLAGS, 0);
167
168 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
169 SMC_SYSCON_RESET_CNTL,
170 rst_reg, 1);
171
172 result = smu7_upload_smu_firmware_image(hwmgr);
173 if (result != 0)
174 return result;
175
176 /* Set smc instruct start point at 0x0 */
177 smu7_program_jump_on_start(hwmgr);
178
179 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
180 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
181
182 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
183 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
184
185 /* Wait for firmware to initialize */
186
187 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
188 FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
189
190 return result;
191 }
192
vegam_start_smu(struct pp_hwmgr * hwmgr)193 static int vegam_start_smu(struct pp_hwmgr *hwmgr)
194 {
195 int result = 0;
196 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
197
198 /* Only start SMC if SMC RAM is not running */
199 if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) {
200 smu_data->protected_mode = (uint8_t)(PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
201 CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
202 smu_data->smu7_data.security_hard_key = (uint8_t)(PHM_READ_VFPF_INDIRECT_FIELD(
203 hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
204
205 /* Check if SMU is running in protected mode */
206 if (smu_data->protected_mode == 0)
207 result = vegam_start_smu_in_non_protection_mode(hwmgr);
208 else
209 result = vegam_start_smu_in_protection_mode(hwmgr);
210
211 if (result != 0)
212 PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);
213 }
214
215 /* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */
216 smu7_read_smc_sram_dword(hwmgr,
217 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU75_Firmware_Header, SoftRegisters),
218 &(smu_data->smu7_data.soft_regs_start),
219 0x40000);
220
221 result = smu7_request_smu_load_fw(hwmgr);
222
223 return result;
224 }
225
vegam_process_firmware_header(struct pp_hwmgr * hwmgr)226 static int vegam_process_firmware_header(struct pp_hwmgr *hwmgr)
227 {
228 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
229 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
230 uint32_t tmp;
231 int result;
232 bool error = false;
233
234 result = smu7_read_smc_sram_dword(hwmgr,
235 SMU7_FIRMWARE_HEADER_LOCATION +
236 offsetof(SMU75_Firmware_Header, DpmTable),
237 &tmp, SMC_RAM_END);
238
239 if (0 == result)
240 smu_data->smu7_data.dpm_table_start = tmp;
241
242 error |= (0 != result);
243
244 result = smu7_read_smc_sram_dword(hwmgr,
245 SMU7_FIRMWARE_HEADER_LOCATION +
246 offsetof(SMU75_Firmware_Header, SoftRegisters),
247 &tmp, SMC_RAM_END);
248
249 if (!result) {
250 data->soft_regs_start = tmp;
251 smu_data->smu7_data.soft_regs_start = tmp;
252 }
253
254 error |= (0 != result);
255
256 result = smu7_read_smc_sram_dword(hwmgr,
257 SMU7_FIRMWARE_HEADER_LOCATION +
258 offsetof(SMU75_Firmware_Header, mcRegisterTable),
259 &tmp, SMC_RAM_END);
260
261 if (!result)
262 smu_data->smu7_data.mc_reg_table_start = tmp;
263
264 result = smu7_read_smc_sram_dword(hwmgr,
265 SMU7_FIRMWARE_HEADER_LOCATION +
266 offsetof(SMU75_Firmware_Header, FanTable),
267 &tmp, SMC_RAM_END);
268
269 if (!result)
270 smu_data->smu7_data.fan_table_start = tmp;
271
272 error |= (0 != result);
273
274 result = smu7_read_smc_sram_dword(hwmgr,
275 SMU7_FIRMWARE_HEADER_LOCATION +
276 offsetof(SMU75_Firmware_Header, mcArbDramTimingTable),
277 &tmp, SMC_RAM_END);
278
279 if (!result)
280 smu_data->smu7_data.arb_table_start = tmp;
281
282 error |= (0 != result);
283
284 result = smu7_read_smc_sram_dword(hwmgr,
285 SMU7_FIRMWARE_HEADER_LOCATION +
286 offsetof(SMU75_Firmware_Header, Version),
287 &tmp, SMC_RAM_END);
288
289 if (!result)
290 hwmgr->microcode_version_info.SMC = tmp;
291
292 error |= (0 != result);
293
294 return error ? -1 : 0;
295 }
296
vegam_is_dpm_running(struct pp_hwmgr * hwmgr)297 static bool vegam_is_dpm_running(struct pp_hwmgr *hwmgr)
298 {
299 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
300 CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
301 ? true : false;
302 }
303
vegam_get_mac_definition(uint32_t value)304 static uint32_t vegam_get_mac_definition(uint32_t value)
305 {
306 switch (value) {
307 case SMU_MAX_LEVELS_GRAPHICS:
308 return SMU75_MAX_LEVELS_GRAPHICS;
309 case SMU_MAX_LEVELS_MEMORY:
310 return SMU75_MAX_LEVELS_MEMORY;
311 case SMU_MAX_LEVELS_LINK:
312 return SMU75_MAX_LEVELS_LINK;
313 case SMU_MAX_ENTRIES_SMIO:
314 return SMU75_MAX_ENTRIES_SMIO;
315 case SMU_MAX_LEVELS_VDDC:
316 return SMU75_MAX_LEVELS_VDDC;
317 case SMU_MAX_LEVELS_VDDGFX:
318 return SMU75_MAX_LEVELS_VDDGFX;
319 case SMU_MAX_LEVELS_VDDCI:
320 return SMU75_MAX_LEVELS_VDDCI;
321 case SMU_MAX_LEVELS_MVDD:
322 return SMU75_MAX_LEVELS_MVDD;
323 case SMU_UVD_MCLK_HANDSHAKE_DISABLE:
324 return SMU7_UVD_MCLK_HANDSHAKE_DISABLE |
325 SMU7_VCE_MCLK_HANDSHAKE_DISABLE;
326 }
327
328 pr_warn("can't get the mac of %x\n", value);
329 return 0;
330 }
331
vegam_update_uvd_smc_table(struct pp_hwmgr * hwmgr)332 static int vegam_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
333 {
334 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
335 uint32_t mm_boot_level_offset, mm_boot_level_value;
336 struct phm_ppt_v1_information *table_info =
337 (struct phm_ppt_v1_information *)(hwmgr->pptable);
338
339 smu_data->smc_state_table.UvdBootLevel = 0;
340 if (table_info->mm_dep_table->count > 0)
341 smu_data->smc_state_table.UvdBootLevel =
342 (uint8_t) (table_info->mm_dep_table->count - 1);
343 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU75_Discrete_DpmTable,
344 UvdBootLevel);
345 mm_boot_level_offset /= 4;
346 mm_boot_level_offset *= 4;
347 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
348 CGS_IND_REG__SMC, mm_boot_level_offset);
349 mm_boot_level_value &= 0x00FFFFFF;
350 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
351 cgs_write_ind_register(hwmgr->device,
352 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
353
354 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
355 PHM_PlatformCaps_UVDDPM) ||
356 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
357 PHM_PlatformCaps_StablePState))
358 smum_send_msg_to_smc_with_parameter(hwmgr,
359 PPSMC_MSG_UVDDPM_SetEnabledMask,
360 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
361 return 0;
362 }
363
vegam_update_vce_smc_table(struct pp_hwmgr * hwmgr)364 static int vegam_update_vce_smc_table(struct pp_hwmgr *hwmgr)
365 {
366 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
367 uint32_t mm_boot_level_offset, mm_boot_level_value;
368 struct phm_ppt_v1_information *table_info =
369 (struct phm_ppt_v1_information *)(hwmgr->pptable);
370
371 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
372 PHM_PlatformCaps_StablePState))
373 smu_data->smc_state_table.VceBootLevel =
374 (uint8_t) (table_info->mm_dep_table->count - 1);
375 else
376 smu_data->smc_state_table.VceBootLevel = 0;
377
378 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
379 offsetof(SMU75_Discrete_DpmTable, VceBootLevel);
380 mm_boot_level_offset /= 4;
381 mm_boot_level_offset *= 4;
382 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
383 CGS_IND_REG__SMC, mm_boot_level_offset);
384 mm_boot_level_value &= 0xFF00FFFF;
385 mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
386 cgs_write_ind_register(hwmgr->device,
387 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
388
389 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
390 smum_send_msg_to_smc_with_parameter(hwmgr,
391 PPSMC_MSG_VCEDPM_SetEnabledMask,
392 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
393 return 0;
394 }
395
vegam_update_bif_smc_table(struct pp_hwmgr * hwmgr)396 static int vegam_update_bif_smc_table(struct pp_hwmgr *hwmgr)
397 {
398 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
399 struct phm_ppt_v1_information *table_info =
400 (struct phm_ppt_v1_information *)(hwmgr->pptable);
401 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
402 int max_entry, i;
403
404 max_entry = (SMU75_MAX_LEVELS_LINK < pcie_table->count) ?
405 SMU75_MAX_LEVELS_LINK :
406 pcie_table->count;
407 /* Setup BIF_SCLK levels */
408 for (i = 0; i < max_entry; i++)
409 smu_data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
410 return 0;
411 }
412
vegam_update_smc_table(struct pp_hwmgr * hwmgr,uint32_t type)413 static int vegam_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
414 {
415 switch (type) {
416 case SMU_UVD_TABLE:
417 vegam_update_uvd_smc_table(hwmgr);
418 break;
419 case SMU_VCE_TABLE:
420 vegam_update_vce_smc_table(hwmgr);
421 break;
422 case SMU_BIF_TABLE:
423 vegam_update_bif_smc_table(hwmgr);
424 break;
425 default:
426 break;
427 }
428 return 0;
429 }
430
vegam_initialize_power_tune_defaults(struct pp_hwmgr * hwmgr)431 static void vegam_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
432 {
433 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
434 struct phm_ppt_v1_information *table_info =
435 (struct phm_ppt_v1_information *)(hwmgr->pptable);
436
437 if (table_info &&
438 table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
439 table_info->cac_dtp_table->usPowerTuneDataSetID)
440 smu_data->power_tune_defaults =
441 &vegam_power_tune_data_set_array
442 [table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
443 else
444 smu_data->power_tune_defaults = &vegam_power_tune_data_set_array[0];
445
446 }
447
vegam_populate_smc_mvdd_table(struct pp_hwmgr * hwmgr,SMU75_Discrete_DpmTable * table)448 static int vegam_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
449 SMU75_Discrete_DpmTable *table)
450 {
451 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
452 uint32_t count, level;
453
454 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
455 count = data->mvdd_voltage_table.count;
456 if (count > SMU_MAX_SMIO_LEVELS)
457 count = SMU_MAX_SMIO_LEVELS;
458 for (level = 0; level < count; level++) {
459 table->SmioTable2.Pattern[level].Voltage = PP_HOST_TO_SMC_US(
460 data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
461 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
462 table->SmioTable2.Pattern[level].Smio =
463 (uint8_t) level;
464 table->Smio[level] |=
465 data->mvdd_voltage_table.entries[level].smio_low;
466 }
467 table->SmioMask2 = data->mvdd_voltage_table.mask_low;
468
469 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
470 }
471
472 return 0;
473 }
474
vegam_populate_smc_vddci_table(struct pp_hwmgr * hwmgr,struct SMU75_Discrete_DpmTable * table)475 static int vegam_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
476 struct SMU75_Discrete_DpmTable *table)
477 {
478 uint32_t count, level;
479 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
480
481 count = data->vddci_voltage_table.count;
482
483 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
484 if (count > SMU_MAX_SMIO_LEVELS)
485 count = SMU_MAX_SMIO_LEVELS;
486 for (level = 0; level < count; ++level) {
487 table->SmioTable1.Pattern[level].Voltage = PP_HOST_TO_SMC_US(
488 data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
489 table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
490
491 table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
492 }
493 }
494
495 table->SmioMask1 = data->vddci_voltage_table.mask_low;
496
497 return 0;
498 }
499
vegam_populate_cac_table(struct pp_hwmgr * hwmgr,struct SMU75_Discrete_DpmTable * table)500 static int vegam_populate_cac_table(struct pp_hwmgr *hwmgr,
501 struct SMU75_Discrete_DpmTable *table)
502 {
503 uint32_t count;
504 uint8_t index;
505 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
506 struct phm_ppt_v1_information *table_info =
507 (struct phm_ppt_v1_information *)(hwmgr->pptable);
508 struct phm_ppt_v1_voltage_lookup_table *lookup_table =
509 table_info->vddc_lookup_table;
510 /* tables is already swapped, so in order to use the value from it,
511 * we need to swap it back.
512 * We are populating vddc CAC data to BapmVddc table
513 * in split and merged mode
514 */
515 for (count = 0; count < lookup_table->count; count++) {
516 index = phm_get_voltage_index(lookup_table,
517 data->vddc_voltage_table.entries[count].value);
518 table->BapmVddcVidLoSidd[count] =
519 convert_to_vid(lookup_table->entries[index].us_cac_low);
520 table->BapmVddcVidHiSidd[count] =
521 convert_to_vid(lookup_table->entries[index].us_cac_mid);
522 table->BapmVddcVidHiSidd2[count] =
523 convert_to_vid(lookup_table->entries[index].us_cac_high);
524 }
525
526 return 0;
527 }
528
vegam_populate_smc_voltage_tables(struct pp_hwmgr * hwmgr,struct SMU75_Discrete_DpmTable * table)529 static int vegam_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
530 struct SMU75_Discrete_DpmTable *table)
531 {
532 vegam_populate_smc_vddci_table(hwmgr, table);
533 vegam_populate_smc_mvdd_table(hwmgr, table);
534 vegam_populate_cac_table(hwmgr, table);
535
536 return 0;
537 }
538
vegam_populate_ulv_level(struct pp_hwmgr * hwmgr,struct SMU75_Discrete_Ulv * state)539 static int vegam_populate_ulv_level(struct pp_hwmgr *hwmgr,
540 struct SMU75_Discrete_Ulv *state)
541 {
542 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
543 struct phm_ppt_v1_information *table_info =
544 (struct phm_ppt_v1_information *)(hwmgr->pptable);
545
546 state->CcPwrDynRm = 0;
547 state->CcPwrDynRm1 = 0;
548
549 state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
550 state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
551 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
552
553 state->VddcPhase = data->vddc_phase_shed_control ^ 0x3;
554
555 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
556 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
557 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
558
559 return 0;
560 }
561
vegam_populate_ulv_state(struct pp_hwmgr * hwmgr,struct SMU75_Discrete_DpmTable * table)562 static int vegam_populate_ulv_state(struct pp_hwmgr *hwmgr,
563 struct SMU75_Discrete_DpmTable *table)
564 {
565 return vegam_populate_ulv_level(hwmgr, &table->Ulv);
566 }
567
vegam_populate_smc_link_level(struct pp_hwmgr * hwmgr,struct SMU75_Discrete_DpmTable * table)568 static int vegam_populate_smc_link_level(struct pp_hwmgr *hwmgr,
569 struct SMU75_Discrete_DpmTable *table)
570 {
571 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
572 struct vegam_smumgr *smu_data =
573 (struct vegam_smumgr *)(hwmgr->smu_backend);
574 struct smu7_dpm_table *dpm_table = &data->dpm_table;
575 int i;
576
577 /* Index (dpm_table->pcie_speed_table.count)
578 * is reserved for PCIE boot level. */
579 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
580 table->LinkLevel[i].PcieGenSpeed =
581 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
582 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
583 dpm_table->pcie_speed_table.dpm_levels[i].param1);
584 table->LinkLevel[i].EnabledForActivity = 1;
585 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
586 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
587 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
588 }
589
590 smu_data->smc_state_table.LinkLevelCount =
591 (uint8_t)dpm_table->pcie_speed_table.count;
592
593 /* To Do move to hwmgr */
594 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
595 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
596
597 return 0;
598 }
599
vegam_get_dependency_volt_by_clk(struct pp_hwmgr * hwmgr,struct phm_ppt_v1_clock_voltage_dependency_table * dep_table,uint32_t clock,SMU_VoltageLevel * voltage,uint32_t * mvdd)600 static int vegam_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
601 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
602 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
603 {
604 uint32_t i;
605 uint16_t vddci;
606 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
607
608 *voltage = *mvdd = 0;
609
610 /* clock - voltage dependency table is empty table */
611 if (dep_table->count == 0)
612 return -EINVAL;
613
614 for (i = 0; i < dep_table->count; i++) {
615 /* find first sclk bigger than request */
616 if (dep_table->entries[i].clk >= clock) {
617 *voltage |= (dep_table->entries[i].vddc *
618 VOLTAGE_SCALE) << VDDC_SHIFT;
619 if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
620 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
621 VOLTAGE_SCALE) << VDDCI_SHIFT;
622 else if (dep_table->entries[i].vddci)
623 *voltage |= (dep_table->entries[i].vddci *
624 VOLTAGE_SCALE) << VDDCI_SHIFT;
625 else {
626 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
627 (dep_table->entries[i].vddc -
628 (uint16_t)VDDC_VDDCI_DELTA));
629 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
630 }
631
632 if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
633 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
634 VOLTAGE_SCALE;
635 else if (dep_table->entries[i].mvdd)
636 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
637 VOLTAGE_SCALE;
638
639 *voltage |= 1 << PHASES_SHIFT;
640 return 0;
641 }
642 }
643
644 /* sclk is bigger than max sclk in the dependence table */
645 *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
646
647 if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
648 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
649 VOLTAGE_SCALE) << VDDCI_SHIFT;
650 else if (dep_table->entries[i - 1].vddci)
651 *voltage |= (dep_table->entries[i - 1].vddci *
652 VOLTAGE_SCALE) << VDDC_SHIFT;
653 else {
654 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
655 (dep_table->entries[i - 1].vddc -
656 (uint16_t)VDDC_VDDCI_DELTA));
657
658 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
659 }
660
661 if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
662 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
663 else if (dep_table->entries[i].mvdd)
664 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
665
666 return 0;
667 }
668
vegam_get_sclk_range_table(struct pp_hwmgr * hwmgr,SMU75_Discrete_DpmTable * table)669 static void vegam_get_sclk_range_table(struct pp_hwmgr *hwmgr,
670 SMU75_Discrete_DpmTable *table)
671 {
672 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
673 uint32_t i, ref_clk;
674
675 struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
676
677 ref_clk = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
678
679 if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
680 for (i = 0; i < NUM_SCLK_RANGE; i++) {
681 table->SclkFcwRangeTable[i].vco_setting =
682 range_table_from_vbios.entry[i].ucVco_setting;
683 table->SclkFcwRangeTable[i].postdiv =
684 range_table_from_vbios.entry[i].ucPostdiv;
685 table->SclkFcwRangeTable[i].fcw_pcc =
686 range_table_from_vbios.entry[i].usFcw_pcc;
687
688 table->SclkFcwRangeTable[i].fcw_trans_upper =
689 range_table_from_vbios.entry[i].usFcw_trans_upper;
690 table->SclkFcwRangeTable[i].fcw_trans_lower =
691 range_table_from_vbios.entry[i].usRcw_trans_lower;
692
693 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
694 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
695 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
696 }
697 return;
698 }
699
700 for (i = 0; i < NUM_SCLK_RANGE; i++) {
701 smu_data->range_table[i].trans_lower_frequency =
702 (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
703 smu_data->range_table[i].trans_upper_frequency =
704 (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
705
706 table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
707 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
708 table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
709
710 table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
711 table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
712
713 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
714 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
715 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
716 }
717 }
718
vegam_calculate_sclk_params(struct pp_hwmgr * hwmgr,uint32_t clock,SMU_SclkSetting * sclk_setting)719 static int vegam_calculate_sclk_params(struct pp_hwmgr *hwmgr,
720 uint32_t clock, SMU_SclkSetting *sclk_setting)
721 {
722 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
723 const SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
724 struct pp_atomctrl_clock_dividers_ai dividers;
725 uint32_t ref_clock;
726 uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
727 uint8_t i;
728 int result;
729 uint64_t temp;
730
731 sclk_setting->SclkFrequency = clock;
732 /* get the engine clock dividers for this clock value */
733 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs);
734 if (result == 0) {
735 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
736 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
737 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
738 sclk_setting->PllRange = dividers.ucSclkPllRange;
739 sclk_setting->Sclk_slew_rate = 0x400;
740 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
741 sclk_setting->Pcc_down_slew_rate = 0xffff;
742 sclk_setting->SSc_En = dividers.ucSscEnable;
743 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
744 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
745 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
746 return result;
747 }
748
749 ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
750
751 for (i = 0; i < NUM_SCLK_RANGE; i++) {
752 if (clock > smu_data->range_table[i].trans_lower_frequency
753 && clock <= smu_data->range_table[i].trans_upper_frequency) {
754 sclk_setting->PllRange = i;
755 break;
756 }
757 }
758
759 sclk_setting->Fcw_int = (uint16_t)
760 ((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) /
761 ref_clock);
762 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
763 temp <<= 0x10;
764 do_div(temp, ref_clock);
765 sclk_setting->Fcw_frac = temp & 0xffff;
766
767 pcc_target_percent = 10; /* Hardcode 10% for now. */
768 pcc_target_freq = clock - (clock * pcc_target_percent / 100);
769 sclk_setting->Pcc_fcw_int = (uint16_t)
770 ((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) /
771 ref_clock);
772
773 ss_target_percent = 2; /* Hardcode 2% for now. */
774 sclk_setting->SSc_En = 0;
775 if (ss_target_percent) {
776 sclk_setting->SSc_En = 1;
777 ss_target_freq = clock - (clock * ss_target_percent / 100);
778 sclk_setting->Fcw1_int = (uint16_t)
779 ((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) /
780 ref_clock);
781 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
782 temp <<= 0x10;
783 do_div(temp, ref_clock);
784 sclk_setting->Fcw1_frac = temp & 0xffff;
785 }
786
787 return 0;
788 }
789
vegam_get_sleep_divider_id_from_clock(uint32_t clock,uint32_t clock_insr)790 static uint8_t vegam_get_sleep_divider_id_from_clock(uint32_t clock,
791 uint32_t clock_insr)
792 {
793 uint8_t i;
794 uint32_t temp;
795 uint32_t min = max(clock_insr, (uint32_t)SMU7_MINIMUM_ENGINE_CLOCK);
796
797 PP_ASSERT_WITH_CODE((clock >= min),
798 "Engine clock can't satisfy stutter requirement!",
799 return 0);
800 for (i = 31; ; i--) {
801 temp = clock / (i + 1);
802
803 if (temp >= min || i == 0)
804 break;
805 }
806 return i;
807 }
808
vegam_populate_single_graphic_level(struct pp_hwmgr * hwmgr,uint32_t clock,struct SMU75_Discrete_GraphicsLevel * level)809 static int vegam_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
810 uint32_t clock, struct SMU75_Discrete_GraphicsLevel *level)
811 {
812 int result;
813 /* PP_Clocks minClocks; */
814 uint32_t mvdd;
815 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
816 struct phm_ppt_v1_information *table_info =
817 (struct phm_ppt_v1_information *)(hwmgr->pptable);
818 SMU_SclkSetting curr_sclk_setting = { 0 };
819
820 result = vegam_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
821
822 /* populate graphics levels */
823 result = vegam_get_dependency_volt_by_clk(hwmgr,
824 table_info->vdd_dep_on_sclk, clock,
825 &level->MinVoltage, &mvdd);
826
827 PP_ASSERT_WITH_CODE((0 == result),
828 "can not find VDDC voltage value for "
829 "VDDC engine clock dependency table",
830 return result);
831 level->ActivityLevel = (uint16_t)(SclkDPMTuning_VEGAM >> DPMTuning_Activity_Shift);
832
833 level->CcPwrDynRm = 0;
834 level->CcPwrDynRm1 = 0;
835 level->EnabledForActivity = 0;
836 level->EnabledForThrottle = 1;
837 level->VoltageDownHyst = 0;
838 level->PowerThrottle = 0;
839 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
840
841 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
842 level->DeepSleepDivId = vegam_get_sleep_divider_id_from_clock(clock,
843 hwmgr->display_config->min_core_set_clock_in_sr);
844
845 level->SclkSetting = curr_sclk_setting;
846
847 CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
848 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
849 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
850 CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
851 CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
852 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
853 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
854 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
855 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
856 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
857 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
858 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
859 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
860 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
861 return 0;
862 }
863
vegam_populate_all_graphic_levels(struct pp_hwmgr * hwmgr)864 static int vegam_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
865 {
866 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
867 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
868 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
869 struct phm_ppt_v1_information *table_info =
870 (struct phm_ppt_v1_information *)(hwmgr->pptable);
871 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
872 uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count;
873 int result = 0;
874 uint32_t array = smu_data->smu7_data.dpm_table_start +
875 offsetof(SMU75_Discrete_DpmTable, GraphicsLevel);
876 uint32_t array_size = sizeof(struct SMU75_Discrete_GraphicsLevel) *
877 SMU75_MAX_LEVELS_GRAPHICS;
878 struct SMU75_Discrete_GraphicsLevel *levels =
879 smu_data->smc_state_table.GraphicsLevel;
880 uint32_t i, max_entry;
881 uint8_t hightest_pcie_level_enabled = 0,
882 lowest_pcie_level_enabled = 0,
883 mid_pcie_level_enabled = 0,
884 count = 0;
885
886 vegam_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table));
887
888 for (i = 0; i < dpm_table->sclk_table.count; i++) {
889
890 result = vegam_populate_single_graphic_level(hwmgr,
891 dpm_table->sclk_table.dpm_levels[i].value,
892 &(smu_data->smc_state_table.GraphicsLevel[i]));
893 if (result)
894 return result;
895
896 levels[i].UpHyst = (uint8_t)
897 (SclkDPMTuning_VEGAM >> DPMTuning_Uphyst_Shift);
898 levels[i].DownHyst = (uint8_t)
899 (SclkDPMTuning_VEGAM >> DPMTuning_Downhyst_Shift);
900 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
901 if (i > 1)
902 levels[i].DeepSleepDivId = 0;
903 }
904 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
905 PHM_PlatformCaps_SPLLShutdownSupport))
906 smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
907
908 smu_data->smc_state_table.GraphicsDpmLevelCount =
909 (uint8_t)dpm_table->sclk_table.count;
910 hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask =
911 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
912
913 for (i = 0; i < dpm_table->sclk_table.count; i++)
914 levels[i].EnabledForActivity =
915 (hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask >> i) & 0x1;
916
917 if (pcie_table != NULL) {
918 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
919 "There must be 1 or more PCIE levels defined in PPTable.",
920 return -EINVAL);
921 max_entry = pcie_entry_cnt - 1;
922 for (i = 0; i < dpm_table->sclk_table.count; i++)
923 levels[i].pcieDpmLevel =
924 (uint8_t) ((i < max_entry) ? i : max_entry);
925 } else {
926 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
927 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
928 (1 << (hightest_pcie_level_enabled + 1))) != 0))
929 hightest_pcie_level_enabled++;
930
931 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
932 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
933 (1 << lowest_pcie_level_enabled)) == 0))
934 lowest_pcie_level_enabled++;
935
936 while ((count < hightest_pcie_level_enabled) &&
937 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
938 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
939 count++;
940
941 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
942 hightest_pcie_level_enabled ?
943 (lowest_pcie_level_enabled + 1 + count) :
944 hightest_pcie_level_enabled;
945
946 /* set pcieDpmLevel to hightest_pcie_level_enabled */
947 for (i = 2; i < dpm_table->sclk_table.count; i++)
948 levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
949
950 /* set pcieDpmLevel to lowest_pcie_level_enabled */
951 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
952
953 /* set pcieDpmLevel to mid_pcie_level_enabled */
954 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
955 }
956 /* level count will send to smc once at init smc table and never change */
957 result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
958 (uint32_t)array_size, SMC_RAM_END);
959
960 return result;
961 }
962
vegam_calculate_mclk_params(struct pp_hwmgr * hwmgr,uint32_t clock,struct SMU75_Discrete_MemoryLevel * mem_level)963 static int vegam_calculate_mclk_params(struct pp_hwmgr *hwmgr,
964 uint32_t clock, struct SMU75_Discrete_MemoryLevel *mem_level)
965 {
966 struct pp_atomctrl_memory_clock_param_ai mpll_param;
967
968 PP_ASSERT_WITH_CODE(!atomctrl_get_memory_pll_dividers_ai(hwmgr,
969 clock, &mpll_param),
970 "Failed to retrieve memory pll parameter.",
971 return -EINVAL);
972
973 mem_level->MclkFrequency = (uint32_t)mpll_param.ulClock;
974 mem_level->Fcw_int = (uint16_t)mpll_param.ulMclk_fcw_int;
975 mem_level->Fcw_frac = (uint16_t)mpll_param.ulMclk_fcw_frac;
976 mem_level->Postdiv = (uint8_t)mpll_param.ulPostDiv;
977
978 return 0;
979 }
980
vegam_populate_single_memory_level(struct pp_hwmgr * hwmgr,uint32_t clock,struct SMU75_Discrete_MemoryLevel * mem_level)981 static int vegam_populate_single_memory_level(struct pp_hwmgr *hwmgr,
982 uint32_t clock, struct SMU75_Discrete_MemoryLevel *mem_level)
983 {
984 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
985 struct phm_ppt_v1_information *table_info =
986 (struct phm_ppt_v1_information *)(hwmgr->pptable);
987 int result = 0;
988 uint32_t mclk_stutter_mode_threshold = 60000;
989
990
991 if (table_info->vdd_dep_on_mclk) {
992 result = vegam_get_dependency_volt_by_clk(hwmgr,
993 table_info->vdd_dep_on_mclk, clock,
994 &mem_level->MinVoltage, &mem_level->MinMvdd);
995 PP_ASSERT_WITH_CODE(!result,
996 "can not find MinVddc voltage value from memory "
997 "VDDC voltage dependency table", return result);
998 }
999
1000 result = vegam_calculate_mclk_params(hwmgr, clock, mem_level);
1001 PP_ASSERT_WITH_CODE(!result,
1002 "Failed to calculate mclk params.",
1003 return -EINVAL);
1004
1005 mem_level->EnabledForThrottle = 1;
1006 mem_level->EnabledForActivity = 0;
1007 mem_level->VoltageDownHyst = 0;
1008 mem_level->ActivityLevel = (uint16_t)
1009 (MemoryDPMTuning_VEGAM >> DPMTuning_Activity_Shift);
1010 mem_level->StutterEnable = false;
1011 mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1012
1013 data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1014
1015 if (mclk_stutter_mode_threshold &&
1016 (clock <= mclk_stutter_mode_threshold) &&
1017 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1018 STUTTER_ENABLE) & 0x1))
1019 mem_level->StutterEnable = true;
1020
1021 if (!result) {
1022 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1023 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1024 CONVERT_FROM_HOST_TO_SMC_US(mem_level->Fcw_int);
1025 CONVERT_FROM_HOST_TO_SMC_US(mem_level->Fcw_frac);
1026 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1027 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1028 }
1029
1030 return result;
1031 }
1032
vegam_populate_all_memory_levels(struct pp_hwmgr * hwmgr)1033 static int vegam_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1034 {
1035 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1036 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1037 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
1038 int result;
1039 /* populate MCLK dpm table to SMU7 */
1040 uint32_t array = smu_data->smu7_data.dpm_table_start +
1041 offsetof(SMU75_Discrete_DpmTable, MemoryLevel);
1042 uint32_t array_size = sizeof(SMU75_Discrete_MemoryLevel) *
1043 SMU75_MAX_LEVELS_MEMORY;
1044 struct SMU75_Discrete_MemoryLevel *levels =
1045 smu_data->smc_state_table.MemoryLevel;
1046 uint32_t i;
1047
1048 for (i = 0; i < dpm_table->mclk_table.count; i++) {
1049 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1050 "can not populate memory level as memory clock is zero",
1051 return -EINVAL);
1052 result = vegam_populate_single_memory_level(hwmgr,
1053 dpm_table->mclk_table.dpm_levels[i].value,
1054 &levels[i]);
1055
1056 if (result)
1057 return result;
1058
1059 levels[i].UpHyst = (uint8_t)
1060 (MemoryDPMTuning_VEGAM >> DPMTuning_Uphyst_Shift);
1061 levels[i].DownHyst = (uint8_t)
1062 (MemoryDPMTuning_VEGAM >> DPMTuning_Downhyst_Shift);
1063 }
1064
1065 smu_data->smc_state_table.MemoryDpmLevelCount =
1066 (uint8_t)dpm_table->mclk_table.count;
1067 hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1068 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1069
1070 for (i = 0; i < dpm_table->mclk_table.count; i++)
1071 levels[i].EnabledForActivity =
1072 (hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask >> i) & 0x1;
1073
1074 levels[dpm_table->mclk_table.count - 1].DisplayWatermark =
1075 PPSMC_DISPLAY_WATERMARK_HIGH;
1076
1077 /* level count will send to smc once at init smc table and never change */
1078 result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
1079 (uint32_t)array_size, SMC_RAM_END);
1080
1081 return result;
1082 }
1083
vegam_populate_mvdd_value(struct pp_hwmgr * hwmgr,uint32_t mclk,SMIO_Pattern * smio_pat)1084 static int vegam_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1085 uint32_t mclk, SMIO_Pattern *smio_pat)
1086 {
1087 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1088 struct phm_ppt_v1_information *table_info =
1089 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1090 uint32_t i = 0;
1091
1092 if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1093 /* find mvdd value which clock is more than request */
1094 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1095 if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1096 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1097 break;
1098 }
1099 }
1100 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1101 "MVDD Voltage is outside the supported range.",
1102 return -EINVAL);
1103 } else
1104 return -EINVAL;
1105
1106 return 0;
1107 }
1108
vegam_populate_smc_acpi_level(struct pp_hwmgr * hwmgr,SMU75_Discrete_DpmTable * table)1109 static int vegam_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1110 SMU75_Discrete_DpmTable *table)
1111 {
1112 int result = 0;
1113 uint32_t sclk_frequency;
1114 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1115 struct phm_ppt_v1_information *table_info =
1116 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1117 SMIO_Pattern vol_level;
1118 uint32_t mvdd;
1119 uint16_t us_mvdd;
1120
1121 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1122
1123 /* Get MinVoltage and Frequency from DPM0,
1124 * already converted to SMC_UL */
1125 sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
1126 result = vegam_get_dependency_volt_by_clk(hwmgr,
1127 table_info->vdd_dep_on_sclk,
1128 sclk_frequency,
1129 &table->ACPILevel.MinVoltage, &mvdd);
1130 PP_ASSERT_WITH_CODE(!result,
1131 "Cannot find ACPI VDDC voltage value "
1132 "in Clock Dependency Table",
1133 );
1134
1135 result = vegam_calculate_sclk_params(hwmgr, sclk_frequency,
1136 &(table->ACPILevel.SclkSetting));
1137 PP_ASSERT_WITH_CODE(!result,
1138 "Error retrieving Engine Clock dividers from VBIOS.",
1139 return result);
1140
1141 table->ACPILevel.DeepSleepDivId = 0;
1142 table->ACPILevel.CcPwrDynRm = 0;
1143 table->ACPILevel.CcPwrDynRm1 = 0;
1144
1145 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1146 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1147 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1148 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1149
1150 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1151 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1152 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1153 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
1154 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1155 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1156 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
1157 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1158 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
1159 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
1160
1161
1162 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1163 table->MemoryACPILevel.MclkFrequency = data->vbios_boot_state.mclk_bootup_value;
1164 result = vegam_get_dependency_volt_by_clk(hwmgr,
1165 table_info->vdd_dep_on_mclk,
1166 table->MemoryACPILevel.MclkFrequency,
1167 &table->MemoryACPILevel.MinVoltage, &mvdd);
1168 PP_ASSERT_WITH_CODE((0 == result),
1169 "Cannot find ACPI VDDCI voltage value "
1170 "in Clock Dependency Table",
1171 );
1172
1173 us_mvdd = 0;
1174 if ((SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
1175 (data->mclk_dpm_key_disabled))
1176 us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
1177 else {
1178 if (!vegam_populate_mvdd_value(hwmgr,
1179 data->dpm_table.mclk_table.dpm_levels[0].value,
1180 &vol_level))
1181 us_mvdd = vol_level.Voltage;
1182 }
1183
1184 if (!vegam_populate_mvdd_value(hwmgr, 0, &vol_level))
1185 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1186 else
1187 table->MemoryACPILevel.MinMvdd = 0;
1188
1189 table->MemoryACPILevel.StutterEnable = false;
1190
1191 table->MemoryACPILevel.EnabledForThrottle = 0;
1192 table->MemoryACPILevel.EnabledForActivity = 0;
1193 table->MemoryACPILevel.UpHyst = 0;
1194 table->MemoryACPILevel.DownHyst = 100;
1195 table->MemoryACPILevel.VoltageDownHyst = 0;
1196 table->MemoryACPILevel.ActivityLevel =
1197 PP_HOST_TO_SMC_US(data->current_profile_setting.mclk_activity);
1198
1199 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1200 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1201
1202 return result;
1203 }
1204
vegam_populate_smc_vce_level(struct pp_hwmgr * hwmgr,SMU75_Discrete_DpmTable * table)1205 static int vegam_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1206 SMU75_Discrete_DpmTable *table)
1207 {
1208 int result = -EINVAL;
1209 uint8_t count;
1210 struct pp_atomctrl_clock_dividers_vi dividers;
1211 struct phm_ppt_v1_information *table_info =
1212 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1213 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1214 table_info->mm_dep_table;
1215 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1216 uint32_t vddci;
1217
1218 table->VceLevelCount = (uint8_t)(mm_table->count);
1219 table->VceBootLevel = 0;
1220
1221 for (count = 0; count < table->VceLevelCount; count++) {
1222 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1223 table->VceLevel[count].MinVoltage = 0;
1224 table->VceLevel[count].MinVoltage |=
1225 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1226
1227 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1228 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1229 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1230 else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1231 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1232 else
1233 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1234
1235
1236 table->VceLevel[count].MinVoltage |=
1237 (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1238 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1239
1240 /*retrieve divider value for VBIOS */
1241 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1242 table->VceLevel[count].Frequency, ÷rs);
1243 PP_ASSERT_WITH_CODE((0 == result),
1244 "can not find divide id for VCE engine clock",
1245 return result);
1246
1247 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1248
1249 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1250 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1251 }
1252 return result;
1253 }
1254
vegam_populate_memory_timing_parameters(struct pp_hwmgr * hwmgr,int32_t eng_clock,int32_t mem_clock,SMU75_Discrete_MCArbDramTimingTableEntry * arb_regs)1255 static int vegam_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1256 int32_t eng_clock, int32_t mem_clock,
1257 SMU75_Discrete_MCArbDramTimingTableEntry *arb_regs)
1258 {
1259 uint32_t dram_timing;
1260 uint32_t dram_timing2;
1261 uint32_t burst_time;
1262 uint32_t rfsh_rate;
1263 uint32_t misc3;
1264
1265 int result;
1266
1267 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1268 eng_clock, mem_clock);
1269 PP_ASSERT_WITH_CODE(result == 0,
1270 "Error calling VBIOS to set DRAM_TIMING.",
1271 return result);
1272
1273 dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1274 dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1275 burst_time = cgs_read_register(hwmgr->device, mmMC_ARB_BURST_TIME);
1276 rfsh_rate = cgs_read_register(hwmgr->device, mmMC_ARB_RFSH_RATE);
1277 misc3 = cgs_read_register(hwmgr->device, mmMC_ARB_MISC3);
1278
1279 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
1280 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1281 arb_regs->McArbBurstTime = PP_HOST_TO_SMC_UL(burst_time);
1282 arb_regs->McArbRfshRate = PP_HOST_TO_SMC_UL(rfsh_rate);
1283 arb_regs->McArbMisc3 = PP_HOST_TO_SMC_UL(misc3);
1284
1285 return 0;
1286 }
1287
vegam_program_memory_timing_parameters(struct pp_hwmgr * hwmgr)1288 static int vegam_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1289 {
1290 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1291 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1292 struct SMU75_Discrete_MCArbDramTimingTable arb_regs;
1293 uint32_t i, j;
1294 int result = 0;
1295
1296 memset(&arb_regs, 0, sizeof(SMU75_Discrete_MCArbDramTimingTable));
1297
1298 for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) {
1299 for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) {
1300 result = vegam_populate_memory_timing_parameters(hwmgr,
1301 hw_data->dpm_table.sclk_table.dpm_levels[i].value,
1302 hw_data->dpm_table.mclk_table.dpm_levels[j].value,
1303 &arb_regs.entries[i][j]);
1304 if (result)
1305 return result;
1306 }
1307 }
1308
1309 result = smu7_copy_bytes_to_smc(
1310 hwmgr,
1311 smu_data->smu7_data.arb_table_start,
1312 (uint8_t *)&arb_regs,
1313 sizeof(SMU75_Discrete_MCArbDramTimingTable),
1314 SMC_RAM_END);
1315 return result;
1316 }
1317
vegam_populate_smc_uvd_level(struct pp_hwmgr * hwmgr,struct SMU75_Discrete_DpmTable * table)1318 static int vegam_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1319 struct SMU75_Discrete_DpmTable *table)
1320 {
1321 int result = -EINVAL;
1322 uint8_t count;
1323 struct pp_atomctrl_clock_dividers_vi dividers;
1324 struct phm_ppt_v1_information *table_info =
1325 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1326 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1327 table_info->mm_dep_table;
1328 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1329 uint32_t vddci;
1330
1331 table->UvdLevelCount = (uint8_t)(mm_table->count);
1332 table->UvdBootLevel = 0;
1333
1334 for (count = 0; count < table->UvdLevelCount; count++) {
1335 table->UvdLevel[count].MinVoltage = 0;
1336 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1337 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1338 table->UvdLevel[count].MinVoltage |=
1339 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1340
1341 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1342 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1343 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1344 else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1345 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1346 else
1347 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1348
1349 table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1350 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1351
1352 /* retrieve divider value for VBIOS */
1353 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1354 table->UvdLevel[count].VclkFrequency, ÷rs);
1355 PP_ASSERT_WITH_CODE((0 == result),
1356 "can not find divide id for Vclk clock", return result);
1357
1358 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1359
1360 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1361 table->UvdLevel[count].DclkFrequency, ÷rs);
1362 PP_ASSERT_WITH_CODE((0 == result),
1363 "can not find divide id for Dclk clock", return result);
1364
1365 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1366
1367 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1368 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1369 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1370 }
1371
1372 return result;
1373 }
1374
vegam_populate_smc_boot_level(struct pp_hwmgr * hwmgr,struct SMU75_Discrete_DpmTable * table)1375 static int vegam_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1376 struct SMU75_Discrete_DpmTable *table)
1377 {
1378 int result = 0;
1379 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1380
1381 table->GraphicsBootLevel = 0;
1382 table->MemoryBootLevel = 0;
1383
1384 /* find boot level from dpm table */
1385 result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1386 data->vbios_boot_state.sclk_bootup_value,
1387 (uint32_t *)&(table->GraphicsBootLevel));
1388
1389 result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1390 data->vbios_boot_state.mclk_bootup_value,
1391 (uint32_t *)&(table->MemoryBootLevel));
1392
1393 table->BootVddc = data->vbios_boot_state.vddc_bootup_value *
1394 VOLTAGE_SCALE;
1395 table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1396 VOLTAGE_SCALE;
1397 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *
1398 VOLTAGE_SCALE;
1399
1400 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1401 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1402 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1403
1404 return 0;
1405 }
1406
vegam_populate_smc_initial_state(struct pp_hwmgr * hwmgr)1407 static int vegam_populate_smc_initial_state(struct pp_hwmgr *hwmgr)
1408 {
1409 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1410 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1411 struct phm_ppt_v1_information *table_info =
1412 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1413 uint8_t count, level;
1414
1415 count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1416
1417 for (level = 0; level < count; level++) {
1418 if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1419 hw_data->vbios_boot_state.sclk_bootup_value) {
1420 smu_data->smc_state_table.GraphicsBootLevel = level;
1421 break;
1422 }
1423 }
1424
1425 count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1426 for (level = 0; level < count; level++) {
1427 if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1428 hw_data->vbios_boot_state.mclk_bootup_value) {
1429 smu_data->smc_state_table.MemoryBootLevel = level;
1430 break;
1431 }
1432 }
1433
1434 return 0;
1435 }
1436
scale_fan_gain_settings(uint16_t raw_setting)1437 static uint16_t scale_fan_gain_settings(uint16_t raw_setting)
1438 {
1439 uint32_t tmp;
1440 tmp = raw_setting * 4096 / 100;
1441 return (uint16_t)tmp;
1442 }
1443
vegam_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr * hwmgr)1444 static int vegam_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
1445 {
1446 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1447
1448 const struct vegam_pt_defaults *defaults = smu_data->power_tune_defaults;
1449 SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1450 struct phm_ppt_v1_information *table_info =
1451 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1452 struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
1453 struct pp_advance_fan_control_parameters *fan_table =
1454 &hwmgr->thermal_controller.advanceFanControlParameters;
1455 int i, j, k;
1456 const uint16_t *pdef1;
1457 const uint16_t *pdef2;
1458
1459 table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
1460 table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
1461
1462 PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
1463 "Target Operating Temp is out of Range!",
1464 );
1465
1466 table->TemperatureLimitEdge = PP_HOST_TO_SMC_US(
1467 cac_dtp_table->usTargetOperatingTemp * 256);
1468 table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US(
1469 cac_dtp_table->usTemperatureLimitHotspot * 256);
1470 table->FanGainEdge = PP_HOST_TO_SMC_US(
1471 scale_fan_gain_settings(fan_table->usFanGainEdge));
1472 table->FanGainHotspot = PP_HOST_TO_SMC_US(
1473 scale_fan_gain_settings(fan_table->usFanGainHotspot));
1474
1475 pdef1 = defaults->BAPMTI_R;
1476 pdef2 = defaults->BAPMTI_RC;
1477
1478 for (i = 0; i < SMU75_DTE_ITERATIONS; i++) {
1479 for (j = 0; j < SMU75_DTE_SOURCES; j++) {
1480 for (k = 0; k < SMU75_DTE_SINKS; k++) {
1481 table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1);
1482 table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2);
1483 pdef1++;
1484 pdef2++;
1485 }
1486 }
1487 }
1488
1489 return 0;
1490 }
1491
vegam_populate_clock_stretcher_data_table(struct pp_hwmgr * hwmgr)1492 static int vegam_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1493 {
1494 uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
1495 struct vegam_smumgr *smu_data =
1496 (struct vegam_smumgr *)(hwmgr->smu_backend);
1497
1498 uint8_t i, stretch_amount, stretch_amount2, volt_offset = 0;
1499 struct phm_ppt_v1_information *table_info =
1500 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1501 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1502 table_info->vdd_dep_on_sclk;
1503 uint32_t mask = (1 << ((STRAP_ASIC_RO_MSB - STRAP_ASIC_RO_LSB) + 1)) - 1;
1504
1505 stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1506
1507 atomctrl_read_efuse(hwmgr, STRAP_ASIC_RO_LSB, STRAP_ASIC_RO_MSB,
1508 mask, &efuse);
1509
1510 min = 1200;
1511 max = 2500;
1512
1513 ro = efuse * (max - min) / 255 + min;
1514
1515 /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1516 for (i = 0; i < sclk_table->count; i++) {
1517 smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1518 sclk_table->entries[i].cks_enable << i;
1519 volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) *
1520 136418 - (ro - 70) * 1000000) /
1521 (2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000));
1522 volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 *
1523 3232 - (ro - 65) * 1000000) /
1524 (2522480 - sclk_table->entries[i].clk/100 * 115764/100));
1525
1526 if (volt_without_cks >= volt_with_cks)
1527 volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1528 sclk_table->entries[i].cks_voffset) * 100 + 624) / 625);
1529
1530 smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1531 }
1532
1533 smu_data->smc_state_table.LdoRefSel =
1534 (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ?
1535 table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 5;
1536 /* Populate CKS Lookup Table */
1537 if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
1538 stretch_amount2 = 0;
1539 else if (stretch_amount == 3 || stretch_amount == 4)
1540 stretch_amount2 = 1;
1541 else {
1542 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1543 PHM_PlatformCaps_ClockStretcher);
1544 PP_ASSERT_WITH_CODE(false,
1545 "Stretch Amount in PPTable not supported\n",
1546 return -EINVAL);
1547 }
1548
1549 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1550 value &= 0xFFFFFFFE;
1551 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1552
1553 return 0;
1554 }
1555
vegam_is_hw_avfs_present(struct pp_hwmgr * hwmgr)1556 static bool vegam_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
1557 {
1558 uint32_t efuse;
1559
1560 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1561 ixSMU_EFUSE_0 + (49 * 4));
1562 efuse &= 0x00000001;
1563
1564 if (efuse)
1565 return true;
1566
1567 return false;
1568 }
1569
vegam_populate_avfs_parameters(struct pp_hwmgr * hwmgr)1570 static int vegam_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1571 {
1572 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1573 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1574
1575 SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1576 int result = 0;
1577 struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
1578 AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
1579 AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
1580 uint32_t tmp, i;
1581
1582 struct phm_ppt_v1_information *table_info =
1583 (struct phm_ppt_v1_information *)hwmgr->pptable;
1584 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1585 table_info->vdd_dep_on_sclk;
1586
1587 if (!hwmgr->avfs_supported)
1588 return 0;
1589
1590 result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
1591
1592 if (0 == result) {
1593 table->BTCGB_VDROOP_TABLE[0].a0 =
1594 PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
1595 table->BTCGB_VDROOP_TABLE[0].a1 =
1596 PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
1597 table->BTCGB_VDROOP_TABLE[0].a2 =
1598 PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
1599 table->BTCGB_VDROOP_TABLE[1].a0 =
1600 PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
1601 table->BTCGB_VDROOP_TABLE[1].a1 =
1602 PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
1603 table->BTCGB_VDROOP_TABLE[1].a2 =
1604 PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
1605 table->AVFSGB_FUSE_TABLE[0].m1 =
1606 PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
1607 table->AVFSGB_FUSE_TABLE[0].m2 =
1608 PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
1609 table->AVFSGB_FUSE_TABLE[0].b =
1610 PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
1611 table->AVFSGB_FUSE_TABLE[0].m1_shift = 24;
1612 table->AVFSGB_FUSE_TABLE[0].m2_shift = 12;
1613 table->AVFSGB_FUSE_TABLE[1].m1 =
1614 PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
1615 table->AVFSGB_FUSE_TABLE[1].m2 =
1616 PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
1617 table->AVFSGB_FUSE_TABLE[1].b =
1618 PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
1619 table->AVFSGB_FUSE_TABLE[1].m1_shift = 24;
1620 table->AVFSGB_FUSE_TABLE[1].m2_shift = 12;
1621 table->MaxVoltage = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
1622 AVFS_meanNsigma.Aconstant[0] =
1623 PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
1624 AVFS_meanNsigma.Aconstant[1] =
1625 PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
1626 AVFS_meanNsigma.Aconstant[2] =
1627 PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
1628 AVFS_meanNsigma.DC_tol_sigma =
1629 PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
1630 AVFS_meanNsigma.Platform_mean =
1631 PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
1632 AVFS_meanNsigma.PSM_Age_CompFactor =
1633 PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
1634 AVFS_meanNsigma.Platform_sigma =
1635 PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
1636
1637 for (i = 0; i < sclk_table->count; i++) {
1638 AVFS_meanNsigma.Static_Voltage_Offset[i] =
1639 (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
1640 AVFS_SclkOffset.Sclk_Offset[i] =
1641 PP_HOST_TO_SMC_US((uint16_t)
1642 (sclk_table->entries[i].sclk_offset) / 100);
1643 }
1644
1645 result = smu7_read_smc_sram_dword(hwmgr,
1646 SMU7_FIRMWARE_HEADER_LOCATION +
1647 offsetof(SMU75_Firmware_Header, AvfsMeanNSigma),
1648 &tmp, SMC_RAM_END);
1649 smu7_copy_bytes_to_smc(hwmgr,
1650 tmp,
1651 (uint8_t *)&AVFS_meanNsigma,
1652 sizeof(AVFS_meanNsigma_t),
1653 SMC_RAM_END);
1654
1655 result = smu7_read_smc_sram_dword(hwmgr,
1656 SMU7_FIRMWARE_HEADER_LOCATION +
1657 offsetof(SMU75_Firmware_Header, AvfsSclkOffsetTable),
1658 &tmp, SMC_RAM_END);
1659 smu7_copy_bytes_to_smc(hwmgr,
1660 tmp,
1661 (uint8_t *)&AVFS_SclkOffset,
1662 sizeof(AVFS_Sclk_Offset_t),
1663 SMC_RAM_END);
1664
1665 data->avfs_vdroop_override_setting =
1666 (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
1667 (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
1668 (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
1669 (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
1670 data->apply_avfs_cks_off_voltage =
1671 (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
1672 }
1673 return result;
1674 }
1675
vegam_populate_vr_config(struct pp_hwmgr * hwmgr,struct SMU75_Discrete_DpmTable * table)1676 static int vegam_populate_vr_config(struct pp_hwmgr *hwmgr,
1677 struct SMU75_Discrete_DpmTable *table)
1678 {
1679 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1680 struct vegam_smumgr *smu_data =
1681 (struct vegam_smumgr *)(hwmgr->smu_backend);
1682 uint16_t config;
1683
1684 config = VR_MERGED_WITH_VDDC;
1685 table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1686
1687 /* Set Vddc Voltage Controller */
1688 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1689 config = VR_SVI2_PLANE_1;
1690 table->VRConfig |= config;
1691 } else {
1692 PP_ASSERT_WITH_CODE(false,
1693 "VDDC should be on SVI2 control in merged mode!",
1694 );
1695 }
1696 /* Set Vddci Voltage Controller */
1697 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1698 config = VR_SVI2_PLANE_2; /* only in merged mode */
1699 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1700 } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1701 config = VR_SMIO_PATTERN_1;
1702 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1703 } else {
1704 config = VR_STATIC_VOLTAGE;
1705 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1706 }
1707 /* Set Mvdd Voltage Controller */
1708 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1709 if (config != VR_SVI2_PLANE_2) {
1710 config = VR_SVI2_PLANE_2;
1711 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1712 cgs_write_ind_register(hwmgr->device,
1713 CGS_IND_REG__SMC,
1714 smu_data->smu7_data.soft_regs_start +
1715 offsetof(SMU75_SoftRegisters, AllowMvddSwitch),
1716 0x1);
1717 } else {
1718 PP_ASSERT_WITH_CODE(false,
1719 "SVI2 Plane 2 is already taken, set MVDD as Static",);
1720 config = VR_STATIC_VOLTAGE;
1721 table->VRConfig = (config << VRCONF_MVDD_SHIFT);
1722 }
1723 } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1724 config = VR_SMIO_PATTERN_2;
1725 table->VRConfig = (config << VRCONF_MVDD_SHIFT);
1726 cgs_write_ind_register(hwmgr->device,
1727 CGS_IND_REG__SMC,
1728 smu_data->smu7_data.soft_regs_start +
1729 offsetof(SMU75_SoftRegisters, AllowMvddSwitch),
1730 0x1);
1731 } else {
1732 config = VR_STATIC_VOLTAGE;
1733 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1734 }
1735
1736 return 0;
1737 }
1738
vegam_populate_svi_load_line(struct pp_hwmgr * hwmgr)1739 static int vegam_populate_svi_load_line(struct pp_hwmgr *hwmgr)
1740 {
1741 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1742 const struct vegam_pt_defaults *defaults = smu_data->power_tune_defaults;
1743
1744 smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
1745 smu_data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
1746 smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
1747 smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
1748
1749 return 0;
1750 }
1751
vegam_populate_tdc_limit(struct pp_hwmgr * hwmgr)1752 static int vegam_populate_tdc_limit(struct pp_hwmgr *hwmgr)
1753 {
1754 uint16_t tdc_limit;
1755 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1756 struct phm_ppt_v1_information *table_info =
1757 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1758 const struct vegam_pt_defaults *defaults = smu_data->power_tune_defaults;
1759
1760 tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128);
1761 smu_data->power_tune_table.TDC_VDDC_PkgLimit =
1762 CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
1763 smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
1764 defaults->TDC_VDDC_ThrottleReleaseLimitPerc;
1765 smu_data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt;
1766
1767 return 0;
1768 }
1769
vegam_populate_dw8(struct pp_hwmgr * hwmgr,uint32_t fuse_table_offset)1770 static int vegam_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
1771 {
1772 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1773 const struct vegam_pt_defaults *defaults = smu_data->power_tune_defaults;
1774 uint32_t temp;
1775
1776 if (smu7_read_smc_sram_dword(hwmgr,
1777 fuse_table_offset +
1778 offsetof(SMU75_Discrete_PmFuses, TdcWaterfallCtl),
1779 (uint32_t *)&temp, SMC_RAM_END))
1780 PP_ASSERT_WITH_CODE(false,
1781 "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
1782 return -EINVAL);
1783 else {
1784 smu_data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl;
1785 smu_data->power_tune_table.LPMLTemperatureMin =
1786 (uint8_t)((temp >> 16) & 0xff);
1787 smu_data->power_tune_table.LPMLTemperatureMax =
1788 (uint8_t)((temp >> 8) & 0xff);
1789 smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);
1790 }
1791 return 0;
1792 }
1793
vegam_populate_temperature_scaler(struct pp_hwmgr * hwmgr)1794 static int vegam_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
1795 {
1796 int i;
1797 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1798
1799 /* Currently not used. Set all to zero. */
1800 for (i = 0; i < 16; i++)
1801 smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0;
1802
1803 return 0;
1804 }
1805
vegam_populate_fuzzy_fan(struct pp_hwmgr * hwmgr)1806 static int vegam_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
1807 {
1808 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1809
1810 /* TO DO move to hwmgr */
1811 if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15))
1812 || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity)
1813 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
1814 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity;
1815
1816 smu_data->power_tune_table.FuzzyFan_PwmSetDelta = PP_HOST_TO_SMC_US(
1817 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity);
1818 return 0;
1819 }
1820
vegam_populate_gnb_lpml(struct pp_hwmgr * hwmgr)1821 static int vegam_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
1822 {
1823 int i;
1824 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1825
1826 /* Currently not used. Set all to zero. */
1827 for (i = 0; i < 16; i++)
1828 smu_data->power_tune_table.GnbLPML[i] = 0;
1829
1830 return 0;
1831 }
1832
vegam_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr * hwmgr)1833 static int vegam_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
1834 {
1835 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1836 struct phm_ppt_v1_information *table_info =
1837 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1838 uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
1839 uint16_t lo_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
1840 struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
1841
1842 hi_sidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
1843 lo_sidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
1844
1845 smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
1846 CONVERT_FROM_HOST_TO_SMC_US(hi_sidd);
1847 smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
1848 CONVERT_FROM_HOST_TO_SMC_US(lo_sidd);
1849
1850 return 0;
1851 }
1852
vegam_populate_pm_fuses(struct pp_hwmgr * hwmgr)1853 static int vegam_populate_pm_fuses(struct pp_hwmgr *hwmgr)
1854 {
1855 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1856 uint32_t pm_fuse_table_offset;
1857
1858 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1859 PHM_PlatformCaps_PowerContainment)) {
1860 if (smu7_read_smc_sram_dword(hwmgr,
1861 SMU7_FIRMWARE_HEADER_LOCATION +
1862 offsetof(SMU75_Firmware_Header, PmFuseTable),
1863 &pm_fuse_table_offset, SMC_RAM_END))
1864 PP_ASSERT_WITH_CODE(false,
1865 "Attempt to get pm_fuse_table_offset Failed!",
1866 return -EINVAL);
1867
1868 if (vegam_populate_svi_load_line(hwmgr))
1869 PP_ASSERT_WITH_CODE(false,
1870 "Attempt to populate SviLoadLine Failed!",
1871 return -EINVAL);
1872
1873 if (vegam_populate_tdc_limit(hwmgr))
1874 PP_ASSERT_WITH_CODE(false,
1875 "Attempt to populate TDCLimit Failed!", return -EINVAL);
1876
1877 if (vegam_populate_dw8(hwmgr, pm_fuse_table_offset))
1878 PP_ASSERT_WITH_CODE(false,
1879 "Attempt to populate TdcWaterfallCtl, "
1880 "LPMLTemperature Min and Max Failed!",
1881 return -EINVAL);
1882
1883 if (0 != vegam_populate_temperature_scaler(hwmgr))
1884 PP_ASSERT_WITH_CODE(false,
1885 "Attempt to populate LPMLTemperatureScaler Failed!",
1886 return -EINVAL);
1887
1888 if (vegam_populate_fuzzy_fan(hwmgr))
1889 PP_ASSERT_WITH_CODE(false,
1890 "Attempt to populate Fuzzy Fan Control parameters Failed!",
1891 return -EINVAL);
1892
1893 if (vegam_populate_gnb_lpml(hwmgr))
1894 PP_ASSERT_WITH_CODE(false,
1895 "Attempt to populate GnbLPML Failed!",
1896 return -EINVAL);
1897
1898 if (vegam_populate_bapm_vddc_base_leakage_sidd(hwmgr))
1899 PP_ASSERT_WITH_CODE(false,
1900 "Attempt to populate BapmVddCBaseLeakage Hi and Lo "
1901 "Sidd Failed!", return -EINVAL);
1902
1903 if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
1904 (uint8_t *)&smu_data->power_tune_table,
1905 (sizeof(struct SMU75_Discrete_PmFuses) - PMFUSES_AVFSSIZE),
1906 SMC_RAM_END))
1907 PP_ASSERT_WITH_CODE(false,
1908 "Attempt to download PmFuseTable Failed!",
1909 return -EINVAL);
1910 }
1911 return 0;
1912 }
1913
vegam_enable_reconfig_cus(struct pp_hwmgr * hwmgr)1914 static int vegam_enable_reconfig_cus(struct pp_hwmgr *hwmgr)
1915 {
1916 struct amdgpu_device *adev = hwmgr->adev;
1917
1918 smum_send_msg_to_smc_with_parameter(hwmgr,
1919 PPSMC_MSG_EnableModeSwitchRLCNotification,
1920 adev->gfx.cu_info.number);
1921
1922 return 0;
1923 }
1924
vegam_init_smc_table(struct pp_hwmgr * hwmgr)1925 static int vegam_init_smc_table(struct pp_hwmgr *hwmgr)
1926 {
1927 int result;
1928 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1929 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1930
1931 struct phm_ppt_v1_information *table_info =
1932 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1933 struct SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1934 uint8_t i;
1935 struct pp_atomctrl_gpio_pin_assignment gpio_pin;
1936 struct phm_ppt_v1_gpio_table *gpio_table =
1937 (struct phm_ppt_v1_gpio_table *)table_info->gpio_table;
1938 pp_atomctrl_clock_dividers_vi dividers;
1939
1940 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1941 PHM_PlatformCaps_AutomaticDCTransition);
1942
1943 vegam_initialize_power_tune_defaults(hwmgr);
1944
1945 if (SMU7_VOLTAGE_CONTROL_NONE != hw_data->voltage_control)
1946 vegam_populate_smc_voltage_tables(hwmgr, table);
1947
1948 table->SystemFlags = 0;
1949 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1950 PHM_PlatformCaps_AutomaticDCTransition))
1951 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1952
1953 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1954 PHM_PlatformCaps_StepVddc))
1955 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1956
1957 if (hw_data->is_memory_gddr5)
1958 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1959
1960 if (hw_data->ulv_supported && table_info->us_ulv_voltage_offset) {
1961 result = vegam_populate_ulv_state(hwmgr, table);
1962 PP_ASSERT_WITH_CODE(!result,
1963 "Failed to initialize ULV state!", return result);
1964 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1965 ixCG_ULV_PARAMETER, SMU7_CGULVPARAMETER_DFLT);
1966 }
1967
1968 result = vegam_populate_smc_link_level(hwmgr, table);
1969 PP_ASSERT_WITH_CODE(!result,
1970 "Failed to initialize Link Level!", return result);
1971
1972 result = vegam_populate_all_graphic_levels(hwmgr);
1973 PP_ASSERT_WITH_CODE(!result,
1974 "Failed to initialize Graphics Level!", return result);
1975
1976 result = vegam_populate_all_memory_levels(hwmgr);
1977 PP_ASSERT_WITH_CODE(!result,
1978 "Failed to initialize Memory Level!", return result);
1979
1980 result = vegam_populate_smc_acpi_level(hwmgr, table);
1981 PP_ASSERT_WITH_CODE(!result,
1982 "Failed to initialize ACPI Level!", return result);
1983
1984 result = vegam_populate_smc_vce_level(hwmgr, table);
1985 PP_ASSERT_WITH_CODE(!result,
1986 "Failed to initialize VCE Level!", return result);
1987
1988 /* Since only the initial state is completely set up at this point
1989 * (the other states are just copies of the boot state) we only
1990 * need to populate the ARB settings for the initial state.
1991 */
1992 result = vegam_program_memory_timing_parameters(hwmgr);
1993 PP_ASSERT_WITH_CODE(!result,
1994 "Failed to Write ARB settings for the initial state.", return result);
1995
1996 result = vegam_populate_smc_uvd_level(hwmgr, table);
1997 PP_ASSERT_WITH_CODE(!result,
1998 "Failed to initialize UVD Level!", return result);
1999
2000 result = vegam_populate_smc_boot_level(hwmgr, table);
2001 PP_ASSERT_WITH_CODE(!result,
2002 "Failed to initialize Boot Level!", return result);
2003
2004 result = vegam_populate_smc_initial_state(hwmgr);
2005 PP_ASSERT_WITH_CODE(!result,
2006 "Failed to initialize Boot State!", return result);
2007
2008 result = vegam_populate_bapm_parameters_in_dpm_table(hwmgr);
2009 PP_ASSERT_WITH_CODE(!result,
2010 "Failed to populate BAPM Parameters!", return result);
2011
2012 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2013 PHM_PlatformCaps_ClockStretcher)) {
2014 result = vegam_populate_clock_stretcher_data_table(hwmgr);
2015 PP_ASSERT_WITH_CODE(!result,
2016 "Failed to populate Clock Stretcher Data Table!",
2017 return result);
2018 }
2019
2020 result = vegam_populate_avfs_parameters(hwmgr);
2021 PP_ASSERT_WITH_CODE(!result,
2022 "Failed to populate AVFS Parameters!", return result;);
2023
2024 table->CurrSclkPllRange = 0xff;
2025 table->GraphicsVoltageChangeEnable = 1;
2026 table->GraphicsThermThrottleEnable = 1;
2027 table->GraphicsInterval = 1;
2028 table->VoltageInterval = 1;
2029 table->ThermalInterval = 1;
2030 table->TemperatureLimitHigh =
2031 table_info->cac_dtp_table->usTargetOperatingTemp *
2032 SMU7_Q88_FORMAT_CONVERSION_UNIT;
2033 table->TemperatureLimitLow =
2034 (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2035 SMU7_Q88_FORMAT_CONVERSION_UNIT;
2036 table->MemoryVoltageChangeEnable = 1;
2037 table->MemoryInterval = 1;
2038 table->VoltageResponseTime = 0;
2039 table->PhaseResponseTime = 0;
2040 table->MemoryThermThrottleEnable = 1;
2041
2042 PP_ASSERT_WITH_CODE(hw_data->dpm_table.pcie_speed_table.count >= 1,
2043 "There must be 1 or more PCIE levels defined in PPTable.",
2044 return -EINVAL);
2045 table->PCIeBootLinkLevel =
2046 hw_data->dpm_table.pcie_speed_table.count;
2047 table->PCIeGenInterval = 1;
2048 table->VRConfig = 0;
2049
2050 result = vegam_populate_vr_config(hwmgr, table);
2051 PP_ASSERT_WITH_CODE(!result,
2052 "Failed to populate VRConfig setting!", return result);
2053
2054 table->ThermGpio = 17;
2055 table->SclkStepSize = 0x4000;
2056
2057 if (atomctrl_get_pp_assign_pin(hwmgr,
2058 VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2059 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2060 if (gpio_table)
2061 table->VRHotLevel =
2062 table_info->gpio_table->vrhot_triggered_sclk_dpm_index;
2063 } else {
2064 table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
2065 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2066 PHM_PlatformCaps_RegulatorHot);
2067 }
2068
2069 if (atomctrl_get_pp_assign_pin(hwmgr,
2070 PP_AC_DC_SWITCH_GPIO_PINID, &gpio_pin)) {
2071 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2072 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2073 PHM_PlatformCaps_AutomaticDCTransition) &&
2074 !smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UseNewGPIOScheme))
2075 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2076 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
2077 } else {
2078 table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
2079 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2080 PHM_PlatformCaps_AutomaticDCTransition);
2081 }
2082
2083 /* Thermal Output GPIO */
2084 if (atomctrl_get_pp_assign_pin(hwmgr,
2085 THERMAL_INT_OUTPUT_GPIO_PINID, &gpio_pin)) {
2086 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2087
2088 /* For porlarity read GPIOPAD_A with assigned Gpio pin
2089 * since VBIOS will program this register to set 'inactive state',
2090 * driver can then determine 'active state' from this and
2091 * program SMU with correct polarity
2092 */
2093 table->ThermOutPolarity =
2094 (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
2095 (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2096 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2097
2098 /* if required, combine VRHot/PCC with thermal out GPIO */
2099 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2100 PHM_PlatformCaps_RegulatorHot) &&
2101 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2102 PHM_PlatformCaps_CombinePCCWithThermalSignal))
2103 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2104 } else {
2105 table->ThermOutGpio = 17;
2106 table->ThermOutPolarity = 1;
2107 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2108 }
2109
2110 /* Populate BIF_SCLK levels into SMC DPM table */
2111 for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) {
2112 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2113 smu_data->bif_sclk_table[i], ÷rs);
2114 PP_ASSERT_WITH_CODE(!result,
2115 "Can not find DFS divide id for Sclk",
2116 return result);
2117
2118 if (i == 0)
2119 table->Ulv.BifSclkDfs =
2120 PP_HOST_TO_SMC_US((uint16_t)(dividers.pll_post_divider));
2121 else
2122 table->LinkLevel[i - 1].BifSclkDfs =
2123 PP_HOST_TO_SMC_US((uint16_t)(dividers.pll_post_divider));
2124 }
2125
2126 for (i = 0; i < SMU75_MAX_ENTRIES_SMIO; i++)
2127 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2128
2129 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2130 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2131 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2132 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2133 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2134 CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
2135 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2136 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2137 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2138 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2139
2140 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2141 result = smu7_copy_bytes_to_smc(hwmgr,
2142 smu_data->smu7_data.dpm_table_start +
2143 offsetof(SMU75_Discrete_DpmTable, SystemFlags),
2144 (uint8_t *)&(table->SystemFlags),
2145 sizeof(SMU75_Discrete_DpmTable) - 3 * sizeof(SMU75_PIDController),
2146 SMC_RAM_END);
2147 PP_ASSERT_WITH_CODE(!result,
2148 "Failed to upload dpm data to SMC memory!", return result);
2149
2150 result = vegam_populate_pm_fuses(hwmgr);
2151 PP_ASSERT_WITH_CODE(!result,
2152 "Failed to populate PM fuses to SMC memory!", return result);
2153
2154 result = vegam_enable_reconfig_cus(hwmgr);
2155 PP_ASSERT_WITH_CODE(!result,
2156 "Failed to enable reconfigurable CUs!", return result);
2157
2158 return 0;
2159 }
2160
vegam_get_offsetof(uint32_t type,uint32_t member)2161 static uint32_t vegam_get_offsetof(uint32_t type, uint32_t member)
2162 {
2163 switch (type) {
2164 case SMU_SoftRegisters:
2165 switch (member) {
2166 case HandshakeDisables:
2167 return offsetof(SMU75_SoftRegisters, HandshakeDisables);
2168 case VoltageChangeTimeout:
2169 return offsetof(SMU75_SoftRegisters, VoltageChangeTimeout);
2170 case AverageGraphicsActivity:
2171 return offsetof(SMU75_SoftRegisters, AverageGraphicsActivity);
2172 case PreVBlankGap:
2173 return offsetof(SMU75_SoftRegisters, PreVBlankGap);
2174 case VBlankTimeout:
2175 return offsetof(SMU75_SoftRegisters, VBlankTimeout);
2176 case UcodeLoadStatus:
2177 return offsetof(SMU75_SoftRegisters, UcodeLoadStatus);
2178 case DRAM_LOG_ADDR_H:
2179 return offsetof(SMU75_SoftRegisters, DRAM_LOG_ADDR_H);
2180 case DRAM_LOG_ADDR_L:
2181 return offsetof(SMU75_SoftRegisters, DRAM_LOG_ADDR_L);
2182 case DRAM_LOG_PHY_ADDR_H:
2183 return offsetof(SMU75_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
2184 case DRAM_LOG_PHY_ADDR_L:
2185 return offsetof(SMU75_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
2186 case DRAM_LOG_BUFF_SIZE:
2187 return offsetof(SMU75_SoftRegisters, DRAM_LOG_BUFF_SIZE);
2188 }
2189 break;
2190 case SMU_Discrete_DpmTable:
2191 switch (member) {
2192 case UvdBootLevel:
2193 return offsetof(SMU75_Discrete_DpmTable, UvdBootLevel);
2194 case VceBootLevel:
2195 return offsetof(SMU75_Discrete_DpmTable, VceBootLevel);
2196 case LowSclkInterruptThreshold:
2197 return offsetof(SMU75_Discrete_DpmTable, LowSclkInterruptThreshold);
2198 }
2199 break;
2200 }
2201 pr_warn("can't get the offset of type %x member %x\n", type, member);
2202 return 0;
2203 }
2204
vegam_program_mem_timing_parameters(struct pp_hwmgr * hwmgr)2205 static int vegam_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
2206 {
2207 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2208
2209 if (data->need_update_smu7_dpm_table &
2210 (DPMTABLE_OD_UPDATE_SCLK +
2211 DPMTABLE_UPDATE_SCLK +
2212 DPMTABLE_UPDATE_MCLK))
2213 return vegam_program_memory_timing_parameters(hwmgr);
2214
2215 return 0;
2216 }
2217
vegam_update_sclk_threshold(struct pp_hwmgr * hwmgr)2218 static int vegam_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2219 {
2220 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2221 struct vegam_smumgr *smu_data =
2222 (struct vegam_smumgr *)(hwmgr->smu_backend);
2223 int result = 0;
2224 uint32_t low_sclk_interrupt_threshold = 0;
2225
2226 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2227 PHM_PlatformCaps_SclkThrottleLowNotification)
2228 && (data->low_sclk_interrupt_threshold != 0)) {
2229 low_sclk_interrupt_threshold =
2230 data->low_sclk_interrupt_threshold;
2231
2232 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
2233
2234 result = smu7_copy_bytes_to_smc(
2235 hwmgr,
2236 smu_data->smu7_data.dpm_table_start +
2237 offsetof(SMU75_Discrete_DpmTable,
2238 LowSclkInterruptThreshold),
2239 (uint8_t *)&low_sclk_interrupt_threshold,
2240 sizeof(uint32_t),
2241 SMC_RAM_END);
2242 }
2243 PP_ASSERT_WITH_CODE((result == 0),
2244 "Failed to update SCLK threshold!", return result);
2245
2246 result = vegam_program_mem_timing_parameters(hwmgr);
2247 PP_ASSERT_WITH_CODE((result == 0),
2248 "Failed to program memory timing parameters!",
2249 );
2250
2251 return result;
2252 }
2253
2254 int vegam_thermal_avfs_enable(struct pp_hwmgr *hwmgr);
vegam_thermal_avfs_enable(struct pp_hwmgr * hwmgr)2255 int vegam_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
2256 {
2257 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2258 int ret;
2259
2260 if (!hwmgr->avfs_supported)
2261 return 0;
2262
2263 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs);
2264 if (!ret) {
2265 if (data->apply_avfs_cks_off_voltage)
2266 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ApplyAvfsCksOffVoltage);
2267 }
2268
2269 return ret;
2270 }
2271
vegam_thermal_setup_fan_table(struct pp_hwmgr * hwmgr)2272 static int vegam_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2273 {
2274 PP_ASSERT_WITH_CODE(hwmgr->thermal_controller.fanInfo.bNoFan,
2275 "VBIOS fan info is not correct!",
2276 );
2277 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2278 PHM_PlatformCaps_MicrocodeFanControl);
2279 return 0;
2280 }
2281
2282 const struct pp_smumgr_func vegam_smu_funcs = {
2283 .smu_init = vegam_smu_init,
2284 .smu_fini = smu7_smu_fini,
2285 .start_smu = vegam_start_smu,
2286 .check_fw_load_finish = smu7_check_fw_load_finish,
2287 .request_smu_load_fw = smu7_reload_firmware,
2288 .request_smu_load_specific_fw = NULL,
2289 .send_msg_to_smc = smu7_send_msg_to_smc,
2290 .send_msg_to_smc_with_parameter = smu7_send_msg_to_smc_with_parameter,
2291 .process_firmware_header = vegam_process_firmware_header,
2292 .is_dpm_running = vegam_is_dpm_running,
2293 .get_mac_definition = vegam_get_mac_definition,
2294 .update_smc_table = vegam_update_smc_table,
2295 .init_smc_table = vegam_init_smc_table,
2296 .get_offsetof = vegam_get_offsetof,
2297 .populate_all_graphic_levels = vegam_populate_all_graphic_levels,
2298 .populate_all_memory_levels = vegam_populate_all_memory_levels,
2299 .update_sclk_threshold = vegam_update_sclk_threshold,
2300 .is_hw_avfs_present = vegam_is_hw_avfs_present,
2301 .thermal_avfs_enable = vegam_thermal_avfs_enable,
2302 .thermal_setup_fan_table = vegam_thermal_setup_fan_table,
2303 };
2304