xref: /dragonfly/contrib/gcc-4.7/gcc/reload1.c (revision e4b17023)
1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2    Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3    1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4    2011, 2012 Free Software Foundation, Inc.
5 
6 This file is part of GCC.
7 
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
11 version.
12 
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
16 for more details.
17 
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3.  If not see
20 <http://www.gnu.org/licenses/>.  */
21 
22 #include "config.h"
23 #include "system.h"
24 #include "coretypes.h"
25 #include "tm.h"
26 
27 #include "machmode.h"
28 #include "hard-reg-set.h"
29 #include "rtl-error.h"
30 #include "tm_p.h"
31 #include "obstack.h"
32 #include "insn-config.h"
33 #include "ggc.h"
34 #include "flags.h"
35 #include "function.h"
36 #include "expr.h"
37 #include "optabs.h"
38 #include "regs.h"
39 #include "addresses.h"
40 #include "basic-block.h"
41 #include "df.h"
42 #include "reload.h"
43 #include "recog.h"
44 #include "output.h"
45 #include "except.h"
46 #include "tree.h"
47 #include "ira.h"
48 #include "target.h"
49 #include "emit-rtl.h"
50 
51 /* This file contains the reload pass of the compiler, which is
52    run after register allocation has been done.  It checks that
53    each insn is valid (operands required to be in registers really
54    are in registers of the proper class) and fixes up invalid ones
55    by copying values temporarily into registers for the insns
56    that need them.
57 
58    The results of register allocation are described by the vector
59    reg_renumber; the insns still contain pseudo regs, but reg_renumber
60    can be used to find which hard reg, if any, a pseudo reg is in.
61 
62    The technique we always use is to free up a few hard regs that are
63    called ``reload regs'', and for each place where a pseudo reg
64    must be in a hard reg, copy it temporarily into one of the reload regs.
65 
66    Reload regs are allocated locally for every instruction that needs
67    reloads.  When there are pseudos which are allocated to a register that
68    has been chosen as a reload reg, such pseudos must be ``spilled''.
69    This means that they go to other hard regs, or to stack slots if no other
70    available hard regs can be found.  Spilling can invalidate more
71    insns, requiring additional need for reloads, so we must keep checking
72    until the process stabilizes.
73 
74    For machines with different classes of registers, we must keep track
75    of the register class needed for each reload, and make sure that
76    we allocate enough reload registers of each class.
77 
78    The file reload.c contains the code that checks one insn for
79    validity and reports the reloads that it needs.  This file
80    is in charge of scanning the entire rtl code, accumulating the
81    reload needs, spilling, assigning reload registers to use for
82    fixing up each insn, and generating the new insns to copy values
83    into the reload registers.  */
84 
85 struct target_reload default_target_reload;
86 #if SWITCHABLE_TARGET
87 struct target_reload *this_target_reload = &default_target_reload;
88 #endif
89 
90 #define spill_indirect_levels			\
91   (this_target_reload->x_spill_indirect_levels)
92 
93 /* During reload_as_needed, element N contains a REG rtx for the hard reg
94    into which reg N has been reloaded (perhaps for a previous insn).  */
95 static rtx *reg_last_reload_reg;
96 
97 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
98    for an output reload that stores into reg N.  */
99 static regset_head reg_has_output_reload;
100 
101 /* Indicates which hard regs are reload-registers for an output reload
102    in the current insn.  */
103 static HARD_REG_SET reg_is_output_reload;
104 
105 /* Widest width in which each pseudo reg is referred to (via subreg).  */
106 static unsigned int *reg_max_ref_width;
107 
108 /* Vector to remember old contents of reg_renumber before spilling.  */
109 static short *reg_old_renumber;
110 
111 /* During reload_as_needed, element N contains the last pseudo regno reloaded
112    into hard register N.  If that pseudo reg occupied more than one register,
113    reg_reloaded_contents points to that pseudo for each spill register in
114    use; all of these must remain set for an inheritance to occur.  */
115 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
116 
117 /* During reload_as_needed, element N contains the insn for which
118    hard register N was last used.   Its contents are significant only
119    when reg_reloaded_valid is set for this register.  */
120 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
121 
122 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid.  */
123 static HARD_REG_SET reg_reloaded_valid;
124 /* Indicate if the register was dead at the end of the reload.
125    This is only valid if reg_reloaded_contents is set and valid.  */
126 static HARD_REG_SET reg_reloaded_dead;
127 
128 /* Indicate whether the register's current value is one that is not
129    safe to retain across a call, even for registers that are normally
130    call-saved.  This is only meaningful for members of reg_reloaded_valid.  */
131 static HARD_REG_SET reg_reloaded_call_part_clobbered;
132 
133 /* Number of spill-regs so far; number of valid elements of spill_regs.  */
134 static int n_spills;
135 
136 /* In parallel with spill_regs, contains REG rtx's for those regs.
137    Holds the last rtx used for any given reg, or 0 if it has never
138    been used for spilling yet.  This rtx is reused, provided it has
139    the proper mode.  */
140 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
141 
142 /* In parallel with spill_regs, contains nonzero for a spill reg
143    that was stored after the last time it was used.
144    The precise value is the insn generated to do the store.  */
145 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
146 
147 /* This is the register that was stored with spill_reg_store.  This is a
148    copy of reload_out / reload_out_reg when the value was stored; if
149    reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg.  */
150 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
151 
152 /* This table is the inverse mapping of spill_regs:
153    indexed by hard reg number,
154    it contains the position of that reg in spill_regs,
155    or -1 for something that is not in spill_regs.
156 
157    ?!?  This is no longer accurate.  */
158 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
159 
160 /* This reg set indicates registers that can't be used as spill registers for
161    the currently processed insn.  These are the hard registers which are live
162    during the insn, but not allocated to pseudos, as well as fixed
163    registers.  */
164 static HARD_REG_SET bad_spill_regs;
165 
166 /* These are the hard registers that can't be used as spill register for any
167    insn.  This includes registers used for user variables and registers that
168    we can't eliminate.  A register that appears in this set also can't be used
169    to retry register allocation.  */
170 static HARD_REG_SET bad_spill_regs_global;
171 
172 /* Describes order of use of registers for reloading
173    of spilled pseudo-registers.  `n_spills' is the number of
174    elements that are actually valid; new ones are added at the end.
175 
176    Both spill_regs and spill_reg_order are used on two occasions:
177    once during find_reload_regs, where they keep track of the spill registers
178    for a single insn, but also during reload_as_needed where they show all
179    the registers ever used by reload.  For the latter case, the information
180    is calculated during finish_spills.  */
181 static short spill_regs[FIRST_PSEUDO_REGISTER];
182 
183 /* This vector of reg sets indicates, for each pseudo, which hard registers
184    may not be used for retrying global allocation because the register was
185    formerly spilled from one of them.  If we allowed reallocating a pseudo to
186    a register that it was already allocated to, reload might not
187    terminate.  */
188 static HARD_REG_SET *pseudo_previous_regs;
189 
190 /* This vector of reg sets indicates, for each pseudo, which hard
191    registers may not be used for retrying global allocation because they
192    are used as spill registers during one of the insns in which the
193    pseudo is live.  */
194 static HARD_REG_SET *pseudo_forbidden_regs;
195 
196 /* All hard regs that have been used as spill registers for any insn are
197    marked in this set.  */
198 static HARD_REG_SET used_spill_regs;
199 
200 /* Index of last register assigned as a spill register.  We allocate in
201    a round-robin fashion.  */
202 static int last_spill_reg;
203 
204 /* Record the stack slot for each spilled hard register.  */
205 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
206 
207 /* Width allocated so far for that stack slot.  */
208 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
209 
210 /* Record which pseudos needed to be spilled.  */
211 static regset_head spilled_pseudos;
212 
213 /* Record which pseudos changed their allocation in finish_spills.  */
214 static regset_head changed_allocation_pseudos;
215 
216 /* Used for communication between order_regs_for_reload and count_pseudo.
217    Used to avoid counting one pseudo twice.  */
218 static regset_head pseudos_counted;
219 
220 /* First uid used by insns created by reload in this function.
221    Used in find_equiv_reg.  */
222 int reload_first_uid;
223 
224 /* Flag set by local-alloc or global-alloc if anything is live in
225    a call-clobbered reg across calls.  */
226 int caller_save_needed;
227 
228 /* Set to 1 while reload_as_needed is operating.
229    Required by some machines to handle any generated moves differently.  */
230 int reload_in_progress = 0;
231 
232 /* This obstack is used for allocation of rtl during register elimination.
233    The allocated storage can be freed once find_reloads has processed the
234    insn.  */
235 static struct obstack reload_obstack;
236 
237 /* Points to the beginning of the reload_obstack.  All insn_chain structures
238    are allocated first.  */
239 static char *reload_startobj;
240 
241 /* The point after all insn_chain structures.  Used to quickly deallocate
242    memory allocated in copy_reloads during calculate_needs_all_insns.  */
243 static char *reload_firstobj;
244 
245 /* This points before all local rtl generated by register elimination.
246    Used to quickly free all memory after processing one insn.  */
247 static char *reload_insn_firstobj;
248 
249 /* List of insn_chain instructions, one for every insn that reload needs to
250    examine.  */
251 struct insn_chain *reload_insn_chain;
252 
253 /* TRUE if we potentially left dead insns in the insn stream and want to
254    run DCE immediately after reload, FALSE otherwise.  */
255 static bool need_dce;
256 
257 /* List of all insns needing reloads.  */
258 static struct insn_chain *insns_need_reload;
259 
260 /* This structure is used to record information about register eliminations.
261    Each array entry describes one possible way of eliminating a register
262    in favor of another.   If there is more than one way of eliminating a
263    particular register, the most preferred should be specified first.  */
264 
265 struct elim_table
266 {
267   int from;			/* Register number to be eliminated.  */
268   int to;			/* Register number used as replacement.  */
269   HOST_WIDE_INT initial_offset;	/* Initial difference between values.  */
270   int can_eliminate;		/* Nonzero if this elimination can be done.  */
271   int can_eliminate_previous;	/* Value returned by TARGET_CAN_ELIMINATE
272 				   target hook in previous scan over insns
273 				   made by reload.  */
274   HOST_WIDE_INT offset;		/* Current offset between the two regs.  */
275   HOST_WIDE_INT previous_offset;/* Offset at end of previous insn.  */
276   int ref_outside_mem;		/* "to" has been referenced outside a MEM.  */
277   rtx from_rtx;			/* REG rtx for the register to be eliminated.
278 				   We cannot simply compare the number since
279 				   we might then spuriously replace a hard
280 				   register corresponding to a pseudo
281 				   assigned to the reg to be eliminated.  */
282   rtx to_rtx;			/* REG rtx for the replacement.  */
283 };
284 
285 static struct elim_table *reg_eliminate = 0;
286 
287 /* This is an intermediate structure to initialize the table.  It has
288    exactly the members provided by ELIMINABLE_REGS.  */
289 static const struct elim_table_1
290 {
291   const int from;
292   const int to;
293 } reg_eliminate_1[] =
294 
295 /* If a set of eliminable registers was specified, define the table from it.
296    Otherwise, default to the normal case of the frame pointer being
297    replaced by the stack pointer.  */
298 
299 #ifdef ELIMINABLE_REGS
300   ELIMINABLE_REGS;
301 #else
302   {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
303 #endif
304 
305 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
306 
307 /* Record the number of pending eliminations that have an offset not equal
308    to their initial offset.  If nonzero, we use a new copy of each
309    replacement result in any insns encountered.  */
310 int num_not_at_initial_offset;
311 
312 /* Count the number of registers that we may be able to eliminate.  */
313 static int num_eliminable;
314 /* And the number of registers that are equivalent to a constant that
315    can be eliminated to frame_pointer / arg_pointer + constant.  */
316 static int num_eliminable_invariants;
317 
318 /* For each label, we record the offset of each elimination.  If we reach
319    a label by more than one path and an offset differs, we cannot do the
320    elimination.  This information is indexed by the difference of the
321    number of the label and the first label number.  We can't offset the
322    pointer itself as this can cause problems on machines with segmented
323    memory.  The first table is an array of flags that records whether we
324    have yet encountered a label and the second table is an array of arrays,
325    one entry in the latter array for each elimination.  */
326 
327 static int first_label_num;
328 static char *offsets_known_at;
329 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
330 
331 VEC(reg_equivs_t,gc) *reg_equivs;
332 
333 /* Stack of addresses where an rtx has been changed.  We can undo the
334    changes by popping items off the stack and restoring the original
335    value at each location.
336 
337    We use this simplistic undo capability rather than copy_rtx as copy_rtx
338    will not make a deep copy of a normally sharable rtx, such as
339    (const (plus (symbol_ref) (const_int))).  If such an expression appears
340    as R1 in gen_reload_chain_without_interm_reg_p, then a shared
341    rtx expression would be changed.  See PR 42431.  */
342 
343 typedef rtx *rtx_p;
344 DEF_VEC_P(rtx_p);
345 DEF_VEC_ALLOC_P(rtx_p,heap);
346 static VEC(rtx_p,heap) *substitute_stack;
347 
348 /* Number of labels in the current function.  */
349 
350 static int num_labels;
351 
352 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
353 static void maybe_fix_stack_asms (void);
354 static void copy_reloads (struct insn_chain *);
355 static void calculate_needs_all_insns (int);
356 static int find_reg (struct insn_chain *, int);
357 static void find_reload_regs (struct insn_chain *);
358 static void select_reload_regs (void);
359 static void delete_caller_save_insns (void);
360 
361 static void spill_failure (rtx, enum reg_class);
362 static void count_spilled_pseudo (int, int, int);
363 static void delete_dead_insn (rtx);
364 static void alter_reg (int, int, bool);
365 static void set_label_offsets (rtx, rtx, int);
366 static void check_eliminable_occurrences (rtx);
367 static void elimination_effects (rtx, enum machine_mode);
368 static rtx eliminate_regs_1 (rtx, enum machine_mode, rtx, bool, bool);
369 static int eliminate_regs_in_insn (rtx, int);
370 static void update_eliminable_offsets (void);
371 static void mark_not_eliminable (rtx, const_rtx, void *);
372 static void set_initial_elim_offsets (void);
373 static bool verify_initial_elim_offsets (void);
374 static void set_initial_label_offsets (void);
375 static void set_offsets_for_label (rtx);
376 static void init_eliminable_invariants (rtx, bool);
377 static void init_elim_table (void);
378 static void free_reg_equiv (void);
379 static void update_eliminables (HARD_REG_SET *);
380 static void elimination_costs_in_insn (rtx);
381 static void spill_hard_reg (unsigned int, int);
382 static int finish_spills (int);
383 static void scan_paradoxical_subregs (rtx);
384 static void count_pseudo (int);
385 static void order_regs_for_reload (struct insn_chain *);
386 static void reload_as_needed (int);
387 static void forget_old_reloads_1 (rtx, const_rtx, void *);
388 static void forget_marked_reloads (regset);
389 static int reload_reg_class_lower (const void *, const void *);
390 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
391 				    enum machine_mode);
392 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
393 				     enum machine_mode);
394 static int reload_reg_free_p (unsigned int, int, enum reload_type);
395 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
396 					rtx, rtx, int, int);
397 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
398 			     rtx, rtx, int, int);
399 static int allocate_reload_reg (struct insn_chain *, int, int);
400 static int conflicts_with_override (rtx);
401 static void failed_reload (rtx, int);
402 static int set_reload_reg (int, int);
403 static void choose_reload_regs_init (struct insn_chain *, rtx *);
404 static void choose_reload_regs (struct insn_chain *);
405 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
406 				     rtx, int);
407 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
408 				      int);
409 static void do_input_reload (struct insn_chain *, struct reload *, int);
410 static void do_output_reload (struct insn_chain *, struct reload *, int);
411 static void emit_reload_insns (struct insn_chain *);
412 static void delete_output_reload (rtx, int, int, rtx);
413 static void delete_address_reloads (rtx, rtx);
414 static void delete_address_reloads_1 (rtx, rtx, rtx);
415 static void inc_for_reload (rtx, rtx, rtx, int);
416 #ifdef AUTO_INC_DEC
417 static void add_auto_inc_notes (rtx, rtx);
418 #endif
419 static void substitute (rtx *, const_rtx, rtx);
420 static bool gen_reload_chain_without_interm_reg_p (int, int);
421 static int reloads_conflict (int, int);
422 static rtx gen_reload (rtx, rtx, int, enum reload_type);
423 static rtx emit_insn_if_valid_for_reload (rtx);
424 
425 /* Initialize the reload pass.  This is called at the beginning of compilation
426    and may be called again if the target is reinitialized.  */
427 
428 void
init_reload(void)429 init_reload (void)
430 {
431   int i;
432 
433   /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
434      Set spill_indirect_levels to the number of levels such addressing is
435      permitted, zero if it is not permitted at all.  */
436 
437   rtx tem
438     = gen_rtx_MEM (Pmode,
439 		   gen_rtx_PLUS (Pmode,
440 				 gen_rtx_REG (Pmode,
441 					      LAST_VIRTUAL_REGISTER + 1),
442 				 GEN_INT (4)));
443   spill_indirect_levels = 0;
444 
445   while (memory_address_p (QImode, tem))
446     {
447       spill_indirect_levels++;
448       tem = gen_rtx_MEM (Pmode, tem);
449     }
450 
451   /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)).  */
452 
453   tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
454   indirect_symref_ok = memory_address_p (QImode, tem);
455 
456   /* See if reg+reg is a valid (and offsettable) address.  */
457 
458   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
459     {
460       tem = gen_rtx_PLUS (Pmode,
461 			  gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
462 			  gen_rtx_REG (Pmode, i));
463 
464       /* This way, we make sure that reg+reg is an offsettable address.  */
465       tem = plus_constant (tem, 4);
466 
467       if (memory_address_p (QImode, tem))
468 	{
469 	  double_reg_address_ok = 1;
470 	  break;
471 	}
472     }
473 
474   /* Initialize obstack for our rtl allocation.  */
475   gcc_obstack_init (&reload_obstack);
476   reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
477 
478   INIT_REG_SET (&spilled_pseudos);
479   INIT_REG_SET (&changed_allocation_pseudos);
480   INIT_REG_SET (&pseudos_counted);
481 }
482 
483 /* List of insn chains that are currently unused.  */
484 static struct insn_chain *unused_insn_chains = 0;
485 
486 /* Allocate an empty insn_chain structure.  */
487 struct insn_chain *
new_insn_chain(void)488 new_insn_chain (void)
489 {
490   struct insn_chain *c;
491 
492   if (unused_insn_chains == 0)
493     {
494       c = XOBNEW (&reload_obstack, struct insn_chain);
495       INIT_REG_SET (&c->live_throughout);
496       INIT_REG_SET (&c->dead_or_set);
497     }
498   else
499     {
500       c = unused_insn_chains;
501       unused_insn_chains = c->next;
502     }
503   c->is_caller_save_insn = 0;
504   c->need_operand_change = 0;
505   c->need_reload = 0;
506   c->need_elim = 0;
507   return c;
508 }
509 
510 /* Small utility function to set all regs in hard reg set TO which are
511    allocated to pseudos in regset FROM.  */
512 
513 void
compute_use_by_pseudos(HARD_REG_SET * to,regset from)514 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
515 {
516   unsigned int regno;
517   reg_set_iterator rsi;
518 
519   EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
520     {
521       int r = reg_renumber[regno];
522 
523       if (r < 0)
524 	{
525 	  /* reload_combine uses the information from DF_LIVE_IN,
526 	     which might still contain registers that have not
527 	     actually been allocated since they have an
528 	     equivalence.  */
529 	  gcc_assert (ira_conflicts_p || reload_completed);
530 	}
531       else
532 	add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
533     }
534 }
535 
536 /* Replace all pseudos found in LOC with their corresponding
537    equivalences.  */
538 
539 static void
replace_pseudos_in(rtx * loc,enum machine_mode mem_mode,rtx usage)540 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
541 {
542   rtx x = *loc;
543   enum rtx_code code;
544   const char *fmt;
545   int i, j;
546 
547   if (! x)
548     return;
549 
550   code = GET_CODE (x);
551   if (code == REG)
552     {
553       unsigned int regno = REGNO (x);
554 
555       if (regno < FIRST_PSEUDO_REGISTER)
556 	return;
557 
558       x = eliminate_regs_1 (x, mem_mode, usage, true, false);
559       if (x != *loc)
560 	{
561 	  *loc = x;
562 	  replace_pseudos_in (loc, mem_mode, usage);
563 	  return;
564 	}
565 
566       if (reg_equiv_constant (regno))
567 	*loc = reg_equiv_constant (regno);
568       else if (reg_equiv_invariant (regno))
569 	*loc = reg_equiv_invariant (regno);
570       else if (reg_equiv_mem (regno))
571 	*loc = reg_equiv_mem (regno);
572       else if (reg_equiv_address (regno))
573 	*loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address (regno));
574       else
575 	{
576 	  gcc_assert (!REG_P (regno_reg_rtx[regno])
577 		      || REGNO (regno_reg_rtx[regno]) != regno);
578 	  *loc = regno_reg_rtx[regno];
579 	}
580 
581       return;
582     }
583   else if (code == MEM)
584     {
585       replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
586       return;
587     }
588 
589   /* Process each of our operands recursively.  */
590   fmt = GET_RTX_FORMAT (code);
591   for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
592     if (*fmt == 'e')
593       replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
594     else if (*fmt == 'E')
595       for (j = 0; j < XVECLEN (x, i); j++)
596 	replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
597 }
598 
599 /* Determine if the current function has an exception receiver block
600    that reaches the exit block via non-exceptional edges  */
601 
602 static bool
has_nonexceptional_receiver(void)603 has_nonexceptional_receiver (void)
604 {
605   edge e;
606   edge_iterator ei;
607   basic_block *tos, *worklist, bb;
608 
609   /* If we're not optimizing, then just err on the safe side.  */
610   if (!optimize)
611     return true;
612 
613   /* First determine which blocks can reach exit via normal paths.  */
614   tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1);
615 
616   FOR_EACH_BB (bb)
617     bb->flags &= ~BB_REACHABLE;
618 
619   /* Place the exit block on our worklist.  */
620   EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
621   *tos++ = EXIT_BLOCK_PTR;
622 
623   /* Iterate: find everything reachable from what we've already seen.  */
624   while (tos != worklist)
625     {
626       bb = *--tos;
627 
628       FOR_EACH_EDGE (e, ei, bb->preds)
629 	if (!(e->flags & EDGE_ABNORMAL))
630 	  {
631 	    basic_block src = e->src;
632 
633 	    if (!(src->flags & BB_REACHABLE))
634 	      {
635 		src->flags |= BB_REACHABLE;
636 		*tos++ = src;
637 	      }
638 	  }
639     }
640   free (worklist);
641 
642   /* Now see if there's a reachable block with an exceptional incoming
643      edge.  */
644   FOR_EACH_BB (bb)
645     if (bb->flags & BB_REACHABLE && bb_has_abnormal_pred (bb))
646       return true;
647 
648   /* No exceptional block reached exit unexceptionally.  */
649   return false;
650 }
651 
652 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
653    zero elements) to MAX_REG_NUM elements.
654 
655    Initialize all new fields to NULL and update REG_EQUIVS_SIZE.  */
656 void
grow_reg_equivs(void)657 grow_reg_equivs (void)
658 {
659   int old_size = VEC_length (reg_equivs_t, reg_equivs);
660   int max_regno = max_reg_num ();
661   int i;
662 
663   VEC_reserve (reg_equivs_t, gc, reg_equivs, max_regno);
664   for (i = old_size; i < max_regno; i++)
665     {
666       VEC_quick_insert (reg_equivs_t, reg_equivs, i, 0);
667       memset (VEC_index (reg_equivs_t, reg_equivs, i), 0, sizeof (reg_equivs_t));
668     }
669 
670 }
671 
672 
673 /* Global variables used by reload and its subroutines.  */
674 
675 /* The current basic block while in calculate_elim_costs_all_insns.  */
676 static basic_block elim_bb;
677 
678 /* Set during calculate_needs if an insn needs register elimination.  */
679 static int something_needs_elimination;
680 /* Set during calculate_needs if an insn needs an operand changed.  */
681 static int something_needs_operands_changed;
682 /* Set by alter_regs if we spilled a register to the stack.  */
683 static bool something_was_spilled;
684 
685 /* Nonzero means we couldn't get enough spill regs.  */
686 static int failure;
687 
688 /* Temporary array of pseudo-register number.  */
689 static int *temp_pseudo_reg_arr;
690 
691 /* Main entry point for the reload pass.
692 
693    FIRST is the first insn of the function being compiled.
694 
695    GLOBAL nonzero means we were called from global_alloc
696    and should attempt to reallocate any pseudoregs that we
697    displace from hard regs we will use for reloads.
698    If GLOBAL is zero, we do not have enough information to do that,
699    so any pseudo reg that is spilled must go to the stack.
700 
701    Return value is TRUE if reload likely left dead insns in the
702    stream and a DCE pass should be run to elimiante them.  Else the
703    return value is FALSE.  */
704 
705 bool
reload(rtx first,int global)706 reload (rtx first, int global)
707 {
708   int i, n;
709   rtx insn;
710   struct elim_table *ep;
711   basic_block bb;
712   bool inserted;
713 
714   /* Make sure even insns with volatile mem refs are recognizable.  */
715   init_recog ();
716 
717   failure = 0;
718 
719   reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
720 
721   /* Make sure that the last insn in the chain
722      is not something that needs reloading.  */
723   emit_note (NOTE_INSN_DELETED);
724 
725   /* Enable find_equiv_reg to distinguish insns made by reload.  */
726   reload_first_uid = get_max_uid ();
727 
728 #ifdef SECONDARY_MEMORY_NEEDED
729   /* Initialize the secondary memory table.  */
730   clear_secondary_mem ();
731 #endif
732 
733   /* We don't have a stack slot for any spill reg yet.  */
734   memset (spill_stack_slot, 0, sizeof spill_stack_slot);
735   memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
736 
737   /* Initialize the save area information for caller-save, in case some
738      are needed.  */
739   init_save_areas ();
740 
741   /* Compute which hard registers are now in use
742      as homes for pseudo registers.
743      This is done here rather than (eg) in global_alloc
744      because this point is reached even if not optimizing.  */
745   for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
746     mark_home_live (i);
747 
748   /* A function that has a nonlocal label that can reach the exit
749      block via non-exceptional paths must save all call-saved
750      registers.  */
751   if (cfun->has_nonlocal_label
752       && has_nonexceptional_receiver ())
753     crtl->saves_all_registers = 1;
754 
755   if (crtl->saves_all_registers)
756     for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
757       if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
758 	df_set_regs_ever_live (i, true);
759 
760   /* Find all the pseudo registers that didn't get hard regs
761      but do have known equivalent constants or memory slots.
762      These include parameters (known equivalent to parameter slots)
763      and cse'd or loop-moved constant memory addresses.
764 
765      Record constant equivalents in reg_equiv_constant
766      so they will be substituted by find_reloads.
767      Record memory equivalents in reg_mem_equiv so they can
768      be substituted eventually by altering the REG-rtx's.  */
769 
770   grow_reg_equivs ();
771   reg_old_renumber = XCNEWVEC (short, max_regno);
772   memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
773   pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
774   pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
775 
776   CLEAR_HARD_REG_SET (bad_spill_regs_global);
777 
778   init_eliminable_invariants (first, true);
779   init_elim_table ();
780 
781   /* Alter each pseudo-reg rtx to contain its hard reg number.  Assign
782      stack slots to the pseudos that lack hard regs or equivalents.
783      Do not touch virtual registers.  */
784 
785   temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
786   for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
787     temp_pseudo_reg_arr[n++] = i;
788 
789   if (ira_conflicts_p)
790     /* Ask IRA to order pseudo-registers for better stack slot
791        sharing.  */
792     ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
793 
794   for (i = 0; i < n; i++)
795     alter_reg (temp_pseudo_reg_arr[i], -1, false);
796 
797   /* If we have some registers we think can be eliminated, scan all insns to
798      see if there is an insn that sets one of these registers to something
799      other than itself plus a constant.  If so, the register cannot be
800      eliminated.  Doing this scan here eliminates an extra pass through the
801      main reload loop in the most common case where register elimination
802      cannot be done.  */
803   for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
804     if (INSN_P (insn))
805       note_stores (PATTERN (insn), mark_not_eliminable, NULL);
806 
807   maybe_fix_stack_asms ();
808 
809   insns_need_reload = 0;
810   something_needs_elimination = 0;
811 
812   /* Initialize to -1, which means take the first spill register.  */
813   last_spill_reg = -1;
814 
815   /* Spill any hard regs that we know we can't eliminate.  */
816   CLEAR_HARD_REG_SET (used_spill_regs);
817   /* There can be multiple ways to eliminate a register;
818      they should be listed adjacently.
819      Elimination for any register fails only if all possible ways fail.  */
820   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; )
821     {
822       int from = ep->from;
823       int can_eliminate = 0;
824       do
825 	{
826           can_eliminate |= ep->can_eliminate;
827           ep++;
828 	}
829       while (ep < &reg_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
830       if (! can_eliminate)
831 	spill_hard_reg (from, 1);
832     }
833 
834 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
835   if (frame_pointer_needed)
836     spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
837 #endif
838   finish_spills (global);
839 
840   /* From now on, we may need to generate moves differently.  We may also
841      allow modifications of insns which cause them to not be recognized.
842      Any such modifications will be cleaned up during reload itself.  */
843   reload_in_progress = 1;
844 
845   /* This loop scans the entire function each go-round
846      and repeats until one repetition spills no additional hard regs.  */
847   for (;;)
848     {
849       int something_changed;
850       int did_spill;
851       HOST_WIDE_INT starting_frame_size;
852 
853       starting_frame_size = get_frame_size ();
854       something_was_spilled = false;
855 
856       set_initial_elim_offsets ();
857       set_initial_label_offsets ();
858 
859       /* For each pseudo register that has an equivalent location defined,
860 	 try to eliminate any eliminable registers (such as the frame pointer)
861 	 assuming initial offsets for the replacement register, which
862 	 is the normal case.
863 
864 	 If the resulting location is directly addressable, substitute
865 	 the MEM we just got directly for the old REG.
866 
867 	 If it is not addressable but is a constant or the sum of a hard reg
868 	 and constant, it is probably not addressable because the constant is
869 	 out of range, in that case record the address; we will generate
870 	 hairy code to compute the address in a register each time it is
871 	 needed.  Similarly if it is a hard register, but one that is not
872 	 valid as an address register.
873 
874 	 If the location is not addressable, but does not have one of the
875 	 above forms, assign a stack slot.  We have to do this to avoid the
876 	 potential of producing lots of reloads if, e.g., a location involves
877 	 a pseudo that didn't get a hard register and has an equivalent memory
878 	 location that also involves a pseudo that didn't get a hard register.
879 
880 	 Perhaps at some point we will improve reload_when_needed handling
881 	 so this problem goes away.  But that's very hairy.  */
882 
883       for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
884 	if (reg_renumber[i] < 0 && reg_equiv_memory_loc (i))
885 	  {
886 	    rtx x = eliminate_regs (reg_equiv_memory_loc (i), VOIDmode,
887 				    NULL_RTX);
888 
889 	    if (strict_memory_address_addr_space_p
890 		  (GET_MODE (regno_reg_rtx[i]), XEXP (x, 0),
891 		   MEM_ADDR_SPACE (x)))
892 	      reg_equiv_mem (i) = x, reg_equiv_address (i) = 0;
893 	    else if (CONSTANT_P (XEXP (x, 0))
894 		     || (REG_P (XEXP (x, 0))
895 			 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
896 		     || (GET_CODE (XEXP (x, 0)) == PLUS
897 			 && REG_P (XEXP (XEXP (x, 0), 0))
898 			 && (REGNO (XEXP (XEXP (x, 0), 0))
899 			     < FIRST_PSEUDO_REGISTER)
900 			 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
901 	      reg_equiv_address (i) = XEXP (x, 0), reg_equiv_mem (i) = 0;
902 	    else
903 	      {
904 		/* Make a new stack slot.  Then indicate that something
905 		   changed so we go back and recompute offsets for
906 		   eliminable registers because the allocation of memory
907 		   below might change some offset.  reg_equiv_{mem,address}
908 		   will be set up for this pseudo on the next pass around
909 		   the loop.  */
910 		reg_equiv_memory_loc (i) = 0;
911 		reg_equiv_init (i) = 0;
912 		alter_reg (i, -1, true);
913 	      }
914 	  }
915 
916       if (caller_save_needed)
917 	setup_save_areas ();
918 
919       /* If we allocated another stack slot, redo elimination bookkeeping.  */
920       if (something_was_spilled || starting_frame_size != get_frame_size ())
921 	continue;
922       if (starting_frame_size && crtl->stack_alignment_needed)
923 	{
924 	  /* If we have a stack frame, we must align it now.  The
925 	     stack size may be a part of the offset computation for
926 	     register elimination.  So if this changes the stack size,
927 	     then repeat the elimination bookkeeping.  We don't
928 	     realign when there is no stack, as that will cause a
929 	     stack frame when none is needed should
930 	     STARTING_FRAME_OFFSET not be already aligned to
931 	     STACK_BOUNDARY.  */
932 	  assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
933 	  if (starting_frame_size != get_frame_size ())
934 	    continue;
935 	}
936 
937       if (caller_save_needed)
938 	{
939 	  save_call_clobbered_regs ();
940 	  /* That might have allocated new insn_chain structures.  */
941 	  reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
942 	}
943 
944       calculate_needs_all_insns (global);
945 
946       if (! ira_conflicts_p)
947 	/* Don't do it for IRA.  We need this info because we don't
948 	   change live_throughout and dead_or_set for chains when IRA
949 	   is used.  */
950 	CLEAR_REG_SET (&spilled_pseudos);
951 
952       did_spill = 0;
953 
954       something_changed = 0;
955 
956       /* If we allocated any new memory locations, make another pass
957 	 since it might have changed elimination offsets.  */
958       if (something_was_spilled || starting_frame_size != get_frame_size ())
959 	something_changed = 1;
960 
961       /* Even if the frame size remained the same, we might still have
962 	 changed elimination offsets, e.g. if find_reloads called
963 	 force_const_mem requiring the back end to allocate a constant
964 	 pool base register that needs to be saved on the stack.  */
965       else if (!verify_initial_elim_offsets ())
966 	something_changed = 1;
967 
968       {
969 	HARD_REG_SET to_spill;
970 	CLEAR_HARD_REG_SET (to_spill);
971 	update_eliminables (&to_spill);
972 	AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
973 
974 	for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
975 	  if (TEST_HARD_REG_BIT (to_spill, i))
976 	    {
977 	      spill_hard_reg (i, 1);
978 	      did_spill = 1;
979 
980 	      /* Regardless of the state of spills, if we previously had
981 		 a register that we thought we could eliminate, but now can
982 		 not eliminate, we must run another pass.
983 
984 		 Consider pseudos which have an entry in reg_equiv_* which
985 		 reference an eliminable register.  We must make another pass
986 		 to update reg_equiv_* so that we do not substitute in the
987 		 old value from when we thought the elimination could be
988 		 performed.  */
989 	      something_changed = 1;
990 	    }
991       }
992 
993       select_reload_regs ();
994       if (failure)
995 	goto failed;
996 
997       if (insns_need_reload != 0 || did_spill)
998 	something_changed |= finish_spills (global);
999 
1000       if (! something_changed)
1001 	break;
1002 
1003       if (caller_save_needed)
1004 	delete_caller_save_insns ();
1005 
1006       obstack_free (&reload_obstack, reload_firstobj);
1007     }
1008 
1009   /* If global-alloc was run, notify it of any register eliminations we have
1010      done.  */
1011   if (global)
1012     for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1013       if (ep->can_eliminate)
1014 	mark_elimination (ep->from, ep->to);
1015 
1016   /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1017      If that insn didn't set the register (i.e., it copied the register to
1018      memory), just delete that insn instead of the equivalencing insn plus
1019      anything now dead.  If we call delete_dead_insn on that insn, we may
1020      delete the insn that actually sets the register if the register dies
1021      there and that is incorrect.  */
1022 
1023   for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1024     {
1025       if (reg_renumber[i] < 0 && reg_equiv_init (i) != 0)
1026 	{
1027 	  rtx list;
1028 	  for (list = reg_equiv_init (i); list; list = XEXP (list, 1))
1029 	    {
1030 	      rtx equiv_insn = XEXP (list, 0);
1031 
1032 	      /* If we already deleted the insn or if it may trap, we can't
1033 		 delete it.  The latter case shouldn't happen, but can
1034 		 if an insn has a variable address, gets a REG_EH_REGION
1035 		 note added to it, and then gets converted into a load
1036 		 from a constant address.  */
1037 	      if (NOTE_P (equiv_insn)
1038 		  || can_throw_internal (equiv_insn))
1039 		;
1040 	      else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1041 		delete_dead_insn (equiv_insn);
1042 	      else
1043 		SET_INSN_DELETED (equiv_insn);
1044 	    }
1045 	}
1046     }
1047 
1048   /* Use the reload registers where necessary
1049      by generating move instructions to move the must-be-register
1050      values into or out of the reload registers.  */
1051 
1052   if (insns_need_reload != 0 || something_needs_elimination
1053       || something_needs_operands_changed)
1054     {
1055       HOST_WIDE_INT old_frame_size = get_frame_size ();
1056 
1057       reload_as_needed (global);
1058 
1059       gcc_assert (old_frame_size == get_frame_size ());
1060 
1061       gcc_assert (verify_initial_elim_offsets ());
1062     }
1063 
1064   /* If we were able to eliminate the frame pointer, show that it is no
1065      longer live at the start of any basic block.  If it ls live by
1066      virtue of being in a pseudo, that pseudo will be marked live
1067      and hence the frame pointer will be known to be live via that
1068      pseudo.  */
1069 
1070   if (! frame_pointer_needed)
1071     FOR_EACH_BB (bb)
1072       bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1073 
1074   /* Come here (with failure set nonzero) if we can't get enough spill
1075      regs.  */
1076  failed:
1077 
1078   CLEAR_REG_SET (&changed_allocation_pseudos);
1079   CLEAR_REG_SET (&spilled_pseudos);
1080   reload_in_progress = 0;
1081 
1082   /* Now eliminate all pseudo regs by modifying them into
1083      their equivalent memory references.
1084      The REG-rtx's for the pseudos are modified in place,
1085      so all insns that used to refer to them now refer to memory.
1086 
1087      For a reg that has a reg_equiv_address, all those insns
1088      were changed by reloading so that no insns refer to it any longer;
1089      but the DECL_RTL of a variable decl may refer to it,
1090      and if so this causes the debugging info to mention the variable.  */
1091 
1092   for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1093     {
1094       rtx addr = 0;
1095 
1096       if (reg_equiv_mem (i))
1097 	addr = XEXP (reg_equiv_mem (i), 0);
1098 
1099       if (reg_equiv_address (i))
1100 	addr = reg_equiv_address (i);
1101 
1102       if (addr)
1103 	{
1104 	  if (reg_renumber[i] < 0)
1105 	    {
1106 	      rtx reg = regno_reg_rtx[i];
1107 
1108 	      REG_USERVAR_P (reg) = 0;
1109 	      PUT_CODE (reg, MEM);
1110 	      XEXP (reg, 0) = addr;
1111 	      if (reg_equiv_memory_loc (i))
1112 		MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc (i));
1113 	      else
1114 		MEM_ATTRS (reg) = 0;
1115 	      MEM_NOTRAP_P (reg) = 1;
1116 	    }
1117 	  else if (reg_equiv_mem (i))
1118 	    XEXP (reg_equiv_mem (i), 0) = addr;
1119 	}
1120 
1121       /* We don't want complex addressing modes in debug insns
1122 	 if simpler ones will do, so delegitimize equivalences
1123 	 in debug insns.  */
1124       if (MAY_HAVE_DEBUG_INSNS && reg_renumber[i] < 0)
1125 	{
1126 	  rtx reg = regno_reg_rtx[i];
1127 	  rtx equiv = 0;
1128 	  df_ref use, next;
1129 
1130 	  if (reg_equiv_constant (i))
1131 	    equiv = reg_equiv_constant (i);
1132 	  else if (reg_equiv_invariant (i))
1133 	    equiv = reg_equiv_invariant (i);
1134 	  else if (reg && MEM_P (reg))
1135 	    equiv = targetm.delegitimize_address (reg);
1136 	  else if (reg && REG_P (reg) && (int)REGNO (reg) != i)
1137 	    equiv = reg;
1138 
1139 	  if (equiv == reg)
1140 	    continue;
1141 
1142 	  for (use = DF_REG_USE_CHAIN (i); use; use = next)
1143 	    {
1144 	      insn = DF_REF_INSN (use);
1145 
1146 	      /* Make sure the next ref is for a different instruction,
1147 		 so that we're not affected by the rescan.  */
1148 	      next = DF_REF_NEXT_REG (use);
1149 	      while (next && DF_REF_INSN (next) == insn)
1150 		next = DF_REF_NEXT_REG (next);
1151 
1152 	      if (DEBUG_INSN_P (insn))
1153 		{
1154 		  if (!equiv)
1155 		    {
1156 		      INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
1157 		      df_insn_rescan_debug_internal (insn);
1158 		    }
1159 		  else
1160 		    INSN_VAR_LOCATION_LOC (insn)
1161 		      = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn),
1162 					      reg, equiv);
1163 		}
1164 	    }
1165 	}
1166     }
1167 
1168   /* We must set reload_completed now since the cleanup_subreg_operands call
1169      below will re-recognize each insn and reload may have generated insns
1170      which are only valid during and after reload.  */
1171   reload_completed = 1;
1172 
1173   /* Make a pass over all the insns and delete all USEs which we inserted
1174      only to tag a REG_EQUAL note on them.  Remove all REG_DEAD and REG_UNUSED
1175      notes.  Delete all CLOBBER insns, except those that refer to the return
1176      value and the special mem:BLK CLOBBERs added to prevent the scheduler
1177      from misarranging variable-array code, and simplify (subreg (reg))
1178      operands.  Strip and regenerate REG_INC notes that may have been moved
1179      around.  */
1180 
1181   for (insn = first; insn; insn = NEXT_INSN (insn))
1182     if (INSN_P (insn))
1183       {
1184 	rtx *pnote;
1185 
1186 	if (CALL_P (insn))
1187 	  replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1188 			      VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1189 
1190 	if ((GET_CODE (PATTERN (insn)) == USE
1191 	     /* We mark with QImode USEs introduced by reload itself.  */
1192 	     && (GET_MODE (insn) == QImode
1193 		 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1194 	    || (GET_CODE (PATTERN (insn)) == CLOBBER
1195 		&& (!MEM_P (XEXP (PATTERN (insn), 0))
1196 		    || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1197 		    || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1198 			&& XEXP (XEXP (PATTERN (insn), 0), 0)
1199 				!= stack_pointer_rtx))
1200 		&& (!REG_P (XEXP (PATTERN (insn), 0))
1201 		    || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1202 	  {
1203 	    delete_insn (insn);
1204 	    continue;
1205 	  }
1206 
1207 	/* Some CLOBBERs may survive until here and still reference unassigned
1208 	   pseudos with const equivalent, which may in turn cause ICE in later
1209 	   passes if the reference remains in place.  */
1210 	if (GET_CODE (PATTERN (insn)) == CLOBBER)
1211 	  replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1212 			      VOIDmode, PATTERN (insn));
1213 
1214 	/* Discard obvious no-ops, even without -O.  This optimization
1215 	   is fast and doesn't interfere with debugging.  */
1216 	if (NONJUMP_INSN_P (insn)
1217 	    && GET_CODE (PATTERN (insn)) == SET
1218 	    && REG_P (SET_SRC (PATTERN (insn)))
1219 	    && REG_P (SET_DEST (PATTERN (insn)))
1220 	    && (REGNO (SET_SRC (PATTERN (insn)))
1221 		== REGNO (SET_DEST (PATTERN (insn)))))
1222 	  {
1223 	    delete_insn (insn);
1224 	    continue;
1225 	  }
1226 
1227 	pnote = &REG_NOTES (insn);
1228 	while (*pnote != 0)
1229 	  {
1230 	    if (REG_NOTE_KIND (*pnote) == REG_DEAD
1231 		|| REG_NOTE_KIND (*pnote) == REG_UNUSED
1232 		|| REG_NOTE_KIND (*pnote) == REG_INC)
1233 	      *pnote = XEXP (*pnote, 1);
1234 	    else
1235 	      pnote = &XEXP (*pnote, 1);
1236 	  }
1237 
1238 #ifdef AUTO_INC_DEC
1239 	add_auto_inc_notes (insn, PATTERN (insn));
1240 #endif
1241 
1242 	/* Simplify (subreg (reg)) if it appears as an operand.  */
1243 	cleanup_subreg_operands (insn);
1244 
1245 	/* Clean up invalid ASMs so that they don't confuse later passes.
1246 	   See PR 21299.  */
1247 	if (asm_noperands (PATTERN (insn)) >= 0)
1248 	  {
1249 	    extract_insn (insn);
1250 	    if (!constrain_operands (1))
1251 	      {
1252 		error_for_asm (insn,
1253 			       "%<asm%> operand has impossible constraints");
1254 		delete_insn (insn);
1255 		continue;
1256 	      }
1257 	  }
1258       }
1259 
1260   /* If we are doing generic stack checking, give a warning if this
1261      function's frame size is larger than we expect.  */
1262   if (flag_stack_check == GENERIC_STACK_CHECK)
1263     {
1264       HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1265       static int verbose_warned = 0;
1266 
1267       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1268 	if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1269 	  size += UNITS_PER_WORD;
1270 
1271       if (size > STACK_CHECK_MAX_FRAME_SIZE)
1272 	{
1273 	  warning (0, "frame size too large for reliable stack checking");
1274 	  if (! verbose_warned)
1275 	    {
1276 	      warning (0, "try reducing the number of local variables");
1277 	      verbose_warned = 1;
1278 	    }
1279 	}
1280     }
1281 
1282   free (temp_pseudo_reg_arr);
1283 
1284   /* Indicate that we no longer have known memory locations or constants.  */
1285   free_reg_equiv ();
1286 
1287   free (reg_max_ref_width);
1288   free (reg_old_renumber);
1289   free (pseudo_previous_regs);
1290   free (pseudo_forbidden_regs);
1291 
1292   CLEAR_HARD_REG_SET (used_spill_regs);
1293   for (i = 0; i < n_spills; i++)
1294     SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1295 
1296   /* Free all the insn_chain structures at once.  */
1297   obstack_free (&reload_obstack, reload_startobj);
1298   unused_insn_chains = 0;
1299 
1300   inserted = fixup_abnormal_edges ();
1301 
1302   /* We've possibly turned single trapping insn into multiple ones.  */
1303   if (cfun->can_throw_non_call_exceptions)
1304     {
1305       sbitmap blocks;
1306       blocks = sbitmap_alloc (last_basic_block);
1307       sbitmap_ones (blocks);
1308       find_many_sub_basic_blocks (blocks);
1309       sbitmap_free (blocks);
1310     }
1311 
1312   if (inserted)
1313     commit_edge_insertions ();
1314 
1315   /* Replacing pseudos with their memory equivalents might have
1316      created shared rtx.  Subsequent passes would get confused
1317      by this, so unshare everything here.  */
1318   unshare_all_rtl_again (first);
1319 
1320 #ifdef STACK_BOUNDARY
1321   /* init_emit has set the alignment of the hard frame pointer
1322      to STACK_BOUNDARY.  It is very likely no longer valid if
1323      the hard frame pointer was used for register allocation.  */
1324   if (!frame_pointer_needed)
1325     REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1326 #endif
1327 
1328   VEC_free (rtx_p, heap, substitute_stack);
1329 
1330   gcc_assert (bitmap_empty_p (&spilled_pseudos));
1331 
1332   reload_completed = !failure;
1333 
1334   return need_dce;
1335 }
1336 
1337 /* Yet another special case.  Unfortunately, reg-stack forces people to
1338    write incorrect clobbers in asm statements.  These clobbers must not
1339    cause the register to appear in bad_spill_regs, otherwise we'll call
1340    fatal_insn later.  We clear the corresponding regnos in the live
1341    register sets to avoid this.
1342    The whole thing is rather sick, I'm afraid.  */
1343 
1344 static void
maybe_fix_stack_asms(void)1345 maybe_fix_stack_asms (void)
1346 {
1347 #ifdef STACK_REGS
1348   const char *constraints[MAX_RECOG_OPERANDS];
1349   enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1350   struct insn_chain *chain;
1351 
1352   for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1353     {
1354       int i, noperands;
1355       HARD_REG_SET clobbered, allowed;
1356       rtx pat;
1357 
1358       if (! INSN_P (chain->insn)
1359 	  || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1360 	continue;
1361       pat = PATTERN (chain->insn);
1362       if (GET_CODE (pat) != PARALLEL)
1363 	continue;
1364 
1365       CLEAR_HARD_REG_SET (clobbered);
1366       CLEAR_HARD_REG_SET (allowed);
1367 
1368       /* First, make a mask of all stack regs that are clobbered.  */
1369       for (i = 0; i < XVECLEN (pat, 0); i++)
1370 	{
1371 	  rtx t = XVECEXP (pat, 0, i);
1372 	  if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1373 	    SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1374 	}
1375 
1376       /* Get the operand values and constraints out of the insn.  */
1377       decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1378 			   constraints, operand_mode, NULL);
1379 
1380       /* For every operand, see what registers are allowed.  */
1381       for (i = 0; i < noperands; i++)
1382 	{
1383 	  const char *p = constraints[i];
1384 	  /* For every alternative, we compute the class of registers allowed
1385 	     for reloading in CLS, and merge its contents into the reg set
1386 	     ALLOWED.  */
1387 	  int cls = (int) NO_REGS;
1388 
1389 	  for (;;)
1390 	    {
1391 	      char c = *p;
1392 
1393 	      if (c == '\0' || c == ',' || c == '#')
1394 		{
1395 		  /* End of one alternative - mark the regs in the current
1396 		     class, and reset the class.  */
1397 		  IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1398 		  cls = NO_REGS;
1399 		  p++;
1400 		  if (c == '#')
1401 		    do {
1402 		      c = *p++;
1403 		    } while (c != '\0' && c != ',');
1404 		  if (c == '\0')
1405 		    break;
1406 		  continue;
1407 		}
1408 
1409 	      switch (c)
1410 		{
1411 		case '=': case '+': case '*': case '%': case '?': case '!':
1412 		case '0': case '1': case '2': case '3': case '4': case '<':
1413 		case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1414 		case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1415 		case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1416 		case TARGET_MEM_CONSTRAINT:
1417 		  break;
1418 
1419 		case 'p':
1420 		  cls = (int) reg_class_subunion[cls]
1421 		      [(int) base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
1422 					     ADDRESS, SCRATCH)];
1423 		  break;
1424 
1425 		case 'g':
1426 		case 'r':
1427 		  cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1428 		  break;
1429 
1430 		default:
1431 		  if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1432 		    cls = (int) reg_class_subunion[cls]
1433 		      [(int) base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
1434 					     ADDRESS, SCRATCH)];
1435 		  else
1436 		    cls = (int) reg_class_subunion[cls]
1437 		      [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1438 		}
1439 	      p += CONSTRAINT_LEN (c, p);
1440 	    }
1441 	}
1442       /* Those of the registers which are clobbered, but allowed by the
1443 	 constraints, must be usable as reload registers.  So clear them
1444 	 out of the life information.  */
1445       AND_HARD_REG_SET (allowed, clobbered);
1446       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1447 	if (TEST_HARD_REG_BIT (allowed, i))
1448 	  {
1449 	    CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1450 	    CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1451 	  }
1452     }
1453 
1454 #endif
1455 }
1456 
1457 /* Copy the global variables n_reloads and rld into the corresponding elts
1458    of CHAIN.  */
1459 static void
copy_reloads(struct insn_chain * chain)1460 copy_reloads (struct insn_chain *chain)
1461 {
1462   chain->n_reloads = n_reloads;
1463   chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1464   memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1465   reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1466 }
1467 
1468 /* Walk the chain of insns, and determine for each whether it needs reloads
1469    and/or eliminations.  Build the corresponding insns_need_reload list, and
1470    set something_needs_elimination as appropriate.  */
1471 static void
calculate_needs_all_insns(int global)1472 calculate_needs_all_insns (int global)
1473 {
1474   struct insn_chain **pprev_reload = &insns_need_reload;
1475   struct insn_chain *chain, *next = 0;
1476 
1477   something_needs_elimination = 0;
1478 
1479   reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1480   for (chain = reload_insn_chain; chain != 0; chain = next)
1481     {
1482       rtx insn = chain->insn;
1483 
1484       next = chain->next;
1485 
1486       /* Clear out the shortcuts.  */
1487       chain->n_reloads = 0;
1488       chain->need_elim = 0;
1489       chain->need_reload = 0;
1490       chain->need_operand_change = 0;
1491 
1492       /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1493 	 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1494 	 what effects this has on the known offsets at labels.  */
1495 
1496       if (LABEL_P (insn) || JUMP_P (insn)
1497 	  || (INSN_P (insn) && REG_NOTES (insn) != 0))
1498 	set_label_offsets (insn, insn, 0);
1499 
1500       if (INSN_P (insn))
1501 	{
1502 	  rtx old_body = PATTERN (insn);
1503 	  int old_code = INSN_CODE (insn);
1504 	  rtx old_notes = REG_NOTES (insn);
1505 	  int did_elimination = 0;
1506 	  int operands_changed = 0;
1507 	  rtx set = single_set (insn);
1508 
1509 	  /* Skip insns that only set an equivalence.  */
1510 	  if (set && REG_P (SET_DEST (set))
1511 	      && reg_renumber[REGNO (SET_DEST (set))] < 0
1512 	      && (reg_equiv_constant (REGNO (SET_DEST (set)))
1513 		  || (reg_equiv_invariant (REGNO (SET_DEST (set)))))
1514 		      && reg_equiv_init (REGNO (SET_DEST (set))))
1515 	    continue;
1516 
1517 	  /* If needed, eliminate any eliminable registers.  */
1518 	  if (num_eliminable || num_eliminable_invariants)
1519 	    did_elimination = eliminate_regs_in_insn (insn, 0);
1520 
1521 	  /* Analyze the instruction.  */
1522 	  operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1523 					   global, spill_reg_order);
1524 
1525 	  /* If a no-op set needs more than one reload, this is likely
1526 	     to be something that needs input address reloads.  We
1527 	     can't get rid of this cleanly later, and it is of no use
1528 	     anyway, so discard it now.
1529 	     We only do this when expensive_optimizations is enabled,
1530 	     since this complements reload inheritance / output
1531 	     reload deletion, and it can make debugging harder.  */
1532 	  if (flag_expensive_optimizations && n_reloads > 1)
1533 	    {
1534 	      rtx set = single_set (insn);
1535 	      if (set
1536 		  &&
1537 		  ((SET_SRC (set) == SET_DEST (set)
1538 		    && REG_P (SET_SRC (set))
1539 		    && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1540 		   || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1541 		       && reg_renumber[REGNO (SET_SRC (set))] < 0
1542 		       && reg_renumber[REGNO (SET_DEST (set))] < 0
1543 		       && reg_equiv_memory_loc (REGNO (SET_SRC (set))) != NULL
1544 		       && reg_equiv_memory_loc (REGNO (SET_DEST (set))) != NULL
1545 		       && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set))),
1546 				       reg_equiv_memory_loc (REGNO (SET_DEST (set)))))))
1547 		{
1548 		  if (ira_conflicts_p)
1549 		    /* Inform IRA about the insn deletion.  */
1550 		    ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1551 						   REGNO (SET_SRC (set)));
1552 		  delete_insn (insn);
1553 		  /* Delete it from the reload chain.  */
1554 		  if (chain->prev)
1555 		    chain->prev->next = next;
1556 		  else
1557 		    reload_insn_chain = next;
1558 		  if (next)
1559 		    next->prev = chain->prev;
1560 		  chain->next = unused_insn_chains;
1561 		  unused_insn_chains = chain;
1562 		  continue;
1563 		}
1564 	    }
1565 	  if (num_eliminable)
1566 	    update_eliminable_offsets ();
1567 
1568 	  /* Remember for later shortcuts which insns had any reloads or
1569 	     register eliminations.  */
1570 	  chain->need_elim = did_elimination;
1571 	  chain->need_reload = n_reloads > 0;
1572 	  chain->need_operand_change = operands_changed;
1573 
1574 	  /* Discard any register replacements done.  */
1575 	  if (did_elimination)
1576 	    {
1577 	      obstack_free (&reload_obstack, reload_insn_firstobj);
1578 	      PATTERN (insn) = old_body;
1579 	      INSN_CODE (insn) = old_code;
1580 	      REG_NOTES (insn) = old_notes;
1581 	      something_needs_elimination = 1;
1582 	    }
1583 
1584 	  something_needs_operands_changed |= operands_changed;
1585 
1586 	  if (n_reloads != 0)
1587 	    {
1588 	      copy_reloads (chain);
1589 	      *pprev_reload = chain;
1590 	      pprev_reload = &chain->next_need_reload;
1591 	    }
1592 	}
1593     }
1594   *pprev_reload = 0;
1595 }
1596 
1597 /* This function is called from the register allocator to set up estimates
1598    for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1599    an invariant.  The structure is similar to calculate_needs_all_insns.  */
1600 
1601 void
calculate_elim_costs_all_insns(void)1602 calculate_elim_costs_all_insns (void)
1603 {
1604   int *reg_equiv_init_cost;
1605   basic_block bb;
1606   int i;
1607 
1608   reg_equiv_init_cost = XCNEWVEC (int, max_regno);
1609   init_elim_table ();
1610   init_eliminable_invariants (get_insns (), false);
1611 
1612   set_initial_elim_offsets ();
1613   set_initial_label_offsets ();
1614 
1615   FOR_EACH_BB (bb)
1616     {
1617       rtx insn;
1618       elim_bb = bb;
1619 
1620       FOR_BB_INSNS (bb, insn)
1621 	{
1622 	  /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1623 	     include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1624 	     what effects this has on the known offsets at labels.  */
1625 
1626 	  if (LABEL_P (insn) || JUMP_P (insn)
1627 	      || (INSN_P (insn) && REG_NOTES (insn) != 0))
1628 	    set_label_offsets (insn, insn, 0);
1629 
1630 	  if (INSN_P (insn))
1631 	    {
1632 	      rtx set = single_set (insn);
1633 
1634 	      /* Skip insns that only set an equivalence.  */
1635 	      if (set && REG_P (SET_DEST (set))
1636 		  && reg_renumber[REGNO (SET_DEST (set))] < 0
1637 		  && (reg_equiv_constant (REGNO (SET_DEST (set)))
1638 		      || reg_equiv_invariant (REGNO (SET_DEST (set)))))
1639 		{
1640 		  unsigned regno = REGNO (SET_DEST (set));
1641 		  rtx init = reg_equiv_init (regno);
1642 		  if (init)
1643 		    {
1644 		      rtx t = eliminate_regs_1 (SET_SRC (set), VOIDmode, insn,
1645 						false, true);
1646 		      int cost = set_src_cost (t, optimize_bb_for_speed_p (bb));
1647 		      int freq = REG_FREQ_FROM_BB (bb);
1648 
1649 		      reg_equiv_init_cost[regno] = cost * freq;
1650 		      continue;
1651 		    }
1652 		}
1653 	      /* If needed, eliminate any eliminable registers.  */
1654 	      if (num_eliminable || num_eliminable_invariants)
1655 		elimination_costs_in_insn (insn);
1656 
1657 	      if (num_eliminable)
1658 		update_eliminable_offsets ();
1659 	    }
1660 	}
1661     }
1662   for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1663     {
1664       if (reg_equiv_invariant (i))
1665 	{
1666 	  if (reg_equiv_init (i))
1667 	    {
1668 	      int cost = reg_equiv_init_cost[i];
1669 	      if (dump_file)
1670 		fprintf (dump_file,
1671 			 "Reg %d has equivalence, initial gains %d\n", i, cost);
1672 	      if (cost != 0)
1673 		ira_adjust_equiv_reg_cost (i, cost);
1674 	    }
1675 	  else
1676 	    {
1677 	      if (dump_file)
1678 		fprintf (dump_file,
1679 			 "Reg %d had equivalence, but can't be eliminated\n",
1680 			 i);
1681 	      ira_adjust_equiv_reg_cost (i, 0);
1682 	    }
1683 	}
1684     }
1685 
1686   free (reg_equiv_init_cost);
1687   free (offsets_known_at);
1688   free (offsets_at);
1689   offsets_at = NULL;
1690   offsets_known_at = NULL;
1691 }
1692 
1693 /* Comparison function for qsort to decide which of two reloads
1694    should be handled first.  *P1 and *P2 are the reload numbers.  */
1695 
1696 static int
reload_reg_class_lower(const void * r1p,const void * r2p)1697 reload_reg_class_lower (const void *r1p, const void *r2p)
1698 {
1699   int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1700   int t;
1701 
1702   /* Consider required reloads before optional ones.  */
1703   t = rld[r1].optional - rld[r2].optional;
1704   if (t != 0)
1705     return t;
1706 
1707   /* Count all solitary classes before non-solitary ones.  */
1708   t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1709        - (reg_class_size[(int) rld[r1].rclass] == 1));
1710   if (t != 0)
1711     return t;
1712 
1713   /* Aside from solitaires, consider all multi-reg groups first.  */
1714   t = rld[r2].nregs - rld[r1].nregs;
1715   if (t != 0)
1716     return t;
1717 
1718   /* Consider reloads in order of increasing reg-class number.  */
1719   t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1720   if (t != 0)
1721     return t;
1722 
1723   /* If reloads are equally urgent, sort by reload number,
1724      so that the results of qsort leave nothing to chance.  */
1725   return r1 - r2;
1726 }
1727 
1728 /* The cost of spilling each hard reg.  */
1729 static int spill_cost[FIRST_PSEUDO_REGISTER];
1730 
1731 /* When spilling multiple hard registers, we use SPILL_COST for the first
1732    spilled hard reg and SPILL_ADD_COST for subsequent regs.  SPILL_ADD_COST
1733    only the first hard reg for a multi-reg pseudo.  */
1734 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1735 
1736 /* Map of hard regno to pseudo regno currently occupying the hard
1737    reg.  */
1738 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1739 
1740 /* Update the spill cost arrays, considering that pseudo REG is live.  */
1741 
1742 static void
count_pseudo(int reg)1743 count_pseudo (int reg)
1744 {
1745   int freq = REG_FREQ (reg);
1746   int r = reg_renumber[reg];
1747   int nregs;
1748 
1749   if (REGNO_REG_SET_P (&pseudos_counted, reg)
1750       || REGNO_REG_SET_P (&spilled_pseudos, reg)
1751       /* Ignore spilled pseudo-registers which can be here only if IRA
1752 	 is used.  */
1753       || (ira_conflicts_p && r < 0))
1754     return;
1755 
1756   SET_REGNO_REG_SET (&pseudos_counted, reg);
1757 
1758   gcc_assert (r >= 0);
1759 
1760   spill_add_cost[r] += freq;
1761   nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1762   while (nregs-- > 0)
1763     {
1764       hard_regno_to_pseudo_regno[r + nregs] = reg;
1765       spill_cost[r + nregs] += freq;
1766     }
1767 }
1768 
1769 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1770    contents of BAD_SPILL_REGS for the insn described by CHAIN.  */
1771 
1772 static void
order_regs_for_reload(struct insn_chain * chain)1773 order_regs_for_reload (struct insn_chain *chain)
1774 {
1775   unsigned i;
1776   HARD_REG_SET used_by_pseudos;
1777   HARD_REG_SET used_by_pseudos2;
1778   reg_set_iterator rsi;
1779 
1780   COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1781 
1782   memset (spill_cost, 0, sizeof spill_cost);
1783   memset (spill_add_cost, 0, sizeof spill_add_cost);
1784   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1785     hard_regno_to_pseudo_regno[i] = -1;
1786 
1787   /* Count number of uses of each hard reg by pseudo regs allocated to it
1788      and then order them by decreasing use.  First exclude hard registers
1789      that are live in or across this insn.  */
1790 
1791   REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1792   REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1793   IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1794   IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1795 
1796   /* Now find out which pseudos are allocated to it, and update
1797      hard_reg_n_uses.  */
1798   CLEAR_REG_SET (&pseudos_counted);
1799 
1800   EXECUTE_IF_SET_IN_REG_SET
1801     (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1802     {
1803       count_pseudo (i);
1804     }
1805   EXECUTE_IF_SET_IN_REG_SET
1806     (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1807     {
1808       count_pseudo (i);
1809     }
1810   CLEAR_REG_SET (&pseudos_counted);
1811 }
1812 
1813 /* Vector of reload-numbers showing the order in which the reloads should
1814    be processed.  */
1815 static short reload_order[MAX_RELOADS];
1816 
1817 /* This is used to keep track of the spill regs used in one insn.  */
1818 static HARD_REG_SET used_spill_regs_local;
1819 
1820 /* We decided to spill hard register SPILLED, which has a size of
1821    SPILLED_NREGS.  Determine how pseudo REG, which is live during the insn,
1822    is affected.  We will add it to SPILLED_PSEUDOS if necessary, and we will
1823    update SPILL_COST/SPILL_ADD_COST.  */
1824 
1825 static void
count_spilled_pseudo(int spilled,int spilled_nregs,int reg)1826 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1827 {
1828   int freq = REG_FREQ (reg);
1829   int r = reg_renumber[reg];
1830   int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1831 
1832   /* Ignore spilled pseudo-registers which can be here only if IRA is
1833      used.  */
1834   if ((ira_conflicts_p && r < 0)
1835       || REGNO_REG_SET_P (&spilled_pseudos, reg)
1836       || spilled + spilled_nregs <= r || r + nregs <= spilled)
1837     return;
1838 
1839   SET_REGNO_REG_SET (&spilled_pseudos, reg);
1840 
1841   spill_add_cost[r] -= freq;
1842   while (nregs-- > 0)
1843     {
1844       hard_regno_to_pseudo_regno[r + nregs] = -1;
1845       spill_cost[r + nregs] -= freq;
1846     }
1847 }
1848 
1849 /* Find reload register to use for reload number ORDER.  */
1850 
1851 static int
find_reg(struct insn_chain * chain,int order)1852 find_reg (struct insn_chain *chain, int order)
1853 {
1854   int rnum = reload_order[order];
1855   struct reload *rl = rld + rnum;
1856   int best_cost = INT_MAX;
1857   int best_reg = -1;
1858   unsigned int i, j, n;
1859   int k;
1860   HARD_REG_SET not_usable;
1861   HARD_REG_SET used_by_other_reload;
1862   reg_set_iterator rsi;
1863   static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1864   static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1865 
1866   COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1867   IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1868   IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1869 
1870   CLEAR_HARD_REG_SET (used_by_other_reload);
1871   for (k = 0; k < order; k++)
1872     {
1873       int other = reload_order[k];
1874 
1875       if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1876 	for (j = 0; j < rld[other].nregs; j++)
1877 	  SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1878     }
1879 
1880   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1881     {
1882 #ifdef REG_ALLOC_ORDER
1883       unsigned int regno = reg_alloc_order[i];
1884 #else
1885       unsigned int regno = i;
1886 #endif
1887 
1888       if (! TEST_HARD_REG_BIT (not_usable, regno)
1889 	  && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1890 	  && HARD_REGNO_MODE_OK (regno, rl->mode))
1891 	{
1892 	  int this_cost = spill_cost[regno];
1893 	  int ok = 1;
1894 	  unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1895 
1896 	  for (j = 1; j < this_nregs; j++)
1897 	    {
1898 	      this_cost += spill_add_cost[regno + j];
1899 	      if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1900 		  || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1901 		ok = 0;
1902 	    }
1903 	  if (! ok)
1904 	    continue;
1905 
1906 	  if (ira_conflicts_p)
1907 	    {
1908 	      /* Ask IRA to find a better pseudo-register for
1909 		 spilling.  */
1910 	      for (n = j = 0; j < this_nregs; j++)
1911 		{
1912 		  int r = hard_regno_to_pseudo_regno[regno + j];
1913 
1914 		  if (r < 0)
1915 		    continue;
1916 		  if (n == 0 || regno_pseudo_regs[n - 1] != r)
1917 		    regno_pseudo_regs[n++] = r;
1918 		}
1919 	      regno_pseudo_regs[n++] = -1;
1920 	      if (best_reg < 0
1921 		  || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1922 						      best_regno_pseudo_regs,
1923 						      rl->in, rl->out,
1924 						      chain->insn))
1925 		{
1926 		  best_reg = regno;
1927 		  for (j = 0;; j++)
1928 		    {
1929 		      best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1930 		      if (regno_pseudo_regs[j] < 0)
1931 			break;
1932 		    }
1933 		}
1934 	      continue;
1935 	    }
1936 
1937 	  if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1938 	    this_cost--;
1939 	  if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1940 	    this_cost--;
1941 	  if (this_cost < best_cost
1942 	      /* Among registers with equal cost, prefer caller-saved ones, or
1943 		 use REG_ALLOC_ORDER if it is defined.  */
1944 	      || (this_cost == best_cost
1945 #ifdef REG_ALLOC_ORDER
1946 		  && (inv_reg_alloc_order[regno]
1947 		      < inv_reg_alloc_order[best_reg])
1948 #else
1949 		  && call_used_regs[regno]
1950 		  && ! call_used_regs[best_reg]
1951 #endif
1952 		  ))
1953 	    {
1954 	      best_reg = regno;
1955 	      best_cost = this_cost;
1956 	    }
1957 	}
1958     }
1959   if (best_reg == -1)
1960     return 0;
1961 
1962   if (dump_file)
1963     fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1964 
1965   rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1966   rl->regno = best_reg;
1967 
1968   EXECUTE_IF_SET_IN_REG_SET
1969     (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1970     {
1971       count_spilled_pseudo (best_reg, rl->nregs, j);
1972     }
1973 
1974   EXECUTE_IF_SET_IN_REG_SET
1975     (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1976     {
1977       count_spilled_pseudo (best_reg, rl->nregs, j);
1978     }
1979 
1980   for (i = 0; i < rl->nregs; i++)
1981     {
1982       gcc_assert (spill_cost[best_reg + i] == 0);
1983       gcc_assert (spill_add_cost[best_reg + i] == 0);
1984       gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
1985       SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1986     }
1987   return 1;
1988 }
1989 
1990 /* Find more reload regs to satisfy the remaining need of an insn, which
1991    is given by CHAIN.
1992    Do it by ascending class number, since otherwise a reg
1993    might be spilled for a big class and might fail to count
1994    for a smaller class even though it belongs to that class.  */
1995 
1996 static void
find_reload_regs(struct insn_chain * chain)1997 find_reload_regs (struct insn_chain *chain)
1998 {
1999   int i;
2000 
2001   /* In order to be certain of getting the registers we need,
2002      we must sort the reloads into order of increasing register class.
2003      Then our grabbing of reload registers will parallel the process
2004      that provided the reload registers.  */
2005   for (i = 0; i < chain->n_reloads; i++)
2006     {
2007       /* Show whether this reload already has a hard reg.  */
2008       if (chain->rld[i].reg_rtx)
2009 	{
2010 	  int regno = REGNO (chain->rld[i].reg_rtx);
2011 	  chain->rld[i].regno = regno;
2012 	  chain->rld[i].nregs
2013 	    = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
2014 	}
2015       else
2016 	chain->rld[i].regno = -1;
2017       reload_order[i] = i;
2018     }
2019 
2020   n_reloads = chain->n_reloads;
2021   memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
2022 
2023   CLEAR_HARD_REG_SET (used_spill_regs_local);
2024 
2025   if (dump_file)
2026     fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
2027 
2028   qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
2029 
2030   /* Compute the order of preference for hard registers to spill.  */
2031 
2032   order_regs_for_reload (chain);
2033 
2034   for (i = 0; i < n_reloads; i++)
2035     {
2036       int r = reload_order[i];
2037 
2038       /* Ignore reloads that got marked inoperative.  */
2039       if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2040 	  && ! rld[r].optional
2041 	  && rld[r].regno == -1)
2042 	if (! find_reg (chain, i))
2043 	  {
2044 	    if (dump_file)
2045 	      fprintf (dump_file, "reload failure for reload %d\n", r);
2046 	    spill_failure (chain->insn, rld[r].rclass);
2047 	    failure = 1;
2048 	    return;
2049 	  }
2050     }
2051 
2052   COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2053   IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2054 
2055   memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2056 }
2057 
2058 static void
select_reload_regs(void)2059 select_reload_regs (void)
2060 {
2061   struct insn_chain *chain;
2062 
2063   /* Try to satisfy the needs for each insn.  */
2064   for (chain = insns_need_reload; chain != 0;
2065        chain = chain->next_need_reload)
2066     find_reload_regs (chain);
2067 }
2068 
2069 /* Delete all insns that were inserted by emit_caller_save_insns during
2070    this iteration.  */
2071 static void
delete_caller_save_insns(void)2072 delete_caller_save_insns (void)
2073 {
2074   struct insn_chain *c = reload_insn_chain;
2075 
2076   while (c != 0)
2077     {
2078       while (c != 0 && c->is_caller_save_insn)
2079 	{
2080 	  struct insn_chain *next = c->next;
2081 	  rtx insn = c->insn;
2082 
2083 	  if (c == reload_insn_chain)
2084 	    reload_insn_chain = next;
2085 	  delete_insn (insn);
2086 
2087 	  if (next)
2088 	    next->prev = c->prev;
2089 	  if (c->prev)
2090 	    c->prev->next = next;
2091 	  c->next = unused_insn_chains;
2092 	  unused_insn_chains = c;
2093 	  c = next;
2094 	}
2095       if (c != 0)
2096 	c = c->next;
2097     }
2098 }
2099 
2100 /* Handle the failure to find a register to spill.
2101    INSN should be one of the insns which needed this particular spill reg.  */
2102 
2103 static void
spill_failure(rtx insn,enum reg_class rclass)2104 spill_failure (rtx insn, enum reg_class rclass)
2105 {
2106   if (asm_noperands (PATTERN (insn)) >= 0)
2107     error_for_asm (insn, "can%'t find a register in class %qs while "
2108 		   "reloading %<asm%>",
2109 		   reg_class_names[rclass]);
2110   else
2111     {
2112       error ("unable to find a register to spill in class %qs",
2113 	     reg_class_names[rclass]);
2114 
2115       if (dump_file)
2116 	{
2117 	  fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2118 	  debug_reload_to_stream (dump_file);
2119 	}
2120       fatal_insn ("this is the insn:", insn);
2121     }
2122 }
2123 
2124 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2125    data that is dead in INSN.  */
2126 
2127 static void
delete_dead_insn(rtx insn)2128 delete_dead_insn (rtx insn)
2129 {
2130   rtx prev = prev_active_insn (insn);
2131   rtx prev_dest;
2132 
2133   /* If the previous insn sets a register that dies in our insn make
2134      a note that we want to run DCE immediately after reload.
2135 
2136      We used to delete the previous insn & recurse, but that's wrong for
2137      block local equivalences.  Instead of trying to figure out the exact
2138      circumstances where we can delete the potentially dead insns, just
2139      let DCE do the job.  */
2140   if (prev && GET_CODE (PATTERN (prev)) == SET
2141       && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2142       && reg_mentioned_p (prev_dest, PATTERN (insn))
2143       && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2144       && ! side_effects_p (SET_SRC (PATTERN (prev))))
2145     need_dce = 1;
2146 
2147   SET_INSN_DELETED (insn);
2148 }
2149 
2150 /* Modify the home of pseudo-reg I.
2151    The new home is present in reg_renumber[I].
2152 
2153    FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2154    or it may be -1, meaning there is none or it is not relevant.
2155    This is used so that all pseudos spilled from a given hard reg
2156    can share one stack slot.  */
2157 
2158 static void
alter_reg(int i,int from_reg,bool dont_share_p)2159 alter_reg (int i, int from_reg, bool dont_share_p)
2160 {
2161   /* When outputting an inline function, this can happen
2162      for a reg that isn't actually used.  */
2163   if (regno_reg_rtx[i] == 0)
2164     return;
2165 
2166   /* If the reg got changed to a MEM at rtl-generation time,
2167      ignore it.  */
2168   if (!REG_P (regno_reg_rtx[i]))
2169     return;
2170 
2171   /* Modify the reg-rtx to contain the new hard reg
2172      number or else to contain its pseudo reg number.  */
2173   SET_REGNO (regno_reg_rtx[i],
2174 	     reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2175 
2176   /* If we have a pseudo that is needed but has no hard reg or equivalent,
2177      allocate a stack slot for it.  */
2178 
2179   if (reg_renumber[i] < 0
2180       && REG_N_REFS (i) > 0
2181       && reg_equiv_constant (i) == 0
2182       && (reg_equiv_invariant (i) == 0
2183 	  || reg_equiv_init (i) == 0)
2184       && reg_equiv_memory_loc (i) == 0)
2185     {
2186       rtx x = NULL_RTX;
2187       enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2188       unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2189       unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2190       unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2191       unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2192       int adjust = 0;
2193 
2194       something_was_spilled = true;
2195 
2196       if (ira_conflicts_p)
2197 	{
2198 	  /* Mark the spill for IRA.  */
2199 	  SET_REGNO_REG_SET (&spilled_pseudos, i);
2200 	  if (!dont_share_p)
2201 	    x = ira_reuse_stack_slot (i, inherent_size, total_size);
2202 	}
2203 
2204       if (x)
2205 	;
2206 
2207       /* Each pseudo reg has an inherent size which comes from its own mode,
2208 	 and a total size which provides room for paradoxical subregs
2209 	 which refer to the pseudo reg in wider modes.
2210 
2211 	 We can use a slot already allocated if it provides both
2212 	 enough inherent space and enough total space.
2213 	 Otherwise, we allocate a new slot, making sure that it has no less
2214 	 inherent space, and no less total space, then the previous slot.  */
2215       else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2216 	{
2217 	  rtx stack_slot;
2218 
2219 	  /* No known place to spill from => no slot to reuse.  */
2220 	  x = assign_stack_local (mode, total_size,
2221 				  min_align > inherent_align
2222 				  || total_size > inherent_size ? -1 : 0);
2223 
2224 	  stack_slot = x;
2225 
2226 	  /* Cancel the big-endian correction done in assign_stack_local.
2227 	     Get the address of the beginning of the slot.  This is so we
2228 	     can do a big-endian correction unconditionally below.  */
2229 	  if (BYTES_BIG_ENDIAN)
2230 	    {
2231 	      adjust = inherent_size - total_size;
2232 	      if (adjust)
2233 		stack_slot
2234 		  = adjust_address_nv (x, mode_for_size (total_size
2235 						         * BITS_PER_UNIT,
2236 						         MODE_INT, 1),
2237 				       adjust);
2238 	    }
2239 
2240 	  if (! dont_share_p && ira_conflicts_p)
2241 	    /* Inform IRA about allocation a new stack slot.  */
2242 	    ira_mark_new_stack_slot (stack_slot, i, total_size);
2243 	}
2244 
2245       /* Reuse a stack slot if possible.  */
2246       else if (spill_stack_slot[from_reg] != 0
2247 	       && spill_stack_slot_width[from_reg] >= total_size
2248 	       && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2249 		   >= inherent_size)
2250 	       && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2251 	x = spill_stack_slot[from_reg];
2252 
2253       /* Allocate a bigger slot.  */
2254       else
2255 	{
2256 	  /* Compute maximum size needed, both for inherent size
2257 	     and for total size.  */
2258 	  rtx stack_slot;
2259 
2260 	  if (spill_stack_slot[from_reg])
2261 	    {
2262 	      if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2263 		  > inherent_size)
2264 		mode = GET_MODE (spill_stack_slot[from_reg]);
2265 	      if (spill_stack_slot_width[from_reg] > total_size)
2266 		total_size = spill_stack_slot_width[from_reg];
2267 	      if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2268 		min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2269 	    }
2270 
2271 	  /* Make a slot with that size.  */
2272 	  x = assign_stack_local (mode, total_size,
2273 				  min_align > inherent_align
2274 				  || total_size > inherent_size ? -1 : 0);
2275 	  stack_slot = x;
2276 
2277 	  /* Cancel the  big-endian correction done in assign_stack_local.
2278 	     Get the address of the beginning of the slot.  This is so we
2279 	     can do a big-endian correction unconditionally below.  */
2280 	  if (BYTES_BIG_ENDIAN)
2281 	    {
2282 	      adjust = GET_MODE_SIZE (mode) - total_size;
2283 	      if (adjust)
2284 		stack_slot
2285 		  = adjust_address_nv (x, mode_for_size (total_size
2286 							 * BITS_PER_UNIT,
2287 							 MODE_INT, 1),
2288 				       adjust);
2289 	    }
2290 
2291 	  spill_stack_slot[from_reg] = stack_slot;
2292 	  spill_stack_slot_width[from_reg] = total_size;
2293 	}
2294 
2295       /* On a big endian machine, the "address" of the slot
2296 	 is the address of the low part that fits its inherent mode.  */
2297       if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2298 	adjust += (total_size - inherent_size);
2299 
2300       /* If we have any adjustment to make, or if the stack slot is the
2301 	 wrong mode, make a new stack slot.  */
2302       x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2303 
2304       /* Set all of the memory attributes as appropriate for a spill.  */
2305       set_mem_attrs_for_spill (x);
2306 
2307       /* Save the stack slot for later.  */
2308       reg_equiv_memory_loc (i) = x;
2309     }
2310 }
2311 
2312 /* Mark the slots in regs_ever_live for the hard regs used by
2313    pseudo-reg number REGNO, accessed in MODE.  */
2314 
2315 static void
mark_home_live_1(int regno,enum machine_mode mode)2316 mark_home_live_1 (int regno, enum machine_mode mode)
2317 {
2318   int i, lim;
2319 
2320   i = reg_renumber[regno];
2321   if (i < 0)
2322     return;
2323   lim = end_hard_regno (mode, i);
2324   while (i < lim)
2325     df_set_regs_ever_live(i++, true);
2326 }
2327 
2328 /* Mark the slots in regs_ever_live for the hard regs
2329    used by pseudo-reg number REGNO.  */
2330 
2331 void
mark_home_live(int regno)2332 mark_home_live (int regno)
2333 {
2334   if (reg_renumber[regno] >= 0)
2335     mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2336 }
2337 
2338 /* This function handles the tracking of elimination offsets around branches.
2339 
2340    X is a piece of RTL being scanned.
2341 
2342    INSN is the insn that it came from, if any.
2343 
2344    INITIAL_P is nonzero if we are to set the offset to be the initial
2345    offset and zero if we are setting the offset of the label to be the
2346    current offset.  */
2347 
2348 static void
set_label_offsets(rtx x,rtx insn,int initial_p)2349 set_label_offsets (rtx x, rtx insn, int initial_p)
2350 {
2351   enum rtx_code code = GET_CODE (x);
2352   rtx tem;
2353   unsigned int i;
2354   struct elim_table *p;
2355 
2356   switch (code)
2357     {
2358     case LABEL_REF:
2359       if (LABEL_REF_NONLOCAL_P (x))
2360 	return;
2361 
2362       x = XEXP (x, 0);
2363 
2364       /* ... fall through ...  */
2365 
2366     case CODE_LABEL:
2367       /* If we know nothing about this label, set the desired offsets.  Note
2368 	 that this sets the offset at a label to be the offset before a label
2369 	 if we don't know anything about the label.  This is not correct for
2370 	 the label after a BARRIER, but is the best guess we can make.  If
2371 	 we guessed wrong, we will suppress an elimination that might have
2372 	 been possible had we been able to guess correctly.  */
2373 
2374       if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2375 	{
2376 	  for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2377 	    offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2378 	      = (initial_p ? reg_eliminate[i].initial_offset
2379 		 : reg_eliminate[i].offset);
2380 	  offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2381 	}
2382 
2383       /* Otherwise, if this is the definition of a label and it is
2384 	 preceded by a BARRIER, set our offsets to the known offset of
2385 	 that label.  */
2386 
2387       else if (x == insn
2388 	       && (tem = prev_nonnote_insn (insn)) != 0
2389 	       && BARRIER_P (tem))
2390 	set_offsets_for_label (insn);
2391       else
2392 	/* If neither of the above cases is true, compare each offset
2393 	   with those previously recorded and suppress any eliminations
2394 	   where the offsets disagree.  */
2395 
2396 	for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2397 	  if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2398 	      != (initial_p ? reg_eliminate[i].initial_offset
2399 		  : reg_eliminate[i].offset))
2400 	    reg_eliminate[i].can_eliminate = 0;
2401 
2402       return;
2403 
2404     case JUMP_INSN:
2405       set_label_offsets (PATTERN (insn), insn, initial_p);
2406 
2407       /* ... fall through ...  */
2408 
2409     case INSN:
2410     case CALL_INSN:
2411       /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2412 	 to indirectly and hence must have all eliminations at their
2413 	 initial offsets.  */
2414       for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2415 	if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2416 	  set_label_offsets (XEXP (tem, 0), insn, 1);
2417       return;
2418 
2419     case PARALLEL:
2420     case ADDR_VEC:
2421     case ADDR_DIFF_VEC:
2422       /* Each of the labels in the parallel or address vector must be
2423 	 at their initial offsets.  We want the first field for PARALLEL
2424 	 and ADDR_VEC and the second field for ADDR_DIFF_VEC.  */
2425 
2426       for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2427 	set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2428 			   insn, initial_p);
2429       return;
2430 
2431     case SET:
2432       /* We only care about setting PC.  If the source is not RETURN,
2433 	 IF_THEN_ELSE, or a label, disable any eliminations not at
2434 	 their initial offsets.  Similarly if any arm of the IF_THEN_ELSE
2435 	 isn't one of those possibilities.  For branches to a label,
2436 	 call ourselves recursively.
2437 
2438 	 Note that this can disable elimination unnecessarily when we have
2439 	 a non-local goto since it will look like a non-constant jump to
2440 	 someplace in the current function.  This isn't a significant
2441 	 problem since such jumps will normally be when all elimination
2442 	 pairs are back to their initial offsets.  */
2443 
2444       if (SET_DEST (x) != pc_rtx)
2445 	return;
2446 
2447       switch (GET_CODE (SET_SRC (x)))
2448 	{
2449 	case PC:
2450 	case RETURN:
2451 	  return;
2452 
2453 	case LABEL_REF:
2454 	  set_label_offsets (SET_SRC (x), insn, initial_p);
2455 	  return;
2456 
2457 	case IF_THEN_ELSE:
2458 	  tem = XEXP (SET_SRC (x), 1);
2459 	  if (GET_CODE (tem) == LABEL_REF)
2460 	    set_label_offsets (XEXP (tem, 0), insn, initial_p);
2461 	  else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2462 	    break;
2463 
2464 	  tem = XEXP (SET_SRC (x), 2);
2465 	  if (GET_CODE (tem) == LABEL_REF)
2466 	    set_label_offsets (XEXP (tem, 0), insn, initial_p);
2467 	  else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2468 	    break;
2469 	  return;
2470 
2471 	default:
2472 	  break;
2473 	}
2474 
2475       /* If we reach here, all eliminations must be at their initial
2476 	 offset because we are doing a jump to a variable address.  */
2477       for (p = reg_eliminate; p < &reg_eliminate[NUM_ELIMINABLE_REGS]; p++)
2478 	if (p->offset != p->initial_offset)
2479 	  p->can_eliminate = 0;
2480       break;
2481 
2482     default:
2483       break;
2484     }
2485 }
2486 
2487 /* Called through for_each_rtx, this function examines every reg that occurs
2488    in PX and adjusts the costs for its elimination which are gathered by IRA.
2489    DATA is the insn in which PX occurs.  We do not recurse into MEM
2490    expressions.  */
2491 
2492 static int
note_reg_elim_costly(rtx * px,void * data)2493 note_reg_elim_costly (rtx *px, void *data)
2494 {
2495   rtx insn = (rtx)data;
2496   rtx x = *px;
2497 
2498   if (MEM_P (x))
2499     return -1;
2500 
2501   if (REG_P (x)
2502       && REGNO (x) >= FIRST_PSEUDO_REGISTER
2503       && reg_equiv_init (REGNO (x))
2504       && reg_equiv_invariant (REGNO (x)))
2505     {
2506       rtx t = reg_equiv_invariant (REGNO (x));
2507       rtx new_rtx = eliminate_regs_1 (t, Pmode, insn, true, true);
2508       int cost = set_src_cost (new_rtx, optimize_bb_for_speed_p (elim_bb));
2509       int freq = REG_FREQ_FROM_BB (elim_bb);
2510 
2511       if (cost != 0)
2512 	ira_adjust_equiv_reg_cost (REGNO (x), -cost * freq);
2513     }
2514   return 0;
2515 }
2516 
2517 /* Scan X and replace any eliminable registers (such as fp) with a
2518    replacement (such as sp), plus an offset.
2519 
2520    MEM_MODE is the mode of an enclosing MEM.  We need this to know how
2521    much to adjust a register for, e.g., PRE_DEC.  Also, if we are inside a
2522    MEM, we are allowed to replace a sum of a register and the constant zero
2523    with the register, which we cannot do outside a MEM.  In addition, we need
2524    to record the fact that a register is referenced outside a MEM.
2525 
2526    If INSN is an insn, it is the insn containing X.  If we replace a REG
2527    in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2528    CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2529    the REG is being modified.
2530 
2531    Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2532    That's used when we eliminate in expressions stored in notes.
2533    This means, do not set ref_outside_mem even if the reference
2534    is outside of MEMs.
2535 
2536    If FOR_COSTS is true, we are being called before reload in order to
2537    estimate the costs of keeping registers with an equivalence unallocated.
2538 
2539    REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2540    replacements done assuming all offsets are at their initial values.  If
2541    they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2542    encounter, return the actual location so that find_reloads will do
2543    the proper thing.  */
2544 
2545 static rtx
eliminate_regs_1(rtx x,enum machine_mode mem_mode,rtx insn,bool may_use_invariant,bool for_costs)2546 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2547 		  bool may_use_invariant, bool for_costs)
2548 {
2549   enum rtx_code code = GET_CODE (x);
2550   struct elim_table *ep;
2551   int regno;
2552   rtx new_rtx;
2553   int i, j;
2554   const char *fmt;
2555   int copied = 0;
2556 
2557   if (! current_function_decl)
2558     return x;
2559 
2560   switch (code)
2561     {
2562     case CONST_INT:
2563     case CONST_DOUBLE:
2564     case CONST_FIXED:
2565     case CONST_VECTOR:
2566     case CONST:
2567     case SYMBOL_REF:
2568     case CODE_LABEL:
2569     case PC:
2570     case CC0:
2571     case ASM_INPUT:
2572     case ADDR_VEC:
2573     case ADDR_DIFF_VEC:
2574     case RETURN:
2575       return x;
2576 
2577     case REG:
2578       regno = REGNO (x);
2579 
2580       /* First handle the case where we encounter a bare register that
2581 	 is eliminable.  Replace it with a PLUS.  */
2582       if (regno < FIRST_PSEUDO_REGISTER)
2583 	{
2584 	  for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
2585 	       ep++)
2586 	    if (ep->from_rtx == x && ep->can_eliminate)
2587 	      return plus_constant (ep->to_rtx, ep->previous_offset);
2588 
2589 	}
2590       else if (reg_renumber && reg_renumber[regno] < 0
2591 	       && reg_equivs
2592 	       && reg_equiv_invariant (regno))
2593 	{
2594 	  if (may_use_invariant || (insn && DEBUG_INSN_P (insn)))
2595 	    return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno)),
2596 			             mem_mode, insn, true, for_costs);
2597 	  /* There exists at least one use of REGNO that cannot be
2598 	     eliminated.  Prevent the defining insn from being deleted.  */
2599 	  reg_equiv_init (regno) = NULL_RTX;
2600 	  if (!for_costs)
2601 	    alter_reg (regno, -1, true);
2602 	}
2603       return x;
2604 
2605     /* You might think handling MINUS in a manner similar to PLUS is a
2606        good idea.  It is not.  It has been tried multiple times and every
2607        time the change has had to have been reverted.
2608 
2609        Other parts of reload know a PLUS is special (gen_reload for example)
2610        and require special code to handle code a reloaded PLUS operand.
2611 
2612        Also consider backends where the flags register is clobbered by a
2613        MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2614        lea instruction comes to mind).  If we try to reload a MINUS, we
2615        may kill the flags register that was holding a useful value.
2616 
2617        So, please before trying to handle MINUS, consider reload as a
2618        whole instead of this little section as well as the backend issues.  */
2619     case PLUS:
2620       /* If this is the sum of an eliminable register and a constant, rework
2621 	 the sum.  */
2622       if (REG_P (XEXP (x, 0))
2623 	  && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2624 	  && CONSTANT_P (XEXP (x, 1)))
2625 	{
2626 	  for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
2627 	       ep++)
2628 	    if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2629 	      {
2630 		/* The only time we want to replace a PLUS with a REG (this
2631 		   occurs when the constant operand of the PLUS is the negative
2632 		   of the offset) is when we are inside a MEM.  We won't want
2633 		   to do so at other times because that would change the
2634 		   structure of the insn in a way that reload can't handle.
2635 		   We special-case the commonest situation in
2636 		   eliminate_regs_in_insn, so just replace a PLUS with a
2637 		   PLUS here, unless inside a MEM.  */
2638 		if (mem_mode != 0 && CONST_INT_P (XEXP (x, 1))
2639 		    && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2640 		  return ep->to_rtx;
2641 		else
2642 		  return gen_rtx_PLUS (Pmode, ep->to_rtx,
2643 				       plus_constant (XEXP (x, 1),
2644 						      ep->previous_offset));
2645 	      }
2646 
2647 	  /* If the register is not eliminable, we are done since the other
2648 	     operand is a constant.  */
2649 	  return x;
2650 	}
2651 
2652       /* If this is part of an address, we want to bring any constant to the
2653 	 outermost PLUS.  We will do this by doing register replacement in
2654 	 our operands and seeing if a constant shows up in one of them.
2655 
2656 	 Note that there is no risk of modifying the structure of the insn,
2657 	 since we only get called for its operands, thus we are either
2658 	 modifying the address inside a MEM, or something like an address
2659 	 operand of a load-address insn.  */
2660 
2661       {
2662 	rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2663 				     for_costs);
2664 	rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2665 				     for_costs);
2666 
2667 	if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2668 	  {
2669 	    /* If one side is a PLUS and the other side is a pseudo that
2670 	       didn't get a hard register but has a reg_equiv_constant,
2671 	       we must replace the constant here since it may no longer
2672 	       be in the position of any operand.  */
2673 	    if (GET_CODE (new0) == PLUS && REG_P (new1)
2674 		&& REGNO (new1) >= FIRST_PSEUDO_REGISTER
2675 		&& reg_renumber[REGNO (new1)] < 0
2676 		&& reg_equivs
2677 		&& reg_equiv_constant (REGNO (new1)) != 0)
2678 	      new1 = reg_equiv_constant (REGNO (new1));
2679 	    else if (GET_CODE (new1) == PLUS && REG_P (new0)
2680 		     && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2681 		     && reg_renumber[REGNO (new0)] < 0
2682 		     && reg_equiv_constant (REGNO (new0)) != 0)
2683 	      new0 = reg_equiv_constant (REGNO (new0));
2684 
2685 	    new_rtx = form_sum (GET_MODE (x), new0, new1);
2686 
2687 	    /* As above, if we are not inside a MEM we do not want to
2688 	       turn a PLUS into something else.  We might try to do so here
2689 	       for an addition of 0 if we aren't optimizing.  */
2690 	    if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2691 	      return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2692 	    else
2693 	      return new_rtx;
2694 	  }
2695       }
2696       return x;
2697 
2698     case MULT:
2699       /* If this is the product of an eliminable register and a
2700 	 constant, apply the distribute law and move the constant out
2701 	 so that we have (plus (mult ..) ..).  This is needed in order
2702 	 to keep load-address insns valid.   This case is pathological.
2703 	 We ignore the possibility of overflow here.  */
2704       if (REG_P (XEXP (x, 0))
2705 	  && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2706 	  && CONST_INT_P (XEXP (x, 1)))
2707 	for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
2708 	     ep++)
2709 	  if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2710 	    {
2711 	      if (! mem_mode
2712 		  /* Refs inside notes or in DEBUG_INSNs don't count for
2713 		     this purpose.  */
2714 		  && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2715 				      || GET_CODE (insn) == INSN_LIST
2716 				      || DEBUG_INSN_P (insn))))
2717 		ep->ref_outside_mem = 1;
2718 
2719 	      return
2720 		plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2721 			       ep->previous_offset * INTVAL (XEXP (x, 1)));
2722 	    }
2723 
2724       /* ... fall through ...  */
2725 
2726     case CALL:
2727     case COMPARE:
2728     /* See comments before PLUS about handling MINUS.  */
2729     case MINUS:
2730     case DIV:      case UDIV:
2731     case MOD:      case UMOD:
2732     case AND:      case IOR:      case XOR:
2733     case ROTATERT: case ROTATE:
2734     case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2735     case NE:       case EQ:
2736     case GE:       case GT:       case GEU:    case GTU:
2737     case LE:       case LT:       case LEU:    case LTU:
2738       {
2739 	rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2740 				     for_costs);
2741 	rtx new1 = XEXP (x, 1)
2742 	  ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false,
2743 			      for_costs) : 0;
2744 
2745 	if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2746 	  return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2747       }
2748       return x;
2749 
2750     case EXPR_LIST:
2751       /* If we have something in XEXP (x, 0), the usual case, eliminate it.  */
2752       if (XEXP (x, 0))
2753 	{
2754 	  new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2755 				      for_costs);
2756 	  if (new_rtx != XEXP (x, 0))
2757 	    {
2758 	      /* If this is a REG_DEAD note, it is not valid anymore.
2759 		 Using the eliminated version could result in creating a
2760 		 REG_DEAD note for the stack or frame pointer.  */
2761 	      if (REG_NOTE_KIND (x) == REG_DEAD)
2762 		return (XEXP (x, 1)
2763 			? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2764 					    for_costs)
2765 			: NULL_RTX);
2766 
2767 	      x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2768 	    }
2769 	}
2770 
2771       /* ... fall through ...  */
2772 
2773     case INSN_LIST:
2774       /* Now do eliminations in the rest of the chain.  If this was
2775 	 an EXPR_LIST, this might result in allocating more memory than is
2776 	 strictly needed, but it simplifies the code.  */
2777       if (XEXP (x, 1))
2778 	{
2779 	  new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2780 				      for_costs);
2781 	  if (new_rtx != XEXP (x, 1))
2782 	    return
2783 	      gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2784 	}
2785       return x;
2786 
2787     case PRE_INC:
2788     case POST_INC:
2789     case PRE_DEC:
2790     case POST_DEC:
2791       /* We do not support elimination of a register that is modified.
2792 	 elimination_effects has already make sure that this does not
2793 	 happen.  */
2794       return x;
2795 
2796     case PRE_MODIFY:
2797     case POST_MODIFY:
2798       /* We do not support elimination of a register that is modified.
2799 	 elimination_effects has already make sure that this does not
2800 	 happen.  The only remaining case we need to consider here is
2801 	 that the increment value may be an eliminable register.  */
2802       if (GET_CODE (XEXP (x, 1)) == PLUS
2803 	  && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2804 	{
2805 	  rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2806 					  insn, true, for_costs);
2807 
2808 	  if (new_rtx != XEXP (XEXP (x, 1), 1))
2809 	    return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2810 				   gen_rtx_PLUS (GET_MODE (x),
2811 						 XEXP (x, 0), new_rtx));
2812 	}
2813       return x;
2814 
2815     case STRICT_LOW_PART:
2816     case NEG:          case NOT:
2817     case SIGN_EXTEND:  case ZERO_EXTEND:
2818     case TRUNCATE:     case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2819     case FLOAT:        case FIX:
2820     case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2821     case ABS:
2822     case SQRT:
2823     case FFS:
2824     case CLZ:
2825     case CTZ:
2826     case POPCOUNT:
2827     case PARITY:
2828     case BSWAP:
2829       new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2830 				  for_costs);
2831       if (new_rtx != XEXP (x, 0))
2832 	return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2833       return x;
2834 
2835     case SUBREG:
2836       /* Similar to above processing, but preserve SUBREG_BYTE.
2837 	 Convert (subreg (mem)) to (mem) if not paradoxical.
2838 	 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2839 	 pseudo didn't get a hard reg, we must replace this with the
2840 	 eliminated version of the memory location because push_reload
2841 	 may do the replacement in certain circumstances.  */
2842       if (REG_P (SUBREG_REG (x))
2843 	  && !paradoxical_subreg_p (x)
2844 	  && reg_equivs
2845 	  && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
2846 	{
2847 	  new_rtx = SUBREG_REG (x);
2848 	}
2849       else
2850 	new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false, for_costs);
2851 
2852       if (new_rtx != SUBREG_REG (x))
2853 	{
2854 	  int x_size = GET_MODE_SIZE (GET_MODE (x));
2855 	  int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2856 
2857 	  if (MEM_P (new_rtx)
2858 	      && ((x_size < new_size
2859 #ifdef WORD_REGISTER_OPERATIONS
2860 		   /* On these machines, combine can create rtl of the form
2861 		      (set (subreg:m1 (reg:m2 R) 0) ...)
2862 		      where m1 < m2, and expects something interesting to
2863 		      happen to the entire word.  Moreover, it will use the
2864 		      (reg:m2 R) later, expecting all bits to be preserved.
2865 		      So if the number of words is the same, preserve the
2866 		      subreg so that push_reload can see it.  */
2867 		   && ! ((x_size - 1) / UNITS_PER_WORD
2868 			 == (new_size -1 ) / UNITS_PER_WORD)
2869 #endif
2870 		   )
2871 		  || x_size == new_size)
2872 	      )
2873 	    return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2874 	  else
2875 	    return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2876 	}
2877 
2878       return x;
2879 
2880     case MEM:
2881       /* Our only special processing is to pass the mode of the MEM to our
2882 	 recursive call and copy the flags.  While we are here, handle this
2883 	 case more efficiently.  */
2884 
2885       new_rtx = eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), insn, true,
2886 				  for_costs);
2887       if (for_costs
2888 	  && memory_address_p (GET_MODE (x), XEXP (x, 0))
2889 	  && !memory_address_p (GET_MODE (x), new_rtx))
2890 	for_each_rtx (&XEXP (x, 0), note_reg_elim_costly, insn);
2891 
2892       return replace_equiv_address_nv (x, new_rtx);
2893 
2894     case USE:
2895       /* Handle insn_list USE that a call to a pure function may generate.  */
2896       new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false,
2897 				  for_costs);
2898       if (new_rtx != XEXP (x, 0))
2899 	return gen_rtx_USE (GET_MODE (x), new_rtx);
2900       return x;
2901 
2902     case CLOBBER:
2903     case ASM_OPERANDS:
2904       gcc_assert (insn && DEBUG_INSN_P (insn));
2905       break;
2906 
2907     case SET:
2908       gcc_unreachable ();
2909 
2910     default:
2911       break;
2912     }
2913 
2914   /* Process each of our operands recursively.  If any have changed, make a
2915      copy of the rtx.  */
2916   fmt = GET_RTX_FORMAT (code);
2917   for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2918     {
2919       if (*fmt == 'e')
2920 	{
2921 	  new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false,
2922 				      for_costs);
2923 	  if (new_rtx != XEXP (x, i) && ! copied)
2924 	    {
2925 	      x = shallow_copy_rtx (x);
2926 	      copied = 1;
2927 	    }
2928 	  XEXP (x, i) = new_rtx;
2929 	}
2930       else if (*fmt == 'E')
2931 	{
2932 	  int copied_vec = 0;
2933 	  for (j = 0; j < XVECLEN (x, i); j++)
2934 	    {
2935 	      new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false,
2936 					  for_costs);
2937 	      if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2938 		{
2939 		  rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2940 					     XVEC (x, i)->elem);
2941 		  if (! copied)
2942 		    {
2943 		      x = shallow_copy_rtx (x);
2944 		      copied = 1;
2945 		    }
2946 		  XVEC (x, i) = new_v;
2947 		  copied_vec = 1;
2948 		}
2949 	      XVECEXP (x, i, j) = new_rtx;
2950 	    }
2951 	}
2952     }
2953 
2954   return x;
2955 }
2956 
2957 rtx
eliminate_regs(rtx x,enum machine_mode mem_mode,rtx insn)2958 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2959 {
2960   return eliminate_regs_1 (x, mem_mode, insn, false, false);
2961 }
2962 
2963 /* Scan rtx X for modifications of elimination target registers.  Update
2964    the table of eliminables to reflect the changed state.  MEM_MODE is
2965    the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM.  */
2966 
2967 static void
elimination_effects(rtx x,enum machine_mode mem_mode)2968 elimination_effects (rtx x, enum machine_mode mem_mode)
2969 {
2970   enum rtx_code code = GET_CODE (x);
2971   struct elim_table *ep;
2972   int regno;
2973   int i, j;
2974   const char *fmt;
2975 
2976   switch (code)
2977     {
2978     case CONST_INT:
2979     case CONST_DOUBLE:
2980     case CONST_FIXED:
2981     case CONST_VECTOR:
2982     case CONST:
2983     case SYMBOL_REF:
2984     case CODE_LABEL:
2985     case PC:
2986     case CC0:
2987     case ASM_INPUT:
2988     case ADDR_VEC:
2989     case ADDR_DIFF_VEC:
2990     case RETURN:
2991       return;
2992 
2993     case REG:
2994       regno = REGNO (x);
2995 
2996       /* First handle the case where we encounter a bare register that
2997 	 is eliminable.  Replace it with a PLUS.  */
2998       if (regno < FIRST_PSEUDO_REGISTER)
2999 	{
3000 	  for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
3001 	       ep++)
3002 	    if (ep->from_rtx == x && ep->can_eliminate)
3003 	      {
3004 		if (! mem_mode)
3005 		  ep->ref_outside_mem = 1;
3006 		return;
3007 	      }
3008 
3009 	}
3010       else if (reg_renumber[regno] < 0
3011 	       && reg_equivs != 0
3012 	       && reg_equiv_constant (regno)
3013 	       && ! function_invariant_p (reg_equiv_constant (regno)))
3014 	elimination_effects (reg_equiv_constant (regno), mem_mode);
3015       return;
3016 
3017     case PRE_INC:
3018     case POST_INC:
3019     case PRE_DEC:
3020     case POST_DEC:
3021     case POST_MODIFY:
3022     case PRE_MODIFY:
3023       /* If we modify the source of an elimination rule, disable it.  */
3024       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3025 	if (ep->from_rtx == XEXP (x, 0))
3026 	  ep->can_eliminate = 0;
3027 
3028       /* If we modify the target of an elimination rule by adding a constant,
3029 	 update its offset.  If we modify the target in any other way, we'll
3030 	 have to disable the rule as well.  */
3031       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3032 	if (ep->to_rtx == XEXP (x, 0))
3033 	  {
3034 	    int size = GET_MODE_SIZE (mem_mode);
3035 
3036 	    /* If more bytes than MEM_MODE are pushed, account for them.  */
3037 #ifdef PUSH_ROUNDING
3038 	    if (ep->to_rtx == stack_pointer_rtx)
3039 	      size = PUSH_ROUNDING (size);
3040 #endif
3041 	    if (code == PRE_DEC || code == POST_DEC)
3042 	      ep->offset += size;
3043 	    else if (code == PRE_INC || code == POST_INC)
3044 	      ep->offset -= size;
3045 	    else if (code == PRE_MODIFY || code == POST_MODIFY)
3046 	      {
3047 		if (GET_CODE (XEXP (x, 1)) == PLUS
3048 		    && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
3049 		    && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
3050 		  ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
3051 		else
3052 		  ep->can_eliminate = 0;
3053 	      }
3054 	  }
3055 
3056       /* These two aren't unary operators.  */
3057       if (code == POST_MODIFY || code == PRE_MODIFY)
3058 	break;
3059 
3060       /* Fall through to generic unary operation case.  */
3061     case STRICT_LOW_PART:
3062     case NEG:          case NOT:
3063     case SIGN_EXTEND:  case ZERO_EXTEND:
3064     case TRUNCATE:     case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3065     case FLOAT:        case FIX:
3066     case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3067     case ABS:
3068     case SQRT:
3069     case FFS:
3070     case CLZ:
3071     case CTZ:
3072     case POPCOUNT:
3073     case PARITY:
3074     case BSWAP:
3075       elimination_effects (XEXP (x, 0), mem_mode);
3076       return;
3077 
3078     case SUBREG:
3079       if (REG_P (SUBREG_REG (x))
3080 	  && (GET_MODE_SIZE (GET_MODE (x))
3081 	      <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3082 	  && reg_equivs != 0
3083 	  && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
3084 	return;
3085 
3086       elimination_effects (SUBREG_REG (x), mem_mode);
3087       return;
3088 
3089     case USE:
3090       /* If using a register that is the source of an eliminate we still
3091 	 think can be performed, note it cannot be performed since we don't
3092 	 know how this register is used.  */
3093       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3094 	if (ep->from_rtx == XEXP (x, 0))
3095 	  ep->can_eliminate = 0;
3096 
3097       elimination_effects (XEXP (x, 0), mem_mode);
3098       return;
3099 
3100     case CLOBBER:
3101       /* If clobbering a register that is the replacement register for an
3102 	 elimination we still think can be performed, note that it cannot
3103 	 be performed.  Otherwise, we need not be concerned about it.  */
3104       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3105 	if (ep->to_rtx == XEXP (x, 0))
3106 	  ep->can_eliminate = 0;
3107 
3108       elimination_effects (XEXP (x, 0), mem_mode);
3109       return;
3110 
3111     case SET:
3112       /* Check for setting a register that we know about.  */
3113       if (REG_P (SET_DEST (x)))
3114 	{
3115 	  /* See if this is setting the replacement register for an
3116 	     elimination.
3117 
3118 	     If DEST is the hard frame pointer, we do nothing because we
3119 	     assume that all assignments to the frame pointer are for
3120 	     non-local gotos and are being done at a time when they are valid
3121 	     and do not disturb anything else.  Some machines want to
3122 	     eliminate a fake argument pointer (or even a fake frame pointer)
3123 	     with either the real frame or the stack pointer.  Assignments to
3124 	     the hard frame pointer must not prevent this elimination.  */
3125 
3126 	  for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
3127 	       ep++)
3128 	    if (ep->to_rtx == SET_DEST (x)
3129 		&& SET_DEST (x) != hard_frame_pointer_rtx)
3130 	      {
3131 		/* If it is being incremented, adjust the offset.  Otherwise,
3132 		   this elimination can't be done.  */
3133 		rtx src = SET_SRC (x);
3134 
3135 		if (GET_CODE (src) == PLUS
3136 		    && XEXP (src, 0) == SET_DEST (x)
3137 		    && CONST_INT_P (XEXP (src, 1)))
3138 		  ep->offset -= INTVAL (XEXP (src, 1));
3139 		else
3140 		  ep->can_eliminate = 0;
3141 	      }
3142 	}
3143 
3144       elimination_effects (SET_DEST (x), VOIDmode);
3145       elimination_effects (SET_SRC (x), VOIDmode);
3146       return;
3147 
3148     case MEM:
3149       /* Our only special processing is to pass the mode of the MEM to our
3150 	 recursive call.  */
3151       elimination_effects (XEXP (x, 0), GET_MODE (x));
3152       return;
3153 
3154     default:
3155       break;
3156     }
3157 
3158   fmt = GET_RTX_FORMAT (code);
3159   for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3160     {
3161       if (*fmt == 'e')
3162 	elimination_effects (XEXP (x, i), mem_mode);
3163       else if (*fmt == 'E')
3164 	for (j = 0; j < XVECLEN (x, i); j++)
3165 	  elimination_effects (XVECEXP (x, i, j), mem_mode);
3166     }
3167 }
3168 
3169 /* Descend through rtx X and verify that no references to eliminable registers
3170    remain.  If any do remain, mark the involved register as not
3171    eliminable.  */
3172 
3173 static void
check_eliminable_occurrences(rtx x)3174 check_eliminable_occurrences (rtx x)
3175 {
3176   const char *fmt;
3177   int i;
3178   enum rtx_code code;
3179 
3180   if (x == 0)
3181     return;
3182 
3183   code = GET_CODE (x);
3184 
3185   if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3186     {
3187       struct elim_table *ep;
3188 
3189       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3190 	if (ep->from_rtx == x)
3191 	  ep->can_eliminate = 0;
3192       return;
3193     }
3194 
3195   fmt = GET_RTX_FORMAT (code);
3196   for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3197     {
3198       if (*fmt == 'e')
3199 	check_eliminable_occurrences (XEXP (x, i));
3200       else if (*fmt == 'E')
3201 	{
3202 	  int j;
3203 	  for (j = 0; j < XVECLEN (x, i); j++)
3204 	    check_eliminable_occurrences (XVECEXP (x, i, j));
3205 	}
3206     }
3207 }
3208 
3209 /* Scan INSN and eliminate all eliminable registers in it.
3210 
3211    If REPLACE is nonzero, do the replacement destructively.  Also
3212    delete the insn as dead it if it is setting an eliminable register.
3213 
3214    If REPLACE is zero, do all our allocations in reload_obstack.
3215 
3216    If no eliminations were done and this insn doesn't require any elimination
3217    processing (these are not identical conditions: it might be updating sp,
3218    but not referencing fp; this needs to be seen during reload_as_needed so
3219    that the offset between fp and sp can be taken into consideration), zero
3220    is returned.  Otherwise, 1 is returned.  */
3221 
3222 static int
eliminate_regs_in_insn(rtx insn,int replace)3223 eliminate_regs_in_insn (rtx insn, int replace)
3224 {
3225   int icode = recog_memoized (insn);
3226   rtx old_body = PATTERN (insn);
3227   int insn_is_asm = asm_noperands (old_body) >= 0;
3228   rtx old_set = single_set (insn);
3229   rtx new_body;
3230   int val = 0;
3231   int i;
3232   rtx substed_operand[MAX_RECOG_OPERANDS];
3233   rtx orig_operand[MAX_RECOG_OPERANDS];
3234   struct elim_table *ep;
3235   rtx plus_src, plus_cst_src;
3236 
3237   if (! insn_is_asm && icode < 0)
3238     {
3239       gcc_assert (GET_CODE (PATTERN (insn)) == USE
3240 		  || GET_CODE (PATTERN (insn)) == CLOBBER
3241 		  || GET_CODE (PATTERN (insn)) == ADDR_VEC
3242 		  || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3243 		  || GET_CODE (PATTERN (insn)) == ASM_INPUT
3244 		  || DEBUG_INSN_P (insn));
3245       if (DEBUG_INSN_P (insn))
3246 	INSN_VAR_LOCATION_LOC (insn)
3247 	  = eliminate_regs (INSN_VAR_LOCATION_LOC (insn), VOIDmode, insn);
3248       return 0;
3249     }
3250 
3251   if (old_set != 0 && REG_P (SET_DEST (old_set))
3252       && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3253     {
3254       /* Check for setting an eliminable register.  */
3255       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3256 	if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3257 	  {
3258 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
3259 	    /* If this is setting the frame pointer register to the
3260 	       hardware frame pointer register and this is an elimination
3261 	       that will be done (tested above), this insn is really
3262 	       adjusting the frame pointer downward to compensate for
3263 	       the adjustment done before a nonlocal goto.  */
3264 	    if (ep->from == FRAME_POINTER_REGNUM
3265 		&& ep->to == HARD_FRAME_POINTER_REGNUM)
3266 	      {
3267 		rtx base = SET_SRC (old_set);
3268 		rtx base_insn = insn;
3269 		HOST_WIDE_INT offset = 0;
3270 
3271 		while (base != ep->to_rtx)
3272 		  {
3273 		    rtx prev_insn, prev_set;
3274 
3275 		    if (GET_CODE (base) == PLUS
3276 		        && CONST_INT_P (XEXP (base, 1)))
3277 		      {
3278 		        offset += INTVAL (XEXP (base, 1));
3279 		        base = XEXP (base, 0);
3280 		      }
3281 		    else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3282 			     && (prev_set = single_set (prev_insn)) != 0
3283 			     && rtx_equal_p (SET_DEST (prev_set), base))
3284 		      {
3285 		        base = SET_SRC (prev_set);
3286 		        base_insn = prev_insn;
3287 		      }
3288 		    else
3289 		      break;
3290 		  }
3291 
3292 		if (base == ep->to_rtx)
3293 		  {
3294 		    rtx src
3295 		      = plus_constant (ep->to_rtx, offset - ep->offset);
3296 
3297 		    new_body = old_body;
3298 		    if (! replace)
3299 		      {
3300 			new_body = copy_insn (old_body);
3301 			if (REG_NOTES (insn))
3302 			  REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3303 		      }
3304 		    PATTERN (insn) = new_body;
3305 		    old_set = single_set (insn);
3306 
3307 		    /* First see if this insn remains valid when we
3308 		       make the change.  If not, keep the INSN_CODE
3309 		       the same and let reload fit it up.  */
3310 		    validate_change (insn, &SET_SRC (old_set), src, 1);
3311 		    validate_change (insn, &SET_DEST (old_set),
3312 				     ep->to_rtx, 1);
3313 		    if (! apply_change_group ())
3314 		      {
3315 			SET_SRC (old_set) = src;
3316 			SET_DEST (old_set) = ep->to_rtx;
3317 		      }
3318 
3319 		    val = 1;
3320 		    goto done;
3321 		  }
3322 	      }
3323 #endif
3324 
3325 	    /* In this case this insn isn't serving a useful purpose.  We
3326 	       will delete it in reload_as_needed once we know that this
3327 	       elimination is, in fact, being done.
3328 
3329 	       If REPLACE isn't set, we can't delete this insn, but needn't
3330 	       process it since it won't be used unless something changes.  */
3331 	    if (replace)
3332 	      {
3333 		delete_dead_insn (insn);
3334 		return 1;
3335 	      }
3336 	    val = 1;
3337 	    goto done;
3338 	  }
3339     }
3340 
3341   /* We allow one special case which happens to work on all machines we
3342      currently support: a single set with the source or a REG_EQUAL
3343      note being a PLUS of an eliminable register and a constant.  */
3344   plus_src = plus_cst_src = 0;
3345   if (old_set && REG_P (SET_DEST (old_set)))
3346     {
3347       if (GET_CODE (SET_SRC (old_set)) == PLUS)
3348 	plus_src = SET_SRC (old_set);
3349       /* First see if the source is of the form (plus (...) CST).  */
3350       if (plus_src
3351 	  && CONST_INT_P (XEXP (plus_src, 1)))
3352 	plus_cst_src = plus_src;
3353       else if (REG_P (SET_SRC (old_set))
3354 	       || plus_src)
3355 	{
3356 	  /* Otherwise, see if we have a REG_EQUAL note of the form
3357 	     (plus (...) CST).  */
3358 	  rtx links;
3359 	  for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3360 	    {
3361 	      if ((REG_NOTE_KIND (links) == REG_EQUAL
3362 		   || REG_NOTE_KIND (links) == REG_EQUIV)
3363 		  && GET_CODE (XEXP (links, 0)) == PLUS
3364 		  && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3365 		{
3366 		  plus_cst_src = XEXP (links, 0);
3367 		  break;
3368 		}
3369 	    }
3370 	}
3371 
3372       /* Check that the first operand of the PLUS is a hard reg or
3373 	 the lowpart subreg of one.  */
3374       if (plus_cst_src)
3375 	{
3376 	  rtx reg = XEXP (plus_cst_src, 0);
3377 	  if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3378 	    reg = SUBREG_REG (reg);
3379 
3380 	  if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3381 	    plus_cst_src = 0;
3382 	}
3383     }
3384   if (plus_cst_src)
3385     {
3386       rtx reg = XEXP (plus_cst_src, 0);
3387       HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3388 
3389       if (GET_CODE (reg) == SUBREG)
3390 	reg = SUBREG_REG (reg);
3391 
3392       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3393 	if (ep->from_rtx == reg && ep->can_eliminate)
3394 	  {
3395 	    rtx to_rtx = ep->to_rtx;
3396 	    offset += ep->offset;
3397 	    offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3398 
3399 	    if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3400 	      to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3401 				    to_rtx);
3402 	    /* If we have a nonzero offset, and the source is already
3403 	       a simple REG, the following transformation would
3404 	       increase the cost of the insn by replacing a simple REG
3405 	       with (plus (reg sp) CST).  So try only when we already
3406 	       had a PLUS before.  */
3407 	    if (offset == 0 || plus_src)
3408 	      {
3409 		rtx new_src = plus_constant (to_rtx, offset);
3410 
3411 		new_body = old_body;
3412 		if (! replace)
3413 		  {
3414 		    new_body = copy_insn (old_body);
3415 		    if (REG_NOTES (insn))
3416 		      REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3417 		  }
3418 		PATTERN (insn) = new_body;
3419 		old_set = single_set (insn);
3420 
3421 		/* First see if this insn remains valid when we make the
3422 		   change.  If not, try to replace the whole pattern with
3423 		   a simple set (this may help if the original insn was a
3424 		   PARALLEL that was only recognized as single_set due to
3425 		   REG_UNUSED notes).  If this isn't valid either, keep
3426 		   the INSN_CODE the same and let reload fix it up.  */
3427 		if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3428 		  {
3429 		    rtx new_pat = gen_rtx_SET (VOIDmode,
3430 					       SET_DEST (old_set), new_src);
3431 
3432 		    if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3433 		      SET_SRC (old_set) = new_src;
3434 		  }
3435 	      }
3436 	    else
3437 	      break;
3438 
3439 	    val = 1;
3440 	    /* This can't have an effect on elimination offsets, so skip right
3441 	       to the end.  */
3442 	    goto done;
3443 	  }
3444     }
3445 
3446   /* Determine the effects of this insn on elimination offsets.  */
3447   elimination_effects (old_body, VOIDmode);
3448 
3449   /* Eliminate all eliminable registers occurring in operands that
3450      can be handled by reload.  */
3451   extract_insn (insn);
3452   for (i = 0; i < recog_data.n_operands; i++)
3453     {
3454       orig_operand[i] = recog_data.operand[i];
3455       substed_operand[i] = recog_data.operand[i];
3456 
3457       /* For an asm statement, every operand is eliminable.  */
3458       if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3459 	{
3460 	  bool is_set_src, in_plus;
3461 
3462 	  /* Check for setting a register that we know about.  */
3463 	  if (recog_data.operand_type[i] != OP_IN
3464 	      && REG_P (orig_operand[i]))
3465 	    {
3466 	      /* If we are assigning to a register that can be eliminated, it
3467 		 must be as part of a PARALLEL, since the code above handles
3468 		 single SETs.  We must indicate that we can no longer
3469 		 eliminate this reg.  */
3470 	      for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
3471 		   ep++)
3472 		if (ep->from_rtx == orig_operand[i])
3473 		  ep->can_eliminate = 0;
3474 	    }
3475 
3476 	  /* Companion to the above plus substitution, we can allow
3477 	     invariants as the source of a plain move.  */
3478 	  is_set_src = false;
3479 	  if (old_set
3480 	      && recog_data.operand_loc[i] == &SET_SRC (old_set))
3481 	    is_set_src = true;
3482 	  in_plus = false;
3483 	  if (plus_src
3484 	      && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3485 		  || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3486 	    in_plus = true;
3487 
3488 	  substed_operand[i]
3489 	    = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3490 			        replace ? insn : NULL_RTX,
3491 				is_set_src || in_plus, false);
3492 	  if (substed_operand[i] != orig_operand[i])
3493 	    val = 1;
3494 	  /* Terminate the search in check_eliminable_occurrences at
3495 	     this point.  */
3496 	  *recog_data.operand_loc[i] = 0;
3497 
3498 	  /* If an output operand changed from a REG to a MEM and INSN is an
3499 	     insn, write a CLOBBER insn.  */
3500 	  if (recog_data.operand_type[i] != OP_IN
3501 	      && REG_P (orig_operand[i])
3502 	      && MEM_P (substed_operand[i])
3503 	      && replace)
3504 	    emit_insn_after (gen_clobber (orig_operand[i]), insn);
3505 	}
3506     }
3507 
3508   for (i = 0; i < recog_data.n_dups; i++)
3509     *recog_data.dup_loc[i]
3510       = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3511 
3512   /* If any eliminable remain, they aren't eliminable anymore.  */
3513   check_eliminable_occurrences (old_body);
3514 
3515   /* Substitute the operands; the new values are in the substed_operand
3516      array.  */
3517   for (i = 0; i < recog_data.n_operands; i++)
3518     *recog_data.operand_loc[i] = substed_operand[i];
3519   for (i = 0; i < recog_data.n_dups; i++)
3520     *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3521 
3522   /* If we are replacing a body that was a (set X (plus Y Z)), try to
3523      re-recognize the insn.  We do this in case we had a simple addition
3524      but now can do this as a load-address.  This saves an insn in this
3525      common case.
3526      If re-recognition fails, the old insn code number will still be used,
3527      and some register operands may have changed into PLUS expressions.
3528      These will be handled by find_reloads by loading them into a register
3529      again.  */
3530 
3531   if (val)
3532     {
3533       /* If we aren't replacing things permanently and we changed something,
3534 	 make another copy to ensure that all the RTL is new.  Otherwise
3535 	 things can go wrong if find_reload swaps commutative operands
3536 	 and one is inside RTL that has been copied while the other is not.  */
3537       new_body = old_body;
3538       if (! replace)
3539 	{
3540 	  new_body = copy_insn (old_body);
3541 	  if (REG_NOTES (insn))
3542 	    REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3543 	}
3544       PATTERN (insn) = new_body;
3545 
3546       /* If we had a move insn but now we don't, rerecognize it.  This will
3547 	 cause spurious re-recognition if the old move had a PARALLEL since
3548 	 the new one still will, but we can't call single_set without
3549 	 having put NEW_BODY into the insn and the re-recognition won't
3550 	 hurt in this rare case.  */
3551       /* ??? Why this huge if statement - why don't we just rerecognize the
3552 	 thing always?  */
3553       if (! insn_is_asm
3554 	  && old_set != 0
3555 	  && ((REG_P (SET_SRC (old_set))
3556 	       && (GET_CODE (new_body) != SET
3557 		   || !REG_P (SET_SRC (new_body))))
3558 	      /* If this was a load from or store to memory, compare
3559 		 the MEM in recog_data.operand to the one in the insn.
3560 		 If they are not equal, then rerecognize the insn.  */
3561 	      || (old_set != 0
3562 		  && ((MEM_P (SET_SRC (old_set))
3563 		       && SET_SRC (old_set) != recog_data.operand[1])
3564 		      || (MEM_P (SET_DEST (old_set))
3565 			  && SET_DEST (old_set) != recog_data.operand[0])))
3566 	      /* If this was an add insn before, rerecognize.  */
3567 	      || GET_CODE (SET_SRC (old_set)) == PLUS))
3568 	{
3569 	  int new_icode = recog (PATTERN (insn), insn, 0);
3570 	  if (new_icode >= 0)
3571 	    INSN_CODE (insn) = new_icode;
3572 	}
3573     }
3574 
3575   /* Restore the old body.  If there were any changes to it, we made a copy
3576      of it while the changes were still in place, so we'll correctly return
3577      a modified insn below.  */
3578   if (! replace)
3579     {
3580       /* Restore the old body.  */
3581       for (i = 0; i < recog_data.n_operands; i++)
3582 	/* Restoring a top-level match_parallel would clobber the new_body
3583 	   we installed in the insn.  */
3584 	if (recog_data.operand_loc[i] != &PATTERN (insn))
3585 	  *recog_data.operand_loc[i] = orig_operand[i];
3586       for (i = 0; i < recog_data.n_dups; i++)
3587 	*recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3588     }
3589 
3590   /* Update all elimination pairs to reflect the status after the current
3591      insn.  The changes we make were determined by the earlier call to
3592      elimination_effects.
3593 
3594      We also detect cases where register elimination cannot be done,
3595      namely, if a register would be both changed and referenced outside a MEM
3596      in the resulting insn since such an insn is often undefined and, even if
3597      not, we cannot know what meaning will be given to it.  Note that it is
3598      valid to have a register used in an address in an insn that changes it
3599      (presumably with a pre- or post-increment or decrement).
3600 
3601      If anything changes, return nonzero.  */
3602 
3603   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3604     {
3605       if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3606 	ep->can_eliminate = 0;
3607 
3608       ep->ref_outside_mem = 0;
3609 
3610       if (ep->previous_offset != ep->offset)
3611 	val = 1;
3612     }
3613 
3614  done:
3615   /* If we changed something, perform elimination in REG_NOTES.  This is
3616      needed even when REPLACE is zero because a REG_DEAD note might refer
3617      to a register that we eliminate and could cause a different number
3618      of spill registers to be needed in the final reload pass than in
3619      the pre-passes.  */
3620   if (val && REG_NOTES (insn) != 0)
3621     REG_NOTES (insn)
3622       = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true,
3623 			  false);
3624 
3625   return val;
3626 }
3627 
3628 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3629    register allocator.  INSN is the instruction we need to examine, we perform
3630    eliminations in its operands and record cases where eliminating a reg with
3631    an invariant equivalence would add extra cost.  */
3632 
3633 static void
elimination_costs_in_insn(rtx insn)3634 elimination_costs_in_insn (rtx insn)
3635 {
3636   int icode = recog_memoized (insn);
3637   rtx old_body = PATTERN (insn);
3638   int insn_is_asm = asm_noperands (old_body) >= 0;
3639   rtx old_set = single_set (insn);
3640   int i;
3641   rtx orig_operand[MAX_RECOG_OPERANDS];
3642   rtx orig_dup[MAX_RECOG_OPERANDS];
3643   struct elim_table *ep;
3644   rtx plus_src, plus_cst_src;
3645   bool sets_reg_p;
3646 
3647   if (! insn_is_asm && icode < 0)
3648     {
3649       gcc_assert (GET_CODE (PATTERN (insn)) == USE
3650 		  || GET_CODE (PATTERN (insn)) == CLOBBER
3651 		  || GET_CODE (PATTERN (insn)) == ADDR_VEC
3652 		  || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3653 		  || GET_CODE (PATTERN (insn)) == ASM_INPUT
3654 		  || DEBUG_INSN_P (insn));
3655       return;
3656     }
3657 
3658   if (old_set != 0 && REG_P (SET_DEST (old_set))
3659       && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3660     {
3661       /* Check for setting an eliminable register.  */
3662       for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3663 	if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3664 	  return;
3665     }
3666 
3667   /* We allow one special case which happens to work on all machines we
3668      currently support: a single set with the source or a REG_EQUAL
3669      note being a PLUS of an eliminable register and a constant.  */
3670   plus_src = plus_cst_src = 0;
3671   sets_reg_p = false;
3672   if (old_set && REG_P (SET_DEST (old_set)))
3673     {
3674       sets_reg_p = true;
3675       if (GET_CODE (SET_SRC (old_set)) == PLUS)
3676 	plus_src = SET_SRC (old_set);
3677       /* First see if the source is of the form (plus (...) CST).  */
3678       if (plus_src
3679 	  && CONST_INT_P (XEXP (plus_src, 1)))
3680 	plus_cst_src = plus_src;
3681       else if (REG_P (SET_SRC (old_set))
3682 	       || plus_src)
3683 	{
3684 	  /* Otherwise, see if we have a REG_EQUAL note of the form
3685 	     (plus (...) CST).  */
3686 	  rtx links;
3687 	  for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3688 	    {
3689 	      if ((REG_NOTE_KIND (links) == REG_EQUAL
3690 		   || REG_NOTE_KIND (links) == REG_EQUIV)
3691 		  && GET_CODE (XEXP (links, 0)) == PLUS
3692 		  && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3693 		{
3694 		  plus_cst_src = XEXP (links, 0);
3695 		  break;
3696 		}
3697 	    }
3698 	}
3699     }
3700 
3701   /* Determine the effects of this insn on elimination offsets.  */
3702   elimination_effects (old_body, VOIDmode);
3703 
3704   /* Eliminate all eliminable registers occurring in operands that
3705      can be handled by reload.  */
3706   extract_insn (insn);
3707   for (i = 0; i < recog_data.n_dups; i++)
3708     orig_dup[i] = *recog_data.dup_loc[i];
3709 
3710   for (i = 0; i < recog_data.n_operands; i++)
3711     {
3712       orig_operand[i] = recog_data.operand[i];
3713 
3714       /* For an asm statement, every operand is eliminable.  */
3715       if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3716 	{
3717 	  bool is_set_src, in_plus;
3718 
3719 	  /* Check for setting a register that we know about.  */
3720 	  if (recog_data.operand_type[i] != OP_IN
3721 	      && REG_P (orig_operand[i]))
3722 	    {
3723 	      /* If we are assigning to a register that can be eliminated, it
3724 		 must be as part of a PARALLEL, since the code above handles
3725 		 single SETs.  We must indicate that we can no longer
3726 		 eliminate this reg.  */
3727 	      for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
3728 		   ep++)
3729 		if (ep->from_rtx == orig_operand[i])
3730 		  ep->can_eliminate = 0;
3731 	    }
3732 
3733 	  /* Companion to the above plus substitution, we can allow
3734 	     invariants as the source of a plain move.  */
3735 	  is_set_src = false;
3736 	  if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3737 	    is_set_src = true;
3738 	  if (is_set_src && !sets_reg_p)
3739 	    note_reg_elim_costly (&SET_SRC (old_set), insn);
3740 	  in_plus = false;
3741 	  if (plus_src && sets_reg_p
3742 	      && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3743 		  || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3744 	    in_plus = true;
3745 
3746 	  eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3747 			    NULL_RTX,
3748 			    is_set_src || in_plus, true);
3749 	  /* Terminate the search in check_eliminable_occurrences at
3750 	     this point.  */
3751 	  *recog_data.operand_loc[i] = 0;
3752 	}
3753     }
3754 
3755   for (i = 0; i < recog_data.n_dups; i++)
3756     *recog_data.dup_loc[i]
3757       = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3758 
3759   /* If any eliminable remain, they aren't eliminable anymore.  */
3760   check_eliminable_occurrences (old_body);
3761 
3762   /* Restore the old body.  */
3763   for (i = 0; i < recog_data.n_operands; i++)
3764     *recog_data.operand_loc[i] = orig_operand[i];
3765   for (i = 0; i < recog_data.n_dups; i++)
3766     *recog_data.dup_loc[i] = orig_dup[i];
3767 
3768   /* Update all elimination pairs to reflect the status after the current
3769      insn.  The changes we make were determined by the earlier call to
3770      elimination_effects.  */
3771 
3772   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3773     {
3774       if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3775 	ep->can_eliminate = 0;
3776 
3777       ep->ref_outside_mem = 0;
3778     }
3779 
3780   return;
3781 }
3782 
3783 /* Loop through all elimination pairs.
3784    Recalculate the number not at initial offset.
3785 
3786    Compute the maximum offset (minimum offset if the stack does not
3787    grow downward) for each elimination pair.  */
3788 
3789 static void
update_eliminable_offsets(void)3790 update_eliminable_offsets (void)
3791 {
3792   struct elim_table *ep;
3793 
3794   num_not_at_initial_offset = 0;
3795   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3796     {
3797       ep->previous_offset = ep->offset;
3798       if (ep->can_eliminate && ep->offset != ep->initial_offset)
3799 	num_not_at_initial_offset++;
3800     }
3801 }
3802 
3803 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3804    replacement we currently believe is valid, mark it as not eliminable if X
3805    modifies DEST in any way other than by adding a constant integer to it.
3806 
3807    If DEST is the frame pointer, we do nothing because we assume that
3808    all assignments to the hard frame pointer are nonlocal gotos and are being
3809    done at a time when they are valid and do not disturb anything else.
3810    Some machines want to eliminate a fake argument pointer with either the
3811    frame or stack pointer.  Assignments to the hard frame pointer must not
3812    prevent this elimination.
3813 
3814    Called via note_stores from reload before starting its passes to scan
3815    the insns of the function.  */
3816 
3817 static void
mark_not_eliminable(rtx dest,const_rtx x,void * data ATTRIBUTE_UNUSED)3818 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3819 {
3820   unsigned int i;
3821 
3822   /* A SUBREG of a hard register here is just changing its mode.  We should
3823      not see a SUBREG of an eliminable hard register, but check just in
3824      case.  */
3825   if (GET_CODE (dest) == SUBREG)
3826     dest = SUBREG_REG (dest);
3827 
3828   if (dest == hard_frame_pointer_rtx)
3829     return;
3830 
3831   for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3832     if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3833 	&& (GET_CODE (x) != SET
3834 	    || GET_CODE (SET_SRC (x)) != PLUS
3835 	    || XEXP (SET_SRC (x), 0) != dest
3836 	    || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
3837       {
3838 	reg_eliminate[i].can_eliminate_previous
3839 	  = reg_eliminate[i].can_eliminate = 0;
3840 	num_eliminable--;
3841       }
3842 }
3843 
3844 /* Verify that the initial elimination offsets did not change since the
3845    last call to set_initial_elim_offsets.  This is used to catch cases
3846    where something illegal happened during reload_as_needed that could
3847    cause incorrect code to be generated if we did not check for it.  */
3848 
3849 static bool
verify_initial_elim_offsets(void)3850 verify_initial_elim_offsets (void)
3851 {
3852   HOST_WIDE_INT t;
3853 
3854   if (!num_eliminable)
3855     return true;
3856 
3857 #ifdef ELIMINABLE_REGS
3858   {
3859    struct elim_table *ep;
3860 
3861    for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3862      {
3863        INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3864        if (t != ep->initial_offset)
3865 	 return false;
3866      }
3867   }
3868 #else
3869   INITIAL_FRAME_POINTER_OFFSET (t);
3870   if (t != reg_eliminate[0].initial_offset)
3871     return false;
3872 #endif
3873 
3874   return true;
3875 }
3876 
3877 /* Reset all offsets on eliminable registers to their initial values.  */
3878 
3879 static void
set_initial_elim_offsets(void)3880 set_initial_elim_offsets (void)
3881 {
3882   struct elim_table *ep = reg_eliminate;
3883 
3884 #ifdef ELIMINABLE_REGS
3885   for (; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3886     {
3887       INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3888       ep->previous_offset = ep->offset = ep->initial_offset;
3889     }
3890 #else
3891   INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3892   ep->previous_offset = ep->offset = ep->initial_offset;
3893 #endif
3894 
3895   num_not_at_initial_offset = 0;
3896 }
3897 
3898 /* Subroutine of set_initial_label_offsets called via for_each_eh_label.  */
3899 
3900 static void
set_initial_eh_label_offset(rtx label)3901 set_initial_eh_label_offset (rtx label)
3902 {
3903   set_label_offsets (label, NULL_RTX, 1);
3904 }
3905 
3906 /* Initialize the known label offsets.
3907    Set a known offset for each forced label to be at the initial offset
3908    of each elimination.  We do this because we assume that all
3909    computed jumps occur from a location where each elimination is
3910    at its initial offset.
3911    For all other labels, show that we don't know the offsets.  */
3912 
3913 static void
set_initial_label_offsets(void)3914 set_initial_label_offsets (void)
3915 {
3916   rtx x;
3917   memset (offsets_known_at, 0, num_labels);
3918 
3919   for (x = forced_labels; x; x = XEXP (x, 1))
3920     if (XEXP (x, 0))
3921       set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3922 
3923   for (x = nonlocal_goto_handler_labels; x; x = XEXP (x, 1))
3924     if (XEXP (x, 0))
3925       set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3926 
3927   for_each_eh_label (set_initial_eh_label_offset);
3928 }
3929 
3930 /* Set all elimination offsets to the known values for the code label given
3931    by INSN.  */
3932 
3933 static void
set_offsets_for_label(rtx insn)3934 set_offsets_for_label (rtx insn)
3935 {
3936   unsigned int i;
3937   int label_nr = CODE_LABEL_NUMBER (insn);
3938   struct elim_table *ep;
3939 
3940   num_not_at_initial_offset = 0;
3941   for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3942     {
3943       ep->offset = ep->previous_offset
3944 		 = offsets_at[label_nr - first_label_num][i];
3945       if (ep->can_eliminate && ep->offset != ep->initial_offset)
3946 	num_not_at_initial_offset++;
3947     }
3948 }
3949 
3950 /* See if anything that happened changes which eliminations are valid.
3951    For example, on the SPARC, whether or not the frame pointer can
3952    be eliminated can depend on what registers have been used.  We need
3953    not check some conditions again (such as flag_omit_frame_pointer)
3954    since they can't have changed.  */
3955 
3956 static void
update_eliminables(HARD_REG_SET * pset)3957 update_eliminables (HARD_REG_SET *pset)
3958 {
3959   int previous_frame_pointer_needed = frame_pointer_needed;
3960   struct elim_table *ep;
3961 
3962   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3963     if ((ep->from == HARD_FRAME_POINTER_REGNUM
3964          && targetm.frame_pointer_required ())
3965 #ifdef ELIMINABLE_REGS
3966 	|| ! targetm.can_eliminate (ep->from, ep->to)
3967 #endif
3968 	)
3969       ep->can_eliminate = 0;
3970 
3971   /* Look for the case where we have discovered that we can't replace
3972      register A with register B and that means that we will now be
3973      trying to replace register A with register C.  This means we can
3974      no longer replace register C with register B and we need to disable
3975      such an elimination, if it exists.  This occurs often with A == ap,
3976      B == sp, and C == fp.  */
3977 
3978   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3979     {
3980       struct elim_table *op;
3981       int new_to = -1;
3982 
3983       if (! ep->can_eliminate && ep->can_eliminate_previous)
3984 	{
3985 	  /* Find the current elimination for ep->from, if there is a
3986 	     new one.  */
3987 	  for (op = reg_eliminate;
3988 	       op < &reg_eliminate[NUM_ELIMINABLE_REGS]; op++)
3989 	    if (op->from == ep->from && op->can_eliminate)
3990 	      {
3991 		new_to = op->to;
3992 		break;
3993 	      }
3994 
3995 	  /* See if there is an elimination of NEW_TO -> EP->TO.  If so,
3996 	     disable it.  */
3997 	  for (op = reg_eliminate;
3998 	       op < &reg_eliminate[NUM_ELIMINABLE_REGS]; op++)
3999 	    if (op->from == new_to && op->to == ep->to)
4000 	      op->can_eliminate = 0;
4001 	}
4002     }
4003 
4004   /* See if any registers that we thought we could eliminate the previous
4005      time are no longer eliminable.  If so, something has changed and we
4006      must spill the register.  Also, recompute the number of eliminable
4007      registers and see if the frame pointer is needed; it is if there is
4008      no elimination of the frame pointer that we can perform.  */
4009 
4010   frame_pointer_needed = 1;
4011   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4012     {
4013       if (ep->can_eliminate
4014 	  && ep->from == FRAME_POINTER_REGNUM
4015 	  && ep->to != HARD_FRAME_POINTER_REGNUM
4016 	  && (! SUPPORTS_STACK_ALIGNMENT
4017 	      || ! crtl->stack_realign_needed))
4018 	frame_pointer_needed = 0;
4019 
4020       if (! ep->can_eliminate && ep->can_eliminate_previous)
4021 	{
4022 	  ep->can_eliminate_previous = 0;
4023 	  SET_HARD_REG_BIT (*pset, ep->from);
4024 	  num_eliminable--;
4025 	}
4026     }
4027 
4028   /* If we didn't need a frame pointer last time, but we do now, spill
4029      the hard frame pointer.  */
4030   if (frame_pointer_needed && ! previous_frame_pointer_needed)
4031     SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
4032 }
4033 
4034 /* Return true if X is used as the target register of an elimination.  */
4035 
4036 bool
elimination_target_reg_p(rtx x)4037 elimination_target_reg_p (rtx x)
4038 {
4039   struct elim_table *ep;
4040 
4041   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4042     if (ep->to_rtx == x && ep->can_eliminate)
4043       return true;
4044 
4045   return false;
4046 }
4047 
4048 /* Initialize the table of registers to eliminate.
4049    Pre-condition: global flag frame_pointer_needed has been set before
4050    calling this function.  */
4051 
4052 static void
init_elim_table(void)4053 init_elim_table (void)
4054 {
4055   struct elim_table *ep;
4056 #ifdef ELIMINABLE_REGS
4057   const struct elim_table_1 *ep1;
4058 #endif
4059 
4060   if (!reg_eliminate)
4061     reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
4062 
4063   num_eliminable = 0;
4064 
4065 #ifdef ELIMINABLE_REGS
4066   for (ep = reg_eliminate, ep1 = reg_eliminate_1;
4067        ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
4068     {
4069       ep->from = ep1->from;
4070       ep->to = ep1->to;
4071       ep->can_eliminate = ep->can_eliminate_previous
4072 	= (targetm.can_eliminate (ep->from, ep->to)
4073 	   && ! (ep->to == STACK_POINTER_REGNUM
4074 		 && frame_pointer_needed
4075 		 && (! SUPPORTS_STACK_ALIGNMENT
4076 		     || ! stack_realign_fp)));
4077     }
4078 #else
4079   reg_eliminate[0].from = reg_eliminate_1[0].from;
4080   reg_eliminate[0].to = reg_eliminate_1[0].to;
4081   reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
4082     = ! frame_pointer_needed;
4083 #endif
4084 
4085   /* Count the number of eliminable registers and build the FROM and TO
4086      REG rtx's.  Note that code in gen_rtx_REG will cause, e.g.,
4087      gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
4088      We depend on this.  */
4089   for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4090     {
4091       num_eliminable += ep->can_eliminate;
4092       ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
4093       ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
4094     }
4095 }
4096 
4097 /* Find all the pseudo registers that didn't get hard regs
4098    but do have known equivalent constants or memory slots.
4099    These include parameters (known equivalent to parameter slots)
4100    and cse'd or loop-moved constant memory addresses.
4101 
4102    Record constant equivalents in reg_equiv_constant
4103    so they will be substituted by find_reloads.
4104    Record memory equivalents in reg_mem_equiv so they can
4105    be substituted eventually by altering the REG-rtx's.  */
4106 
4107 static void
init_eliminable_invariants(rtx first,bool do_subregs)4108 init_eliminable_invariants (rtx first, bool do_subregs)
4109 {
4110   int i;
4111   rtx insn;
4112 
4113   grow_reg_equivs ();
4114   if (do_subregs)
4115     reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
4116   else
4117     reg_max_ref_width = NULL;
4118 
4119   num_eliminable_invariants = 0;
4120 
4121   first_label_num = get_first_label_num ();
4122   num_labels = max_label_num () - first_label_num;
4123 
4124   /* Allocate the tables used to store offset information at labels.  */
4125   offsets_known_at = XNEWVEC (char, num_labels);
4126   offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
4127 
4128 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4129    to.  If DO_SUBREGS is true, also find all paradoxical subregs and
4130    find largest such for each pseudo.  FIRST is the head of the insn
4131    list.  */
4132 
4133   for (insn = first; insn; insn = NEXT_INSN (insn))
4134     {
4135       rtx set = single_set (insn);
4136 
4137       /* We may introduce USEs that we want to remove at the end, so
4138 	 we'll mark them with QImode.  Make sure there are no
4139 	 previously-marked insns left by say regmove.  */
4140       if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
4141 	  && GET_MODE (insn) != VOIDmode)
4142 	PUT_MODE (insn, VOIDmode);
4143 
4144       if (do_subregs && NONDEBUG_INSN_P (insn))
4145 	scan_paradoxical_subregs (PATTERN (insn));
4146 
4147       if (set != 0 && REG_P (SET_DEST (set)))
4148 	{
4149 	  rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
4150 	  rtx x;
4151 
4152 	  if (! note)
4153 	    continue;
4154 
4155 	  i = REGNO (SET_DEST (set));
4156 	  x = XEXP (note, 0);
4157 
4158 	  if (i <= LAST_VIRTUAL_REGISTER)
4159 	    continue;
4160 
4161 	  /* If flag_pic and we have constant, verify it's legitimate.  */
4162 	  if (!CONSTANT_P (x)
4163 	      || !flag_pic || LEGITIMATE_PIC_OPERAND_P (x))
4164 	    {
4165 	      /* It can happen that a REG_EQUIV note contains a MEM
4166 		 that is not a legitimate memory operand.  As later
4167 		 stages of reload assume that all addresses found
4168 		 in the reg_equiv_* arrays were originally legitimate,
4169 		 we ignore such REG_EQUIV notes.  */
4170 	      if (memory_operand (x, VOIDmode))
4171 		{
4172 		  /* Always unshare the equivalence, so we can
4173 		     substitute into this insn without touching the
4174 		       equivalence.  */
4175 		  reg_equiv_memory_loc (i) = copy_rtx (x);
4176 		}
4177 	      else if (function_invariant_p (x))
4178 		{
4179 		  enum machine_mode mode;
4180 
4181 		  mode = GET_MODE (SET_DEST (set));
4182 		  if (GET_CODE (x) == PLUS)
4183 		    {
4184 		      /* This is PLUS of frame pointer and a constant,
4185 			 and might be shared.  Unshare it.  */
4186 		      reg_equiv_invariant (i) = copy_rtx (x);
4187 		      num_eliminable_invariants++;
4188 		    }
4189 		  else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4190 		    {
4191 		      reg_equiv_invariant (i) = x;
4192 		      num_eliminable_invariants++;
4193 		    }
4194 		  else if (targetm.legitimate_constant_p (mode, x))
4195 		    reg_equiv_constant (i) = x;
4196 		  else
4197 		    {
4198 		      reg_equiv_memory_loc (i) = force_const_mem (mode, x);
4199 		      if (! reg_equiv_memory_loc (i))
4200 			reg_equiv_init (i) = NULL_RTX;
4201 		    }
4202 		}
4203 	      else
4204 		{
4205 		  reg_equiv_init (i) = NULL_RTX;
4206 		  continue;
4207 		}
4208 	    }
4209 	  else
4210 	    reg_equiv_init (i) = NULL_RTX;
4211 	}
4212     }
4213 
4214   if (dump_file)
4215     for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4216       if (reg_equiv_init (i))
4217 	{
4218 	  fprintf (dump_file, "init_insns for %u: ", i);
4219 	  print_inline_rtx (dump_file, reg_equiv_init (i), 20);
4220 	  fprintf (dump_file, "\n");
4221 	}
4222 }
4223 
4224 /* Indicate that we no longer have known memory locations or constants.
4225    Free all data involved in tracking these.  */
4226 
4227 static void
free_reg_equiv(void)4228 free_reg_equiv (void)
4229 {
4230   int i;
4231 
4232 
4233   free (offsets_known_at);
4234   free (offsets_at);
4235   offsets_at = 0;
4236   offsets_known_at = 0;
4237 
4238   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4239     if (reg_equiv_alt_mem_list (i))
4240       free_EXPR_LIST_list (&reg_equiv_alt_mem_list (i));
4241   VEC_free (reg_equivs_t, gc, reg_equivs);
4242   reg_equivs = NULL;
4243 
4244 }
4245 
4246 /* Kick all pseudos out of hard register REGNO.
4247 
4248    If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4249    because we found we can't eliminate some register.  In the case, no pseudos
4250    are allowed to be in the register, even if they are only in a block that
4251    doesn't require spill registers, unlike the case when we are spilling this
4252    hard reg to produce another spill register.
4253 
4254    Return nonzero if any pseudos needed to be kicked out.  */
4255 
4256 static void
spill_hard_reg(unsigned int regno,int cant_eliminate)4257 spill_hard_reg (unsigned int regno, int cant_eliminate)
4258 {
4259   int i;
4260 
4261   if (cant_eliminate)
4262     {
4263       SET_HARD_REG_BIT (bad_spill_regs_global, regno);
4264       df_set_regs_ever_live (regno, true);
4265     }
4266 
4267   /* Spill every pseudo reg that was allocated to this reg
4268      or to something that overlaps this reg.  */
4269 
4270   for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4271     if (reg_renumber[i] >= 0
4272 	&& (unsigned int) reg_renumber[i] <= regno
4273 	&& end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
4274       SET_REGNO_REG_SET (&spilled_pseudos, i);
4275 }
4276 
4277 /* After find_reload_regs has been run for all insn that need reloads,
4278    and/or spill_hard_regs was called, this function is used to actually
4279    spill pseudo registers and try to reallocate them.  It also sets up the
4280    spill_regs array for use by choose_reload_regs.  */
4281 
4282 static int
finish_spills(int global)4283 finish_spills (int global)
4284 {
4285   struct insn_chain *chain;
4286   int something_changed = 0;
4287   unsigned i;
4288   reg_set_iterator rsi;
4289 
4290   /* Build the spill_regs array for the function.  */
4291   /* If there are some registers still to eliminate and one of the spill regs
4292      wasn't ever used before, additional stack space may have to be
4293      allocated to store this register.  Thus, we may have changed the offset
4294      between the stack and frame pointers, so mark that something has changed.
4295 
4296      One might think that we need only set VAL to 1 if this is a call-used
4297      register.  However, the set of registers that must be saved by the
4298      prologue is not identical to the call-used set.  For example, the
4299      register used by the call insn for the return PC is a call-used register,
4300      but must be saved by the prologue.  */
4301 
4302   n_spills = 0;
4303   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4304     if (TEST_HARD_REG_BIT (used_spill_regs, i))
4305       {
4306 	spill_reg_order[i] = n_spills;
4307 	spill_regs[n_spills++] = i;
4308 	if (num_eliminable && ! df_regs_ever_live_p (i))
4309 	  something_changed = 1;
4310 	df_set_regs_ever_live (i, true);
4311       }
4312     else
4313       spill_reg_order[i] = -1;
4314 
4315   EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
4316     if (! ira_conflicts_p || reg_renumber[i] >= 0)
4317       {
4318 	/* Record the current hard register the pseudo is allocated to
4319 	   in pseudo_previous_regs so we avoid reallocating it to the
4320 	   same hard reg in a later pass.  */
4321 	gcc_assert (reg_renumber[i] >= 0);
4322 
4323 	SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
4324 	/* Mark it as no longer having a hard register home.  */
4325 	reg_renumber[i] = -1;
4326 	if (ira_conflicts_p)
4327 	  /* Inform IRA about the change.  */
4328 	  ira_mark_allocation_change (i);
4329 	/* We will need to scan everything again.  */
4330 	something_changed = 1;
4331       }
4332 
4333   /* Retry global register allocation if possible.  */
4334   if (global && ira_conflicts_p)
4335     {
4336       unsigned int n;
4337 
4338       memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
4339       /* For every insn that needs reloads, set the registers used as spill
4340 	 regs in pseudo_forbidden_regs for every pseudo live across the
4341 	 insn.  */
4342       for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
4343 	{
4344 	  EXECUTE_IF_SET_IN_REG_SET
4345 	    (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
4346 	    {
4347 	      IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4348 				chain->used_spill_regs);
4349 	    }
4350 	  EXECUTE_IF_SET_IN_REG_SET
4351 	    (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
4352 	    {
4353 	      IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4354 				chain->used_spill_regs);
4355 	    }
4356 	}
4357 
4358       /* Retry allocating the pseudos spilled in IRA and the
4359 	 reload.  For each reg, merge the various reg sets that
4360 	 indicate which hard regs can't be used, and call
4361 	 ira_reassign_pseudos.  */
4362       for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
4363 	if (reg_old_renumber[i] != reg_renumber[i])
4364 	  {
4365 	    if (reg_renumber[i] < 0)
4366 	      temp_pseudo_reg_arr[n++] = i;
4367 	    else
4368 	      CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4369 	  }
4370       if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4371 				bad_spill_regs_global,
4372 				pseudo_forbidden_regs, pseudo_previous_regs,
4373 				&spilled_pseudos))
4374 	something_changed = 1;
4375     }
4376   /* Fix up the register information in the insn chain.
4377      This involves deleting those of the spilled pseudos which did not get
4378      a new hard register home from the live_{before,after} sets.  */
4379   for (chain = reload_insn_chain; chain; chain = chain->next)
4380     {
4381       HARD_REG_SET used_by_pseudos;
4382       HARD_REG_SET used_by_pseudos2;
4383 
4384       if (! ira_conflicts_p)
4385 	{
4386 	  /* Don't do it for IRA because IRA and the reload still can
4387 	     assign hard registers to the spilled pseudos on next
4388 	     reload iterations.  */
4389 	  AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4390 	  AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4391 	}
4392       /* Mark any unallocated hard regs as available for spills.  That
4393 	 makes inheritance work somewhat better.  */
4394       if (chain->need_reload)
4395 	{
4396 	  REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4397 	  REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4398 	  IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
4399 
4400 	  compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4401 	  compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4402 	  /* Value of chain->used_spill_regs from previous iteration
4403 	     may be not included in the value calculated here because
4404 	     of possible removing caller-saves insns (see function
4405 	     delete_caller_save_insns.  */
4406 	  COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4407 	  AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4408 	}
4409     }
4410 
4411   CLEAR_REG_SET (&changed_allocation_pseudos);
4412   /* Let alter_reg modify the reg rtx's for the modified pseudos.  */
4413   for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4414     {
4415       int regno = reg_renumber[i];
4416       if (reg_old_renumber[i] == regno)
4417 	continue;
4418 
4419       SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4420 
4421       alter_reg (i, reg_old_renumber[i], false);
4422       reg_old_renumber[i] = regno;
4423       if (dump_file)
4424 	{
4425 	  if (regno == -1)
4426 	    fprintf (dump_file, " Register %d now on stack.\n\n", i);
4427 	  else
4428 	    fprintf (dump_file, " Register %d now in %d.\n\n",
4429 		     i, reg_renumber[i]);
4430 	}
4431     }
4432 
4433   return something_changed;
4434 }
4435 
4436 /* Find all paradoxical subregs within X and update reg_max_ref_width.  */
4437 
4438 static void
scan_paradoxical_subregs(rtx x)4439 scan_paradoxical_subregs (rtx x)
4440 {
4441   int i;
4442   const char *fmt;
4443   enum rtx_code code = GET_CODE (x);
4444 
4445   switch (code)
4446     {
4447     case REG:
4448     case CONST_INT:
4449     case CONST:
4450     case SYMBOL_REF:
4451     case LABEL_REF:
4452     case CONST_DOUBLE:
4453     case CONST_FIXED:
4454     case CONST_VECTOR: /* shouldn't happen, but just in case.  */
4455     case CC0:
4456     case PC:
4457     case USE:
4458     case CLOBBER:
4459       return;
4460 
4461     case SUBREG:
4462       if (REG_P (SUBREG_REG (x))
4463 	  && (GET_MODE_SIZE (GET_MODE (x))
4464 	      > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
4465 	{
4466 	  reg_max_ref_width[REGNO (SUBREG_REG (x))]
4467 	    = GET_MODE_SIZE (GET_MODE (x));
4468 	  mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
4469 	}
4470       return;
4471 
4472     default:
4473       break;
4474     }
4475 
4476   fmt = GET_RTX_FORMAT (code);
4477   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4478     {
4479       if (fmt[i] == 'e')
4480 	scan_paradoxical_subregs (XEXP (x, i));
4481       else if (fmt[i] == 'E')
4482 	{
4483 	  int j;
4484 	  for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4485 	    scan_paradoxical_subregs (XVECEXP (x, i, j));
4486 	}
4487     }
4488 }
4489 
4490 /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4491    If *OP_PTR is a paradoxical subreg, try to remove that subreg
4492    and apply the corresponding narrowing subreg to *OTHER_PTR.
4493    Return true if the operands were changed, false otherwise.  */
4494 
4495 static bool
strip_paradoxical_subreg(rtx * op_ptr,rtx * other_ptr)4496 strip_paradoxical_subreg (rtx *op_ptr, rtx *other_ptr)
4497 {
4498   rtx op, inner, other, tem;
4499 
4500   op = *op_ptr;
4501   if (!paradoxical_subreg_p (op))
4502     return false;
4503   inner = SUBREG_REG (op);
4504 
4505   other = *other_ptr;
4506   tem = gen_lowpart_common (GET_MODE (inner), other);
4507   if (!tem)
4508     return false;
4509 
4510   /* If the lowpart operation turned a hard register into a subreg,
4511      rather than simplifying it to another hard register, then the
4512      mode change cannot be properly represented.  For example, OTHER
4513      might be valid in its current mode, but not in the new one.  */
4514   if (GET_CODE (tem) == SUBREG
4515       && REG_P (other)
4516       && HARD_REGISTER_P (other))
4517     return false;
4518 
4519   *op_ptr = inner;
4520   *other_ptr = tem;
4521   return true;
4522 }
4523 
4524 /* A subroutine of reload_as_needed.  If INSN has a REG_EH_REGION note,
4525    examine all of the reload insns between PREV and NEXT exclusive, and
4526    annotate all that may trap.  */
4527 
4528 static void
fixup_eh_region_note(rtx insn,rtx prev,rtx next)4529 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
4530 {
4531   rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4532   if (note == NULL)
4533     return;
4534   if (!insn_could_throw_p (insn))
4535     remove_note (insn, note);
4536   copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next);
4537 }
4538 
4539 /* Reload pseudo-registers into hard regs around each insn as needed.
4540    Additional register load insns are output before the insn that needs it
4541    and perhaps store insns after insns that modify the reloaded pseudo reg.
4542 
4543    reg_last_reload_reg and reg_reloaded_contents keep track of
4544    which registers are already available in reload registers.
4545    We update these for the reloads that we perform,
4546    as the insns are scanned.  */
4547 
4548 static void
reload_as_needed(int live_known)4549 reload_as_needed (int live_known)
4550 {
4551   struct insn_chain *chain;
4552 #if defined (AUTO_INC_DEC)
4553   int i;
4554 #endif
4555   rtx x, marker;
4556 
4557   memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4558   memset (spill_reg_store, 0, sizeof spill_reg_store);
4559   reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4560   INIT_REG_SET (&reg_has_output_reload);
4561   CLEAR_HARD_REG_SET (reg_reloaded_valid);
4562   CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4563 
4564   set_initial_elim_offsets ();
4565 
4566   /* Generate a marker insn that we will move around.  */
4567   marker = emit_note (NOTE_INSN_DELETED);
4568   unlink_insn_chain (marker, marker);
4569 
4570   for (chain = reload_insn_chain; chain; chain = chain->next)
4571     {
4572       rtx prev = 0;
4573       rtx insn = chain->insn;
4574       rtx old_next = NEXT_INSN (insn);
4575 #ifdef AUTO_INC_DEC
4576       rtx old_prev = PREV_INSN (insn);
4577 #endif
4578 
4579       /* If we pass a label, copy the offsets from the label information
4580 	 into the current offsets of each elimination.  */
4581       if (LABEL_P (insn))
4582 	set_offsets_for_label (insn);
4583 
4584       else if (INSN_P (insn))
4585 	{
4586 	  regset_head regs_to_forget;
4587 	  INIT_REG_SET (&regs_to_forget);
4588 	  note_stores (PATTERN (insn), forget_old_reloads_1, &regs_to_forget);
4589 
4590 	  /* If this is a USE and CLOBBER of a MEM, ensure that any
4591 	     references to eliminable registers have been removed.  */
4592 
4593 	  if ((GET_CODE (PATTERN (insn)) == USE
4594 	       || GET_CODE (PATTERN (insn)) == CLOBBER)
4595 	      && MEM_P (XEXP (PATTERN (insn), 0)))
4596 	    XEXP (XEXP (PATTERN (insn), 0), 0)
4597 	      = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4598 				GET_MODE (XEXP (PATTERN (insn), 0)),
4599 				NULL_RTX);
4600 
4601 	  /* If we need to do register elimination processing, do so.
4602 	     This might delete the insn, in which case we are done.  */
4603 	  if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4604 	    {
4605 	      eliminate_regs_in_insn (insn, 1);
4606 	      if (NOTE_P (insn))
4607 		{
4608 		  update_eliminable_offsets ();
4609 		  CLEAR_REG_SET (&regs_to_forget);
4610 		  continue;
4611 		}
4612 	    }
4613 
4614 	  /* If need_elim is nonzero but need_reload is zero, one might think
4615 	     that we could simply set n_reloads to 0.  However, find_reloads
4616 	     could have done some manipulation of the insn (such as swapping
4617 	     commutative operands), and these manipulations are lost during
4618 	     the first pass for every insn that needs register elimination.
4619 	     So the actions of find_reloads must be redone here.  */
4620 
4621 	  if (! chain->need_elim && ! chain->need_reload
4622 	      && ! chain->need_operand_change)
4623 	    n_reloads = 0;
4624 	  /* First find the pseudo regs that must be reloaded for this insn.
4625 	     This info is returned in the tables reload_... (see reload.h).
4626 	     Also modify the body of INSN by substituting RELOAD
4627 	     rtx's for those pseudo regs.  */
4628 	  else
4629 	    {
4630 	      CLEAR_REG_SET (&reg_has_output_reload);
4631 	      CLEAR_HARD_REG_SET (reg_is_output_reload);
4632 
4633 	      find_reloads (insn, 1, spill_indirect_levels, live_known,
4634 			    spill_reg_order);
4635 	    }
4636 
4637 	  if (n_reloads > 0)
4638 	    {
4639 	      rtx next = NEXT_INSN (insn);
4640 	      rtx p;
4641 
4642 	      /* ??? PREV can get deleted by reload inheritance.
4643 		 Work around this by emitting a marker note.  */
4644 	      prev = PREV_INSN (insn);
4645 	      reorder_insns_nobb (marker, marker, prev);
4646 
4647 	      /* Now compute which reload regs to reload them into.  Perhaps
4648 		 reusing reload regs from previous insns, or else output
4649 		 load insns to reload them.  Maybe output store insns too.
4650 		 Record the choices of reload reg in reload_reg_rtx.  */
4651 	      choose_reload_regs (chain);
4652 
4653 	      /* Generate the insns to reload operands into or out of
4654 		 their reload regs.  */
4655 	      emit_reload_insns (chain);
4656 
4657 	      /* Substitute the chosen reload regs from reload_reg_rtx
4658 		 into the insn's body (or perhaps into the bodies of other
4659 		 load and store insn that we just made for reloading
4660 		 and that we moved the structure into).  */
4661 	      subst_reloads (insn);
4662 
4663 	      prev = PREV_INSN (marker);
4664 	      unlink_insn_chain (marker, marker);
4665 
4666 	      /* Adjust the exception region notes for loads and stores.  */
4667 	      if (cfun->can_throw_non_call_exceptions && !CALL_P (insn))
4668 		fixup_eh_region_note (insn, prev, next);
4669 
4670 	      /* Adjust the location of REG_ARGS_SIZE.  */
4671 	      p = find_reg_note (insn, REG_ARGS_SIZE, NULL_RTX);
4672 	      if (p)
4673 		{
4674 		  remove_note (insn, p);
4675 		  fixup_args_size_notes (prev, PREV_INSN (next),
4676 					 INTVAL (XEXP (p, 0)));
4677 		}
4678 
4679 	      /* If this was an ASM, make sure that all the reload insns
4680 		 we have generated are valid.  If not, give an error
4681 		 and delete them.  */
4682 	      if (asm_noperands (PATTERN (insn)) >= 0)
4683 		for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4684 		  if (p != insn && INSN_P (p)
4685 		      && GET_CODE (PATTERN (p)) != USE
4686 		      && (recog_memoized (p) < 0
4687 			  || (extract_insn (p), ! constrain_operands (1))))
4688 		    {
4689 		      error_for_asm (insn,
4690 				     "%<asm%> operand requires "
4691 				     "impossible reload");
4692 		      delete_insn (p);
4693 		    }
4694 	    }
4695 
4696 	  if (num_eliminable && chain->need_elim)
4697 	    update_eliminable_offsets ();
4698 
4699 	  /* Any previously reloaded spilled pseudo reg, stored in this insn,
4700 	     is no longer validly lying around to save a future reload.
4701 	     Note that this does not detect pseudos that were reloaded
4702 	     for this insn in order to be stored in
4703 	     (obeying register constraints).  That is correct; such reload
4704 	     registers ARE still valid.  */
4705 	  forget_marked_reloads (&regs_to_forget);
4706 	  CLEAR_REG_SET (&regs_to_forget);
4707 
4708 	  /* There may have been CLOBBER insns placed after INSN.  So scan
4709 	     between INSN and NEXT and use them to forget old reloads.  */
4710 	  for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4711 	    if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4712 	      note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4713 
4714 #ifdef AUTO_INC_DEC
4715 	  /* Likewise for regs altered by auto-increment in this insn.
4716 	     REG_INC notes have been changed by reloading:
4717 	     find_reloads_address_1 records substitutions for them,
4718 	     which have been performed by subst_reloads above.  */
4719 	  for (i = n_reloads - 1; i >= 0; i--)
4720 	    {
4721 	      rtx in_reg = rld[i].in_reg;
4722 	      if (in_reg)
4723 		{
4724 		  enum rtx_code code = GET_CODE (in_reg);
4725 		  /* PRE_INC / PRE_DEC will have the reload register ending up
4726 		     with the same value as the stack slot, but that doesn't
4727 		     hold true for POST_INC / POST_DEC.  Either we have to
4728 		     convert the memory access to a true POST_INC / POST_DEC,
4729 		     or we can't use the reload register for inheritance.  */
4730 		  if ((code == POST_INC || code == POST_DEC)
4731 		      && TEST_HARD_REG_BIT (reg_reloaded_valid,
4732 					    REGNO (rld[i].reg_rtx))
4733 		      /* Make sure it is the inc/dec pseudo, and not
4734 			 some other (e.g. output operand) pseudo.  */
4735 		      && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4736 			  == REGNO (XEXP (in_reg, 0))))
4737 
4738 		    {
4739 		      rtx reload_reg = rld[i].reg_rtx;
4740 		      enum machine_mode mode = GET_MODE (reload_reg);
4741 		      int n = 0;
4742 		      rtx p;
4743 
4744 		      for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4745 			{
4746 			  /* We really want to ignore REG_INC notes here, so
4747 			     use PATTERN (p) as argument to reg_set_p .  */
4748 			  if (reg_set_p (reload_reg, PATTERN (p)))
4749 			    break;
4750 			  n = count_occurrences (PATTERN (p), reload_reg, 0);
4751 			  if (! n)
4752 			    continue;
4753 			  if (n == 1)
4754 			    {
4755 			      rtx replace_reg
4756 				= gen_rtx_fmt_e (code, mode, reload_reg);
4757 
4758 			      validate_replace_rtx_group (reload_reg,
4759 							  replace_reg, p);
4760 			      n = verify_changes (0);
4761 
4762 			      /* We must also verify that the constraints
4763 				 are met after the replacement.  Make sure
4764 				 extract_insn is only called for an insn
4765 				 where the replacements were found to be
4766 				 valid so far. */
4767 			      if (n)
4768 				{
4769 				  extract_insn (p);
4770 				  n = constrain_operands (1);
4771 				}
4772 
4773 			      /* If the constraints were not met, then
4774 				 undo the replacement, else confirm it.  */
4775 			      if (!n)
4776 				cancel_changes (0);
4777 			      else
4778 				confirm_change_group ();
4779 			    }
4780 			  break;
4781 			}
4782 		      if (n == 1)
4783 			{
4784 			  add_reg_note (p, REG_INC, reload_reg);
4785 			  /* Mark this as having an output reload so that the
4786 			     REG_INC processing code below won't invalidate
4787 			     the reload for inheritance.  */
4788 			  SET_HARD_REG_BIT (reg_is_output_reload,
4789 					    REGNO (reload_reg));
4790 			  SET_REGNO_REG_SET (&reg_has_output_reload,
4791 					     REGNO (XEXP (in_reg, 0)));
4792 			}
4793 		      else
4794 			forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4795 					      NULL);
4796 		    }
4797 		  else if ((code == PRE_INC || code == PRE_DEC)
4798 			   && TEST_HARD_REG_BIT (reg_reloaded_valid,
4799 						 REGNO (rld[i].reg_rtx))
4800 			   /* Make sure it is the inc/dec pseudo, and not
4801 			      some other (e.g. output operand) pseudo.  */
4802 			   && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4803 			       == REGNO (XEXP (in_reg, 0))))
4804 		    {
4805 		      SET_HARD_REG_BIT (reg_is_output_reload,
4806 					REGNO (rld[i].reg_rtx));
4807 		      SET_REGNO_REG_SET (&reg_has_output_reload,
4808 					 REGNO (XEXP (in_reg, 0)));
4809 		    }
4810 		  else if (code == PRE_INC || code == PRE_DEC
4811 			   || code == POST_INC || code == POST_DEC)
4812 		    {
4813 		      int in_regno = REGNO (XEXP (in_reg, 0));
4814 
4815 		      if (reg_last_reload_reg[in_regno] != NULL_RTX)
4816 			{
4817 			  int in_hard_regno;
4818 			  bool forget_p = true;
4819 
4820 			  in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4821 			  if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4822 						 in_hard_regno))
4823 			    {
4824 			      for (x = old_prev ? NEXT_INSN (old_prev) : insn;
4825 				   x != old_next;
4826 				   x = NEXT_INSN (x))
4827 				if (x == reg_reloaded_insn[in_hard_regno])
4828 				  {
4829 				    forget_p = false;
4830 				    break;
4831 				  }
4832 			    }
4833 			  /* If for some reasons, we didn't set up
4834 			     reg_last_reload_reg in this insn,
4835 			     invalidate inheritance from previous
4836 			     insns for the incremented/decremented
4837 			     register.  Such registers will be not in
4838 			     reg_has_output_reload.  Invalidate it
4839 			     also if the corresponding element in
4840 			     reg_reloaded_insn is also
4841 			     invalidated.  */
4842 			  if (forget_p)
4843 			    forget_old_reloads_1 (XEXP (in_reg, 0),
4844 						  NULL_RTX, NULL);
4845 			}
4846 		    }
4847 		}
4848 	    }
4849 	  /* If a pseudo that got a hard register is auto-incremented,
4850 	     we must purge records of copying it into pseudos without
4851 	     hard registers.  */
4852 	  for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4853 	    if (REG_NOTE_KIND (x) == REG_INC)
4854 	      {
4855 		/* See if this pseudo reg was reloaded in this insn.
4856 		   If so, its last-reload info is still valid
4857 		   because it is based on this insn's reload.  */
4858 		for (i = 0; i < n_reloads; i++)
4859 		  if (rld[i].out == XEXP (x, 0))
4860 		    break;
4861 
4862 		if (i == n_reloads)
4863 		  forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4864 	      }
4865 #endif
4866 	}
4867       /* A reload reg's contents are unknown after a label.  */
4868       if (LABEL_P (insn))
4869 	CLEAR_HARD_REG_SET (reg_reloaded_valid);
4870 
4871       /* Don't assume a reload reg is still good after a call insn
4872 	 if it is a call-used reg, or if it contains a value that will
4873          be partially clobbered by the call.  */
4874       else if (CALL_P (insn))
4875 	{
4876 	  AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4877 	  AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4878 
4879 	  /* If this is a call to a setjmp-type function, we must not
4880 	     reuse any reload reg contents across the call; that will
4881 	     just be clobbered by other uses of the register in later
4882 	     code, before the longjmp.  */
4883 	  if (find_reg_note (insn, REG_SETJMP, NULL_RTX))
4884 	    CLEAR_HARD_REG_SET (reg_reloaded_valid);
4885 	}
4886     }
4887 
4888   /* Clean up.  */
4889   free (reg_last_reload_reg);
4890   CLEAR_REG_SET (&reg_has_output_reload);
4891 }
4892 
4893 /* Discard all record of any value reloaded from X,
4894    or reloaded in X from someplace else;
4895    unless X is an output reload reg of the current insn.
4896 
4897    X may be a hard reg (the reload reg)
4898    or it may be a pseudo reg that was reloaded from.
4899 
4900    When DATA is non-NULL just mark the registers in regset
4901    to be forgotten later.  */
4902 
4903 static void
forget_old_reloads_1(rtx x,const_rtx ignored ATTRIBUTE_UNUSED,void * data)4904 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4905 		      void *data)
4906 {
4907   unsigned int regno;
4908   unsigned int nr;
4909   regset regs = (regset) data;
4910 
4911   /* note_stores does give us subregs of hard regs,
4912      subreg_regno_offset requires a hard reg.  */
4913   while (GET_CODE (x) == SUBREG)
4914     {
4915       /* We ignore the subreg offset when calculating the regno,
4916 	 because we are using the entire underlying hard register
4917 	 below.  */
4918       x = SUBREG_REG (x);
4919     }
4920 
4921   if (!REG_P (x))
4922     return;
4923 
4924   regno = REGNO (x);
4925 
4926   if (regno >= FIRST_PSEUDO_REGISTER)
4927     nr = 1;
4928   else
4929     {
4930       unsigned int i;
4931 
4932       nr = hard_regno_nregs[regno][GET_MODE (x)];
4933       /* Storing into a spilled-reg invalidates its contents.
4934 	 This can happen if a block-local pseudo is allocated to that reg
4935 	 and it wasn't spilled because this block's total need is 0.
4936 	 Then some insn might have an optional reload and use this reg.  */
4937       if (!regs)
4938 	for (i = 0; i < nr; i++)
4939 	  /* But don't do this if the reg actually serves as an output
4940 	     reload reg in the current instruction.  */
4941 	  if (n_reloads == 0
4942 	      || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4943 	    {
4944 	      CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4945 	      spill_reg_store[regno + i] = 0;
4946 	    }
4947     }
4948 
4949   if (regs)
4950     while (nr-- > 0)
4951       SET_REGNO_REG_SET (regs, regno + nr);
4952   else
4953     {
4954       /* Since value of X has changed,
4955 	 forget any value previously copied from it.  */
4956 
4957       while (nr-- > 0)
4958 	/* But don't forget a copy if this is the output reload
4959 	   that establishes the copy's validity.  */
4960 	if (n_reloads == 0
4961 	    || !REGNO_REG_SET_P (&reg_has_output_reload, regno + nr))
4962 	  reg_last_reload_reg[regno + nr] = 0;
4963      }
4964 }
4965 
4966 /* Forget the reloads marked in regset by previous function.  */
4967 static void
forget_marked_reloads(regset regs)4968 forget_marked_reloads (regset regs)
4969 {
4970   unsigned int reg;
4971   reg_set_iterator rsi;
4972   EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4973     {
4974       if (reg < FIRST_PSEUDO_REGISTER
4975 	  /* But don't do this if the reg actually serves as an output
4976 	     reload reg in the current instruction.  */
4977 	  && (n_reloads == 0
4978 	      || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4979 	  {
4980 	    CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4981 	    spill_reg_store[reg] = 0;
4982 	  }
4983       if (n_reloads == 0
4984 	  || !REGNO_REG_SET_P (&reg_has_output_reload, reg))
4985 	reg_last_reload_reg[reg] = 0;
4986     }
4987 }
4988 
4989 /* The following HARD_REG_SETs indicate when each hard register is
4990    used for a reload of various parts of the current insn.  */
4991 
4992 /* If reg is unavailable for all reloads.  */
4993 static HARD_REG_SET reload_reg_unavailable;
4994 /* If reg is in use as a reload reg for a RELOAD_OTHER reload.  */
4995 static HARD_REG_SET reload_reg_used;
4996 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I.  */
4997 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4998 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I.  */
4999 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
5000 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I.  */
5001 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
5002 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I.  */
5003 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
5004 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I.  */
5005 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
5006 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I.  */
5007 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
5008 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload.  */
5009 static HARD_REG_SET reload_reg_used_in_op_addr;
5010 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload.  */
5011 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
5012 /* If reg is in use for a RELOAD_FOR_INSN reload.  */
5013 static HARD_REG_SET reload_reg_used_in_insn;
5014 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload.  */
5015 static HARD_REG_SET reload_reg_used_in_other_addr;
5016 
5017 /* If reg is in use as a reload reg for any sort of reload.  */
5018 static HARD_REG_SET reload_reg_used_at_all;
5019 
5020 /* If reg is use as an inherited reload.  We just mark the first register
5021    in the group.  */
5022 static HARD_REG_SET reload_reg_used_for_inherit;
5023 
5024 /* Records which hard regs are used in any way, either as explicit use or
5025    by being allocated to a pseudo during any point of the current insn.  */
5026 static HARD_REG_SET reg_used_in_insn;
5027 
5028 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
5029    TYPE. MODE is used to indicate how many consecutive regs are
5030    actually used.  */
5031 
5032 static void
mark_reload_reg_in_use(unsigned int regno,int opnum,enum reload_type type,enum machine_mode mode)5033 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
5034 			enum machine_mode mode)
5035 {
5036   switch (type)
5037     {
5038     case RELOAD_OTHER:
5039       add_to_hard_reg_set (&reload_reg_used, mode, regno);
5040       break;
5041 
5042     case RELOAD_FOR_INPUT_ADDRESS:
5043       add_to_hard_reg_set (&reload_reg_used_in_input_addr[opnum], mode, regno);
5044       break;
5045 
5046     case RELOAD_FOR_INPADDR_ADDRESS:
5047       add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr[opnum], mode, regno);
5048       break;
5049 
5050     case RELOAD_FOR_OUTPUT_ADDRESS:
5051       add_to_hard_reg_set (&reload_reg_used_in_output_addr[opnum], mode, regno);
5052       break;
5053 
5054     case RELOAD_FOR_OUTADDR_ADDRESS:
5055       add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr[opnum], mode, regno);
5056       break;
5057 
5058     case RELOAD_FOR_OPERAND_ADDRESS:
5059       add_to_hard_reg_set (&reload_reg_used_in_op_addr, mode, regno);
5060       break;
5061 
5062     case RELOAD_FOR_OPADDR_ADDR:
5063       add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload, mode, regno);
5064       break;
5065 
5066     case RELOAD_FOR_OTHER_ADDRESS:
5067       add_to_hard_reg_set (&reload_reg_used_in_other_addr, mode, regno);
5068       break;
5069 
5070     case RELOAD_FOR_INPUT:
5071       add_to_hard_reg_set (&reload_reg_used_in_input[opnum], mode, regno);
5072       break;
5073 
5074     case RELOAD_FOR_OUTPUT:
5075       add_to_hard_reg_set (&reload_reg_used_in_output[opnum], mode, regno);
5076       break;
5077 
5078     case RELOAD_FOR_INSN:
5079       add_to_hard_reg_set (&reload_reg_used_in_insn,  mode, regno);
5080       break;
5081     }
5082 
5083   add_to_hard_reg_set (&reload_reg_used_at_all, mode, regno);
5084 }
5085 
5086 /* Similarly, but show REGNO is no longer in use for a reload.  */
5087 
5088 static void
clear_reload_reg_in_use(unsigned int regno,int opnum,enum reload_type type,enum machine_mode mode)5089 clear_reload_reg_in_use (unsigned int regno, int opnum,
5090 			 enum reload_type type, enum machine_mode mode)
5091 {
5092   unsigned int nregs = hard_regno_nregs[regno][mode];
5093   unsigned int start_regno, end_regno, r;
5094   int i;
5095   /* A complication is that for some reload types, inheritance might
5096      allow multiple reloads of the same types to share a reload register.
5097      We set check_opnum if we have to check only reloads with the same
5098      operand number, and check_any if we have to check all reloads.  */
5099   int check_opnum = 0;
5100   int check_any = 0;
5101   HARD_REG_SET *used_in_set;
5102 
5103   switch (type)
5104     {
5105     case RELOAD_OTHER:
5106       used_in_set = &reload_reg_used;
5107       break;
5108 
5109     case RELOAD_FOR_INPUT_ADDRESS:
5110       used_in_set = &reload_reg_used_in_input_addr[opnum];
5111       break;
5112 
5113     case RELOAD_FOR_INPADDR_ADDRESS:
5114       check_opnum = 1;
5115       used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
5116       break;
5117 
5118     case RELOAD_FOR_OUTPUT_ADDRESS:
5119       used_in_set = &reload_reg_used_in_output_addr[opnum];
5120       break;
5121 
5122     case RELOAD_FOR_OUTADDR_ADDRESS:
5123       check_opnum = 1;
5124       used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
5125       break;
5126 
5127     case RELOAD_FOR_OPERAND_ADDRESS:
5128       used_in_set = &reload_reg_used_in_op_addr;
5129       break;
5130 
5131     case RELOAD_FOR_OPADDR_ADDR:
5132       check_any = 1;
5133       used_in_set = &reload_reg_used_in_op_addr_reload;
5134       break;
5135 
5136     case RELOAD_FOR_OTHER_ADDRESS:
5137       used_in_set = &reload_reg_used_in_other_addr;
5138       check_any = 1;
5139       break;
5140 
5141     case RELOAD_FOR_INPUT:
5142       used_in_set = &reload_reg_used_in_input[opnum];
5143       break;
5144 
5145     case RELOAD_FOR_OUTPUT:
5146       used_in_set = &reload_reg_used_in_output[opnum];
5147       break;
5148 
5149     case RELOAD_FOR_INSN:
5150       used_in_set = &reload_reg_used_in_insn;
5151       break;
5152     default:
5153       gcc_unreachable ();
5154     }
5155   /* We resolve conflicts with remaining reloads of the same type by
5156      excluding the intervals of reload registers by them from the
5157      interval of freed reload registers.  Since we only keep track of
5158      one set of interval bounds, we might have to exclude somewhat
5159      more than what would be necessary if we used a HARD_REG_SET here.
5160      But this should only happen very infrequently, so there should
5161      be no reason to worry about it.  */
5162 
5163   start_regno = regno;
5164   end_regno = regno + nregs;
5165   if (check_opnum || check_any)
5166     {
5167       for (i = n_reloads - 1; i >= 0; i--)
5168 	{
5169 	  if (rld[i].when_needed == type
5170 	      && (check_any || rld[i].opnum == opnum)
5171 	      && rld[i].reg_rtx)
5172 	    {
5173 	      unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
5174 	      unsigned int conflict_end
5175 		= end_hard_regno (rld[i].mode, conflict_start);
5176 
5177 	      /* If there is an overlap with the first to-be-freed register,
5178 		 adjust the interval start.  */
5179 	      if (conflict_start <= start_regno && conflict_end > start_regno)
5180 		start_regno = conflict_end;
5181 	      /* Otherwise, if there is a conflict with one of the other
5182 		 to-be-freed registers, adjust the interval end.  */
5183 	      if (conflict_start > start_regno && conflict_start < end_regno)
5184 		end_regno = conflict_start;
5185 	    }
5186 	}
5187     }
5188 
5189   for (r = start_regno; r < end_regno; r++)
5190     CLEAR_HARD_REG_BIT (*used_in_set, r);
5191 }
5192 
5193 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5194    specified by OPNUM and TYPE.  */
5195 
5196 static int
reload_reg_free_p(unsigned int regno,int opnum,enum reload_type type)5197 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
5198 {
5199   int i;
5200 
5201   /* In use for a RELOAD_OTHER means it's not available for anything.  */
5202   if (TEST_HARD_REG_BIT (reload_reg_used, regno)
5203       || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5204     return 0;
5205 
5206   switch (type)
5207     {
5208     case RELOAD_OTHER:
5209       /* In use for anything means we can't use it for RELOAD_OTHER.  */
5210       if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
5211 	  || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5212 	  || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5213 	  || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5214 	return 0;
5215 
5216       for (i = 0; i < reload_n_operands; i++)
5217 	if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5218 	    || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5219 	    || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5220 	    || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5221 	    || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5222 	    || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5223 	  return 0;
5224 
5225       return 1;
5226 
5227     case RELOAD_FOR_INPUT:
5228       if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5229 	  || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
5230 	return 0;
5231 
5232       if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5233 	return 0;
5234 
5235       /* If it is used for some other input, can't use it.  */
5236       for (i = 0; i < reload_n_operands; i++)
5237 	if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5238 	  return 0;
5239 
5240       /* If it is used in a later operand's address, can't use it.  */
5241       for (i = opnum + 1; i < reload_n_operands; i++)
5242 	if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5243 	    || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5244 	  return 0;
5245 
5246       return 1;
5247 
5248     case RELOAD_FOR_INPUT_ADDRESS:
5249       /* Can't use a register if it is used for an input address for this
5250 	 operand or used as an input in an earlier one.  */
5251       if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
5252 	  || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5253 	return 0;
5254 
5255       for (i = 0; i < opnum; i++)
5256 	if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5257 	  return 0;
5258 
5259       return 1;
5260 
5261     case RELOAD_FOR_INPADDR_ADDRESS:
5262       /* Can't use a register if it is used for an input address
5263 	 for this operand or used as an input in an earlier
5264 	 one.  */
5265       if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5266 	return 0;
5267 
5268       for (i = 0; i < opnum; i++)
5269 	if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5270 	  return 0;
5271 
5272       return 1;
5273 
5274     case RELOAD_FOR_OUTPUT_ADDRESS:
5275       /* Can't use a register if it is used for an output address for this
5276 	 operand or used as an output in this or a later operand.  Note
5277 	 that multiple output operands are emitted in reverse order, so
5278 	 the conflicting ones are those with lower indices.  */
5279       if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
5280 	return 0;
5281 
5282       for (i = 0; i <= opnum; i++)
5283 	if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5284 	  return 0;
5285 
5286       return 1;
5287 
5288     case RELOAD_FOR_OUTADDR_ADDRESS:
5289       /* Can't use a register if it is used for an output address
5290 	 for this operand or used as an output in this or a
5291 	 later operand.  Note that multiple output operands are
5292 	 emitted in reverse order, so the conflicting ones are
5293 	 those with lower indices.  */
5294       if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5295 	return 0;
5296 
5297       for (i = 0; i <= opnum; i++)
5298 	if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5299 	  return 0;
5300 
5301       return 1;
5302 
5303     case RELOAD_FOR_OPERAND_ADDRESS:
5304       for (i = 0; i < reload_n_operands; i++)
5305 	if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5306 	  return 0;
5307 
5308       return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5309 	      && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5310 
5311     case RELOAD_FOR_OPADDR_ADDR:
5312       for (i = 0; i < reload_n_operands; i++)
5313 	if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5314 	  return 0;
5315 
5316       return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
5317 
5318     case RELOAD_FOR_OUTPUT:
5319       /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5320 	 outputs, or an operand address for this or an earlier output.
5321 	 Note that multiple output operands are emitted in reverse order,
5322 	 so the conflicting ones are those with higher indices.  */
5323       if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5324 	return 0;
5325 
5326       for (i = 0; i < reload_n_operands; i++)
5327 	if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5328 	  return 0;
5329 
5330       for (i = opnum; i < reload_n_operands; i++)
5331 	if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5332 	    || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5333 	  return 0;
5334 
5335       return 1;
5336 
5337     case RELOAD_FOR_INSN:
5338       for (i = 0; i < reload_n_operands; i++)
5339 	if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5340 	    || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5341 	  return 0;
5342 
5343       return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5344 	      && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5345 
5346     case RELOAD_FOR_OTHER_ADDRESS:
5347       return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
5348 
5349     default:
5350       gcc_unreachable ();
5351     }
5352 }
5353 
5354 /* Return 1 if the value in reload reg REGNO, as used by the reload with
5355    the number RELOADNUM, is still available in REGNO at the end of the insn.
5356 
5357    We can assume that the reload reg was already tested for availability
5358    at the time it is needed, and we should not check this again,
5359    in case the reg has already been marked in use.  */
5360 
5361 static int
reload_reg_reaches_end_p(unsigned int regno,int reloadnum)5362 reload_reg_reaches_end_p (unsigned int regno, int reloadnum)
5363 {
5364   int opnum = rld[reloadnum].opnum;
5365   enum reload_type type = rld[reloadnum].when_needed;
5366   int i;
5367 
5368   /* See if there is a reload with the same type for this operand, using
5369      the same register. This case is not handled by the code below.  */
5370   for (i = reloadnum + 1; i < n_reloads; i++)
5371     {
5372       rtx reg;
5373       int nregs;
5374 
5375       if (rld[i].opnum != opnum || rld[i].when_needed != type)
5376 	continue;
5377       reg = rld[i].reg_rtx;
5378       if (reg == NULL_RTX)
5379 	continue;
5380       nregs = hard_regno_nregs[REGNO (reg)][GET_MODE (reg)];
5381       if (regno >= REGNO (reg) && regno < REGNO (reg) + nregs)
5382 	return 0;
5383     }
5384 
5385   switch (type)
5386     {
5387     case RELOAD_OTHER:
5388       /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5389 	 its value must reach the end.  */
5390       return 1;
5391 
5392       /* If this use is for part of the insn,
5393 	 its value reaches if no subsequent part uses the same register.
5394 	 Just like the above function, don't try to do this with lots
5395 	 of fallthroughs.  */
5396 
5397     case RELOAD_FOR_OTHER_ADDRESS:
5398       /* Here we check for everything else, since these don't conflict
5399 	 with anything else and everything comes later.  */
5400 
5401       for (i = 0; i < reload_n_operands; i++)
5402 	if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5403 	    || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5404 	    || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
5405 	    || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5406 	    || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5407 	    || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5408 	  return 0;
5409 
5410       return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5411 	      && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5412 	      && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5413 	      && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5414 
5415     case RELOAD_FOR_INPUT_ADDRESS:
5416     case RELOAD_FOR_INPADDR_ADDRESS:
5417       /* Similar, except that we check only for this and subsequent inputs
5418 	 and the address of only subsequent inputs and we do not need
5419 	 to check for RELOAD_OTHER objects since they are known not to
5420 	 conflict.  */
5421 
5422       for (i = opnum; i < reload_n_operands; i++)
5423 	if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5424 	  return 0;
5425 
5426       /* Reload register of reload with type RELOAD_FOR_INPADDR_ADDRESS
5427 	 could be killed if the register is also used by reload with type
5428 	 RELOAD_FOR_INPUT_ADDRESS, so check it.  */
5429       if (type == RELOAD_FOR_INPADDR_ADDRESS
5430 	  && TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno))
5431 	return 0;
5432 
5433       for (i = opnum + 1; i < reload_n_operands; i++)
5434 	if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5435 	    || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5436 	  return 0;
5437 
5438       for (i = 0; i < reload_n_operands; i++)
5439 	if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5440 	    || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5441 	    || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5442 	  return 0;
5443 
5444       if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5445 	return 0;
5446 
5447       return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5448 	      && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5449 	      && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5450 
5451     case RELOAD_FOR_INPUT:
5452       /* Similar to input address, except we start at the next operand for
5453 	 both input and input address and we do not check for
5454 	 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5455 	 would conflict.  */
5456 
5457       for (i = opnum + 1; i < reload_n_operands; i++)
5458 	if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5459 	    || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5460 	    || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5461 	  return 0;
5462 
5463       /* ... fall through ...  */
5464 
5465     case RELOAD_FOR_OPERAND_ADDRESS:
5466       /* Check outputs and their addresses.  */
5467 
5468       for (i = 0; i < reload_n_operands; i++)
5469 	if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5470 	    || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5471 	    || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5472 	  return 0;
5473 
5474       return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5475 
5476     case RELOAD_FOR_OPADDR_ADDR:
5477       for (i = 0; i < reload_n_operands; i++)
5478 	if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5479 	    || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5480 	    || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5481 	  return 0;
5482 
5483       return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5484 	      && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5485 	      && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5486 
5487     case RELOAD_FOR_INSN:
5488       /* These conflict with other outputs with RELOAD_OTHER.  So
5489 	 we need only check for output addresses.  */
5490 
5491       opnum = reload_n_operands;
5492 
5493       /* ... fall through ...  */
5494 
5495     case RELOAD_FOR_OUTPUT:
5496     case RELOAD_FOR_OUTPUT_ADDRESS:
5497     case RELOAD_FOR_OUTADDR_ADDRESS:
5498       /* We already know these can't conflict with a later output.  So the
5499 	 only thing to check are later output addresses.
5500 	 Note that multiple output operands are emitted in reverse order,
5501 	 so the conflicting ones are those with lower indices.  */
5502       for (i = 0; i < opnum; i++)
5503 	if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5504 	    || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5505 	  return 0;
5506 
5507       /* Reload register of reload with type RELOAD_FOR_OUTADDR_ADDRESS
5508 	 could be killed if the register is also used by reload with type
5509 	 RELOAD_FOR_OUTPUT_ADDRESS, so check it.  */
5510       if (type == RELOAD_FOR_OUTADDR_ADDRESS
5511 	  && TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5512 	return 0;
5513 
5514       return 1;
5515 
5516     default:
5517       gcc_unreachable ();
5518     }
5519 }
5520 
5521 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5522    every register in REG.  */
5523 
5524 static bool
reload_reg_rtx_reaches_end_p(rtx reg,int reloadnum)5525 reload_reg_rtx_reaches_end_p (rtx reg, int reloadnum)
5526 {
5527   unsigned int i;
5528 
5529   for (i = REGNO (reg); i < END_REGNO (reg); i++)
5530     if (!reload_reg_reaches_end_p (i, reloadnum))
5531       return false;
5532   return true;
5533 }
5534 
5535 
5536 /*  Returns whether R1 and R2 are uniquely chained: the value of one
5537     is used by the other, and that value is not used by any other
5538     reload for this insn.  This is used to partially undo the decision
5539     made in find_reloads when in the case of multiple
5540     RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5541     RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5542     reloads.  This code tries to avoid the conflict created by that
5543     change.  It might be cleaner to explicitly keep track of which
5544     RELOAD_FOR_OPADDR_ADDR reload is associated with which
5545     RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5546     this after the fact. */
5547 static bool
reloads_unique_chain_p(int r1,int r2)5548 reloads_unique_chain_p (int r1, int r2)
5549 {
5550   int i;
5551 
5552   /* We only check input reloads.  */
5553   if (! rld[r1].in || ! rld[r2].in)
5554     return false;
5555 
5556   /* Avoid anything with output reloads.  */
5557   if (rld[r1].out || rld[r2].out)
5558     return false;
5559 
5560   /* "chained" means one reload is a component of the other reload,
5561      not the same as the other reload.  */
5562   if (rld[r1].opnum != rld[r2].opnum
5563       || rtx_equal_p (rld[r1].in, rld[r2].in)
5564       || rld[r1].optional || rld[r2].optional
5565       || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5566 	    || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5567     return false;
5568 
5569   for (i = 0; i < n_reloads; i ++)
5570     /* Look for input reloads that aren't our two */
5571     if (i != r1 && i != r2 && rld[i].in)
5572       {
5573 	/* If our reload is mentioned at all, it isn't a simple chain.  */
5574 	if (reg_mentioned_p (rld[r1].in, rld[i].in))
5575 	  return false;
5576       }
5577   return true;
5578 }
5579 
5580 /* The recursive function change all occurrences of WHAT in *WHERE
5581    to REPL.  */
5582 static void
substitute(rtx * where,const_rtx what,rtx repl)5583 substitute (rtx *where, const_rtx what, rtx repl)
5584 {
5585   const char *fmt;
5586   int i;
5587   enum rtx_code code;
5588 
5589   if (*where == 0)
5590     return;
5591 
5592   if (*where == what || rtx_equal_p (*where, what))
5593     {
5594       /* Record the location of the changed rtx.  */
5595       VEC_safe_push (rtx_p, heap, substitute_stack, where);
5596       *where = repl;
5597       return;
5598     }
5599 
5600   code = GET_CODE (*where);
5601   fmt = GET_RTX_FORMAT (code);
5602   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5603     {
5604       if (fmt[i] == 'E')
5605 	{
5606 	  int j;
5607 
5608 	  for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5609 	    substitute (&XVECEXP (*where, i, j), what, repl);
5610 	}
5611       else if (fmt[i] == 'e')
5612 	substitute (&XEXP (*where, i), what, repl);
5613     }
5614 }
5615 
5616 /* The function returns TRUE if chain of reload R1 and R2 (in any
5617    order) can be evaluated without usage of intermediate register for
5618    the reload containing another reload.  It is important to see
5619    gen_reload to understand what the function is trying to do.  As an
5620    example, let us have reload chain
5621 
5622       r2: const
5623       r1: <something> + const
5624 
5625    and reload R2 got reload reg HR.  The function returns true if
5626    there is a correct insn HR = HR + <something>.  Otherwise,
5627    gen_reload will use intermediate register (and this is the reload
5628    reg for R1) to reload <something>.
5629 
5630    We need this function to find a conflict for chain reloads.  In our
5631    example, if HR = HR + <something> is incorrect insn, then we cannot
5632    use HR as a reload register for R2.  If we do use it then we get a
5633    wrong code:
5634 
5635       HR = const
5636       HR = <something>
5637       HR = HR + HR
5638 
5639 */
5640 static bool
gen_reload_chain_without_interm_reg_p(int r1,int r2)5641 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5642 {
5643   /* Assume other cases in gen_reload are not possible for
5644      chain reloads or do need an intermediate hard registers.  */
5645   bool result = true;
5646   int regno, n, code;
5647   rtx out, in, insn;
5648   rtx last = get_last_insn ();
5649 
5650   /* Make r2 a component of r1.  */
5651   if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5652     {
5653       n = r1;
5654       r1 = r2;
5655       r2 = n;
5656     }
5657   gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5658   regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5659   gcc_assert (regno >= 0);
5660   out = gen_rtx_REG (rld[r1].mode, regno);
5661   in = rld[r1].in;
5662   substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5663 
5664   /* If IN is a paradoxical SUBREG, remove it and try to put the
5665      opposite SUBREG on OUT.  Likewise for a paradoxical SUBREG on OUT.  */
5666   strip_paradoxical_subreg (&in, &out);
5667 
5668   if (GET_CODE (in) == PLUS
5669       && (REG_P (XEXP (in, 0))
5670 	  || GET_CODE (XEXP (in, 0)) == SUBREG
5671 	  || MEM_P (XEXP (in, 0)))
5672       && (REG_P (XEXP (in, 1))
5673 	  || GET_CODE (XEXP (in, 1)) == SUBREG
5674 	  || CONSTANT_P (XEXP (in, 1))
5675 	  || MEM_P (XEXP (in, 1))))
5676     {
5677       insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
5678       code = recog_memoized (insn);
5679       result = false;
5680 
5681       if (code >= 0)
5682 	{
5683 	  extract_insn (insn);
5684 	  /* We want constrain operands to treat this insn strictly in
5685 	     its validity determination, i.e., the way it would after
5686 	     reload has completed.  */
5687 	  result = constrain_operands (1);
5688 	}
5689 
5690       delete_insns_since (last);
5691     }
5692 
5693   /* Restore the original value at each changed address within R1.  */
5694   while (!VEC_empty (rtx_p, substitute_stack))
5695     {
5696       rtx *where = VEC_pop (rtx_p, substitute_stack);
5697       *where = rld[r2].in;
5698     }
5699 
5700   return result;
5701 }
5702 
5703 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5704    Return 0 otherwise.
5705 
5706    This function uses the same algorithm as reload_reg_free_p above.  */
5707 
5708 static int
reloads_conflict(int r1,int r2)5709 reloads_conflict (int r1, int r2)
5710 {
5711   enum reload_type r1_type = rld[r1].when_needed;
5712   enum reload_type r2_type = rld[r2].when_needed;
5713   int r1_opnum = rld[r1].opnum;
5714   int r2_opnum = rld[r2].opnum;
5715 
5716   /* RELOAD_OTHER conflicts with everything.  */
5717   if (r2_type == RELOAD_OTHER)
5718     return 1;
5719 
5720   /* Otherwise, check conflicts differently for each type.  */
5721 
5722   switch (r1_type)
5723     {
5724     case RELOAD_FOR_INPUT:
5725       return (r2_type == RELOAD_FOR_INSN
5726 	      || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5727 	      || r2_type == RELOAD_FOR_OPADDR_ADDR
5728 	      || r2_type == RELOAD_FOR_INPUT
5729 	      || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5730 		   || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5731 		  && r2_opnum > r1_opnum));
5732 
5733     case RELOAD_FOR_INPUT_ADDRESS:
5734       return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5735 	      || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5736 
5737     case RELOAD_FOR_INPADDR_ADDRESS:
5738       return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5739 	      || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5740 
5741     case RELOAD_FOR_OUTPUT_ADDRESS:
5742       return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5743 	      || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5744 
5745     case RELOAD_FOR_OUTADDR_ADDRESS:
5746       return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5747 	      || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5748 
5749     case RELOAD_FOR_OPERAND_ADDRESS:
5750       return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5751 	      || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5752 		  && (!reloads_unique_chain_p (r1, r2)
5753 		      || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5754 
5755     case RELOAD_FOR_OPADDR_ADDR:
5756       return (r2_type == RELOAD_FOR_INPUT
5757 	      || r2_type == RELOAD_FOR_OPADDR_ADDR);
5758 
5759     case RELOAD_FOR_OUTPUT:
5760       return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5761 	      || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5762 		   || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5763 		  && r2_opnum >= r1_opnum));
5764 
5765     case RELOAD_FOR_INSN:
5766       return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5767 	      || r2_type == RELOAD_FOR_INSN
5768 	      || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5769 
5770     case RELOAD_FOR_OTHER_ADDRESS:
5771       return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5772 
5773     case RELOAD_OTHER:
5774       return 1;
5775 
5776     default:
5777       gcc_unreachable ();
5778     }
5779 }
5780 
5781 /* Indexed by reload number, 1 if incoming value
5782    inherited from previous insns.  */
5783 static char reload_inherited[MAX_RELOADS];
5784 
5785 /* For an inherited reload, this is the insn the reload was inherited from,
5786    if we know it.  Otherwise, this is 0.  */
5787 static rtx reload_inheritance_insn[MAX_RELOADS];
5788 
5789 /* If nonzero, this is a place to get the value of the reload,
5790    rather than using reload_in.  */
5791 static rtx reload_override_in[MAX_RELOADS];
5792 
5793 /* For each reload, the hard register number of the register used,
5794    or -1 if we did not need a register for this reload.  */
5795 static int reload_spill_index[MAX_RELOADS];
5796 
5797 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode.  */
5798 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5799 
5800 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode.  */
5801 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5802 
5803 /* Subroutine of free_for_value_p, used to check a single register.
5804    START_REGNO is the starting regno of the full reload register
5805    (possibly comprising multiple hard registers) that we are considering.  */
5806 
5807 static int
reload_reg_free_for_value_p(int start_regno,int regno,int opnum,enum reload_type type,rtx value,rtx out,int reloadnum,int ignore_address_reloads)5808 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5809 			     enum reload_type type, rtx value, rtx out,
5810 			     int reloadnum, int ignore_address_reloads)
5811 {
5812   int time1;
5813   /* Set if we see an input reload that must not share its reload register
5814      with any new earlyclobber, but might otherwise share the reload
5815      register with an output or input-output reload.  */
5816   int check_earlyclobber = 0;
5817   int i;
5818   int copy = 0;
5819 
5820   if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5821     return 0;
5822 
5823   if (out == const0_rtx)
5824     {
5825       copy = 1;
5826       out = NULL_RTX;
5827     }
5828 
5829   /* We use some pseudo 'time' value to check if the lifetimes of the
5830      new register use would overlap with the one of a previous reload
5831      that is not read-only or uses a different value.
5832      The 'time' used doesn't have to be linear in any shape or form, just
5833      monotonic.
5834      Some reload types use different 'buckets' for each operand.
5835      So there are MAX_RECOG_OPERANDS different time values for each
5836      such reload type.
5837      We compute TIME1 as the time when the register for the prospective
5838      new reload ceases to be live, and TIME2 for each existing
5839      reload as the time when that the reload register of that reload
5840      becomes live.
5841      Where there is little to be gained by exact lifetime calculations,
5842      we just make conservative assumptions, i.e. a longer lifetime;
5843      this is done in the 'default:' cases.  */
5844   switch (type)
5845     {
5846     case RELOAD_FOR_OTHER_ADDRESS:
5847       /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads.  */
5848       time1 = copy ? 0 : 1;
5849       break;
5850     case RELOAD_OTHER:
5851       time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5852       break;
5853       /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5854 	 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT.  By adding 0 / 1 / 2 ,
5855 	 respectively, to the time values for these, we get distinct time
5856 	 values.  To get distinct time values for each operand, we have to
5857 	 multiply opnum by at least three.  We round that up to four because
5858 	 multiply by four is often cheaper.  */
5859     case RELOAD_FOR_INPADDR_ADDRESS:
5860       time1 = opnum * 4 + 2;
5861       break;
5862     case RELOAD_FOR_INPUT_ADDRESS:
5863       time1 = opnum * 4 + 3;
5864       break;
5865     case RELOAD_FOR_INPUT:
5866       /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5867 	 executes (inclusive).  */
5868       time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5869       break;
5870     case RELOAD_FOR_OPADDR_ADDR:
5871       /* opnum * 4 + 4
5872 	 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5873       time1 = MAX_RECOG_OPERANDS * 4 + 1;
5874       break;
5875     case RELOAD_FOR_OPERAND_ADDRESS:
5876       /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5877 	 is executed.  */
5878       time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5879       break;
5880     case RELOAD_FOR_OUTADDR_ADDRESS:
5881       time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5882       break;
5883     case RELOAD_FOR_OUTPUT_ADDRESS:
5884       time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5885       break;
5886     default:
5887       time1 = MAX_RECOG_OPERANDS * 5 + 5;
5888     }
5889 
5890   for (i = 0; i < n_reloads; i++)
5891     {
5892       rtx reg = rld[i].reg_rtx;
5893       if (reg && REG_P (reg)
5894 	  && ((unsigned) regno - true_regnum (reg)
5895 	      <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5896 	  && i != reloadnum)
5897 	{
5898 	  rtx other_input = rld[i].in;
5899 
5900 	  /* If the other reload loads the same input value, that
5901 	     will not cause a conflict only if it's loading it into
5902 	     the same register.  */
5903 	  if (true_regnum (reg) != start_regno)
5904 	    other_input = NULL_RTX;
5905 	  if (! other_input || ! rtx_equal_p (other_input, value)
5906 	      || rld[i].out || out)
5907 	    {
5908 	      int time2;
5909 	      switch (rld[i].when_needed)
5910 		{
5911 		case RELOAD_FOR_OTHER_ADDRESS:
5912 		  time2 = 0;
5913 		  break;
5914 		case RELOAD_FOR_INPADDR_ADDRESS:
5915 		  /* find_reloads makes sure that a
5916 		     RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5917 		     by at most one - the first -
5918 		     RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS .  If the
5919 		     address reload is inherited, the address address reload
5920 		     goes away, so we can ignore this conflict.  */
5921 		  if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5922 		      && ignore_address_reloads
5923 		      /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5924 			 Then the address address is still needed to store
5925 			 back the new address.  */
5926 		      && ! rld[reloadnum].out)
5927 		    continue;
5928 		  /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5929 		     RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5930 		     reloads go away.  */
5931 		  if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5932 		      && ignore_address_reloads
5933 		      /* Unless we are reloading an auto_inc expression.  */
5934 		      && ! rld[reloadnum].out)
5935 		    continue;
5936 		  time2 = rld[i].opnum * 4 + 2;
5937 		  break;
5938 		case RELOAD_FOR_INPUT_ADDRESS:
5939 		  if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5940 		      && ignore_address_reloads
5941 		      && ! rld[reloadnum].out)
5942 		    continue;
5943 		  time2 = rld[i].opnum * 4 + 3;
5944 		  break;
5945 		case RELOAD_FOR_INPUT:
5946 		  time2 = rld[i].opnum * 4 + 4;
5947 		  check_earlyclobber = 1;
5948 		  break;
5949 		  /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5950 		     == MAX_RECOG_OPERAND * 4  */
5951 		case RELOAD_FOR_OPADDR_ADDR:
5952 		  if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5953 		      && ignore_address_reloads
5954 		      && ! rld[reloadnum].out)
5955 		    continue;
5956 		  time2 = MAX_RECOG_OPERANDS * 4 + 1;
5957 		  break;
5958 		case RELOAD_FOR_OPERAND_ADDRESS:
5959 		  time2 = MAX_RECOG_OPERANDS * 4 + 2;
5960 		  check_earlyclobber = 1;
5961 		  break;
5962 		case RELOAD_FOR_INSN:
5963 		  time2 = MAX_RECOG_OPERANDS * 4 + 3;
5964 		  break;
5965 		case RELOAD_FOR_OUTPUT:
5966 		  /* All RELOAD_FOR_OUTPUT reloads become live just after the
5967 		     instruction is executed.  */
5968 		  time2 = MAX_RECOG_OPERANDS * 4 + 4;
5969 		  break;
5970 		  /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5971 		     the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5972 		     value.  */
5973 		case RELOAD_FOR_OUTADDR_ADDRESS:
5974 		  if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5975 		      && ignore_address_reloads
5976 		      && ! rld[reloadnum].out)
5977 		    continue;
5978 		  time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5979 		  break;
5980 		case RELOAD_FOR_OUTPUT_ADDRESS:
5981 		  time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5982 		  break;
5983 		case RELOAD_OTHER:
5984 		  /* If there is no conflict in the input part, handle this
5985 		     like an output reload.  */
5986 		  if (! rld[i].in || rtx_equal_p (other_input, value))
5987 		    {
5988 		      time2 = MAX_RECOG_OPERANDS * 4 + 4;
5989 		      /* Earlyclobbered outputs must conflict with inputs.  */
5990 		      if (earlyclobber_operand_p (rld[i].out))
5991 			time2 = MAX_RECOG_OPERANDS * 4 + 3;
5992 
5993 		      break;
5994 		    }
5995 		  time2 = 1;
5996 		  /* RELOAD_OTHER might be live beyond instruction execution,
5997 		     but this is not obvious when we set time2 = 1.  So check
5998 		     here if there might be a problem with the new reload
5999 		     clobbering the register used by the RELOAD_OTHER.  */
6000 		  if (out)
6001 		    return 0;
6002 		  break;
6003 		default:
6004 		  return 0;
6005 		}
6006 	      if ((time1 >= time2
6007 		   && (! rld[i].in || rld[i].out
6008 		       || ! rtx_equal_p (other_input, value)))
6009 		  || (out && rld[reloadnum].out_reg
6010 		      && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
6011 		return 0;
6012 	    }
6013 	}
6014     }
6015 
6016   /* Earlyclobbered outputs must conflict with inputs.  */
6017   if (check_earlyclobber && out && earlyclobber_operand_p (out))
6018     return 0;
6019 
6020   return 1;
6021 }
6022 
6023 /* Return 1 if the value in reload reg REGNO, as used by a reload
6024    needed for the part of the insn specified by OPNUM and TYPE,
6025    may be used to load VALUE into it.
6026 
6027    MODE is the mode in which the register is used, this is needed to
6028    determine how many hard regs to test.
6029 
6030    Other read-only reloads with the same value do not conflict
6031    unless OUT is nonzero and these other reloads have to live while
6032    output reloads live.
6033    If OUT is CONST0_RTX, this is a special case: it means that the
6034    test should not be for using register REGNO as reload register, but
6035    for copying from register REGNO into the reload register.
6036 
6037    RELOADNUM is the number of the reload we want to load this value for;
6038    a reload does not conflict with itself.
6039 
6040    When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
6041    reloads that load an address for the very reload we are considering.
6042 
6043    The caller has to make sure that there is no conflict with the return
6044    register.  */
6045 
6046 static int
free_for_value_p(int regno,enum machine_mode mode,int opnum,enum reload_type type,rtx value,rtx out,int reloadnum,int ignore_address_reloads)6047 free_for_value_p (int regno, enum machine_mode mode, int opnum,
6048 		  enum reload_type type, rtx value, rtx out, int reloadnum,
6049 		  int ignore_address_reloads)
6050 {
6051   int nregs = hard_regno_nregs[regno][mode];
6052   while (nregs-- > 0)
6053     if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
6054 				       value, out, reloadnum,
6055 				       ignore_address_reloads))
6056       return 0;
6057   return 1;
6058 }
6059 
6060 /* Return nonzero if the rtx X is invariant over the current function.  */
6061 /* ??? Actually, the places where we use this expect exactly what is
6062    tested here, and not everything that is function invariant.  In
6063    particular, the frame pointer and arg pointer are special cased;
6064    pic_offset_table_rtx is not, and we must not spill these things to
6065    memory.  */
6066 
6067 int
function_invariant_p(const_rtx x)6068 function_invariant_p (const_rtx x)
6069 {
6070   if (CONSTANT_P (x))
6071     return 1;
6072   if (x == frame_pointer_rtx || x == arg_pointer_rtx)
6073     return 1;
6074   if (GET_CODE (x) == PLUS
6075       && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
6076       && GET_CODE (XEXP (x, 1)) == CONST_INT)
6077     return 1;
6078   return 0;
6079 }
6080 
6081 /* Determine whether the reload reg X overlaps any rtx'es used for
6082    overriding inheritance.  Return nonzero if so.  */
6083 
6084 static int
conflicts_with_override(rtx x)6085 conflicts_with_override (rtx x)
6086 {
6087   int i;
6088   for (i = 0; i < n_reloads; i++)
6089     if (reload_override_in[i]
6090 	&& reg_overlap_mentioned_p (x, reload_override_in[i]))
6091       return 1;
6092   return 0;
6093 }
6094 
6095 /* Give an error message saying we failed to find a reload for INSN,
6096    and clear out reload R.  */
6097 static void
failed_reload(rtx insn,int r)6098 failed_reload (rtx insn, int r)
6099 {
6100   if (asm_noperands (PATTERN (insn)) < 0)
6101     /* It's the compiler's fault.  */
6102     fatal_insn ("could not find a spill register", insn);
6103 
6104   /* It's the user's fault; the operand's mode and constraint
6105      don't match.  Disable this reload so we don't crash in final.  */
6106   error_for_asm (insn,
6107 		 "%<asm%> operand constraint incompatible with operand size");
6108   rld[r].in = 0;
6109   rld[r].out = 0;
6110   rld[r].reg_rtx = 0;
6111   rld[r].optional = 1;
6112   rld[r].secondary_p = 1;
6113 }
6114 
6115 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6116    for reload R.  If it's valid, get an rtx for it.  Return nonzero if
6117    successful.  */
6118 static int
set_reload_reg(int i,int r)6119 set_reload_reg (int i, int r)
6120 {
6121   /* regno is 'set but not used' if HARD_REGNO_MODE_OK doesn't use its first
6122      parameter.  */
6123   int regno ATTRIBUTE_UNUSED;
6124   rtx reg = spill_reg_rtx[i];
6125 
6126   if (reg == 0 || GET_MODE (reg) != rld[r].mode)
6127     spill_reg_rtx[i] = reg
6128       = gen_rtx_REG (rld[r].mode, spill_regs[i]);
6129 
6130   regno = true_regnum (reg);
6131 
6132   /* Detect when the reload reg can't hold the reload mode.
6133      This used to be one `if', but Sequent compiler can't handle that.  */
6134   if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
6135     {
6136       enum machine_mode test_mode = VOIDmode;
6137       if (rld[r].in)
6138 	test_mode = GET_MODE (rld[r].in);
6139       /* If rld[r].in has VOIDmode, it means we will load it
6140 	 in whatever mode the reload reg has: to wit, rld[r].mode.
6141 	 We have already tested that for validity.  */
6142       /* Aside from that, we need to test that the expressions
6143 	 to reload from or into have modes which are valid for this
6144 	 reload register.  Otherwise the reload insns would be invalid.  */
6145       if (! (rld[r].in != 0 && test_mode != VOIDmode
6146 	     && ! HARD_REGNO_MODE_OK (regno, test_mode)))
6147 	if (! (rld[r].out != 0
6148 	       && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
6149 	  {
6150 	    /* The reg is OK.  */
6151 	    last_spill_reg = i;
6152 
6153 	    /* Mark as in use for this insn the reload regs we use
6154 	       for this.  */
6155 	    mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
6156 				    rld[r].when_needed, rld[r].mode);
6157 
6158 	    rld[r].reg_rtx = reg;
6159 	    reload_spill_index[r] = spill_regs[i];
6160 	    return 1;
6161 	  }
6162     }
6163   return 0;
6164 }
6165 
6166 /* Find a spill register to use as a reload register for reload R.
6167    LAST_RELOAD is nonzero if this is the last reload for the insn being
6168    processed.
6169 
6170    Set rld[R].reg_rtx to the register allocated.
6171 
6172    We return 1 if successful, or 0 if we couldn't find a spill reg and
6173    we didn't change anything.  */
6174 
6175 static int
allocate_reload_reg(struct insn_chain * chain ATTRIBUTE_UNUSED,int r,int last_reload)6176 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
6177 		     int last_reload)
6178 {
6179   int i, pass, count;
6180 
6181   /* If we put this reload ahead, thinking it is a group,
6182      then insist on finding a group.  Otherwise we can grab a
6183      reg that some other reload needs.
6184      (That can happen when we have a 68000 DATA_OR_FP_REG
6185      which is a group of data regs or one fp reg.)
6186      We need not be so restrictive if there are no more reloads
6187      for this insn.
6188 
6189      ??? Really it would be nicer to have smarter handling
6190      for that kind of reg class, where a problem like this is normal.
6191      Perhaps those classes should be avoided for reloading
6192      by use of more alternatives.  */
6193 
6194   int force_group = rld[r].nregs > 1 && ! last_reload;
6195 
6196   /* If we want a single register and haven't yet found one,
6197      take any reg in the right class and not in use.
6198      If we want a consecutive group, here is where we look for it.
6199 
6200      We use three passes so we can first look for reload regs to
6201      reuse, which are already in use for other reloads in this insn,
6202      and only then use additional registers which are not "bad", then
6203      finally any register.
6204 
6205      I think that maximizing reuse is needed to make sure we don't
6206      run out of reload regs.  Suppose we have three reloads, and
6207      reloads A and B can share regs.  These need two regs.
6208      Suppose A and B are given different regs.
6209      That leaves none for C.  */
6210   for (pass = 0; pass < 3; pass++)
6211     {
6212       /* I is the index in spill_regs.
6213 	 We advance it round-robin between insns to use all spill regs
6214 	 equally, so that inherited reloads have a chance
6215 	 of leapfrogging each other.  */
6216 
6217       i = last_spill_reg;
6218 
6219       for (count = 0; count < n_spills; count++)
6220 	{
6221 	  int rclass = (int) rld[r].rclass;
6222 	  int regnum;
6223 
6224 	  i++;
6225 	  if (i >= n_spills)
6226 	    i -= n_spills;
6227 	  regnum = spill_regs[i];
6228 
6229 	  if ((reload_reg_free_p (regnum, rld[r].opnum,
6230 				  rld[r].when_needed)
6231 	       || (rld[r].in
6232 		   /* We check reload_reg_used to make sure we
6233 		      don't clobber the return register.  */
6234 		   && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
6235 		   && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
6236 					rld[r].when_needed, rld[r].in,
6237 					rld[r].out, r, 1)))
6238 	      && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
6239 	      && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
6240 	      /* Look first for regs to share, then for unshared.  But
6241 		 don't share regs used for inherited reloads; they are
6242 		 the ones we want to preserve.  */
6243 	      && (pass
6244 		  || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
6245 					 regnum)
6246 		      && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
6247 					      regnum))))
6248 	    {
6249 	      int nr = hard_regno_nregs[regnum][rld[r].mode];
6250 
6251 	      /* During the second pass we want to avoid reload registers
6252 		 which are "bad" for this reload.  */
6253 	      if (pass == 1
6254 		  && ira_bad_reload_regno (regnum, rld[r].in, rld[r].out))
6255 		continue;
6256 
6257 	      /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6258 		 (on 68000) got us two FP regs.  If NR is 1,
6259 		 we would reject both of them.  */
6260 	      if (force_group)
6261 		nr = rld[r].nregs;
6262 	      /* If we need only one reg, we have already won.  */
6263 	      if (nr == 1)
6264 		{
6265 		  /* But reject a single reg if we demand a group.  */
6266 		  if (force_group)
6267 		    continue;
6268 		  break;
6269 		}
6270 	      /* Otherwise check that as many consecutive regs as we need
6271 		 are available here.  */
6272 	      while (nr > 1)
6273 		{
6274 		  int regno = regnum + nr - 1;
6275 		  if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
6276 			&& spill_reg_order[regno] >= 0
6277 			&& reload_reg_free_p (regno, rld[r].opnum,
6278 					      rld[r].when_needed)))
6279 		    break;
6280 		  nr--;
6281 		}
6282 	      if (nr == 1)
6283 		break;
6284 	    }
6285 	}
6286 
6287       /* If we found something on the current pass, omit later passes.  */
6288       if (count < n_spills)
6289 	break;
6290     }
6291 
6292   /* We should have found a spill register by now.  */
6293   if (count >= n_spills)
6294     return 0;
6295 
6296   /* I is the index in SPILL_REG_RTX of the reload register we are to
6297      allocate.  Get an rtx for it and find its register number.  */
6298 
6299   return set_reload_reg (i, r);
6300 }
6301 
6302 /* Initialize all the tables needed to allocate reload registers.
6303    CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6304    is the array we use to restore the reg_rtx field for every reload.  */
6305 
6306 static void
choose_reload_regs_init(struct insn_chain * chain,rtx * save_reload_reg_rtx)6307 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
6308 {
6309   int i;
6310 
6311   for (i = 0; i < n_reloads; i++)
6312     rld[i].reg_rtx = save_reload_reg_rtx[i];
6313 
6314   memset (reload_inherited, 0, MAX_RELOADS);
6315   memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
6316   memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
6317 
6318   CLEAR_HARD_REG_SET (reload_reg_used);
6319   CLEAR_HARD_REG_SET (reload_reg_used_at_all);
6320   CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
6321   CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
6322   CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
6323   CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
6324 
6325   CLEAR_HARD_REG_SET (reg_used_in_insn);
6326   {
6327     HARD_REG_SET tmp;
6328     REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
6329     IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6330     REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
6331     IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6332     compute_use_by_pseudos (&reg_used_in_insn, &chain->live_throughout);
6333     compute_use_by_pseudos (&reg_used_in_insn, &chain->dead_or_set);
6334   }
6335 
6336   for (i = 0; i < reload_n_operands; i++)
6337     {
6338       CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
6339       CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
6340       CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
6341       CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
6342       CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
6343       CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
6344     }
6345 
6346   COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
6347 
6348   CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
6349 
6350   for (i = 0; i < n_reloads; i++)
6351     /* If we have already decided to use a certain register,
6352        don't use it in another way.  */
6353     if (rld[i].reg_rtx)
6354       mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
6355 			      rld[i].when_needed, rld[i].mode);
6356 }
6357 
6358 /* Assign hard reg targets for the pseudo-registers we must reload
6359    into hard regs for this insn.
6360    Also output the instructions to copy them in and out of the hard regs.
6361 
6362    For machines with register classes, we are responsible for
6363    finding a reload reg in the proper class.  */
6364 
6365 static void
choose_reload_regs(struct insn_chain * chain)6366 choose_reload_regs (struct insn_chain *chain)
6367 {
6368   rtx insn = chain->insn;
6369   int i, j;
6370   unsigned int max_group_size = 1;
6371   enum reg_class group_class = NO_REGS;
6372   int pass, win, inheritance;
6373 
6374   rtx save_reload_reg_rtx[MAX_RELOADS];
6375 
6376   /* In order to be certain of getting the registers we need,
6377      we must sort the reloads into order of increasing register class.
6378      Then our grabbing of reload registers will parallel the process
6379      that provided the reload registers.
6380 
6381      Also note whether any of the reloads wants a consecutive group of regs.
6382      If so, record the maximum size of the group desired and what
6383      register class contains all the groups needed by this insn.  */
6384 
6385   for (j = 0; j < n_reloads; j++)
6386     {
6387       reload_order[j] = j;
6388       if (rld[j].reg_rtx != NULL_RTX)
6389 	{
6390 	  gcc_assert (REG_P (rld[j].reg_rtx)
6391 		      && HARD_REGISTER_P (rld[j].reg_rtx));
6392 	  reload_spill_index[j] = REGNO (rld[j].reg_rtx);
6393 	}
6394       else
6395 	reload_spill_index[j] = -1;
6396 
6397       if (rld[j].nregs > 1)
6398 	{
6399 	  max_group_size = MAX (rld[j].nregs, max_group_size);
6400 	  group_class
6401 	    = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
6402 	}
6403 
6404       save_reload_reg_rtx[j] = rld[j].reg_rtx;
6405     }
6406 
6407   if (n_reloads > 1)
6408     qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
6409 
6410   /* If -O, try first with inheritance, then turning it off.
6411      If not -O, don't do inheritance.
6412      Using inheritance when not optimizing leads to paradoxes
6413      with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6414      because one side of the comparison might be inherited.  */
6415   win = 0;
6416   for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
6417     {
6418       choose_reload_regs_init (chain, save_reload_reg_rtx);
6419 
6420       /* Process the reloads in order of preference just found.
6421 	 Beyond this point, subregs can be found in reload_reg_rtx.
6422 
6423 	 This used to look for an existing reloaded home for all of the
6424 	 reloads, and only then perform any new reloads.  But that could lose
6425 	 if the reloads were done out of reg-class order because a later
6426 	 reload with a looser constraint might have an old home in a register
6427 	 needed by an earlier reload with a tighter constraint.
6428 
6429 	 To solve this, we make two passes over the reloads, in the order
6430 	 described above.  In the first pass we try to inherit a reload
6431 	 from a previous insn.  If there is a later reload that needs a
6432 	 class that is a proper subset of the class being processed, we must
6433 	 also allocate a spill register during the first pass.
6434 
6435 	 Then make a second pass over the reloads to allocate any reloads
6436 	 that haven't been given registers yet.  */
6437 
6438       for (j = 0; j < n_reloads; j++)
6439 	{
6440 	  int r = reload_order[j];
6441 	  rtx search_equiv = NULL_RTX;
6442 
6443 	  /* Ignore reloads that got marked inoperative.  */
6444 	  if (rld[r].out == 0 && rld[r].in == 0
6445 	      && ! rld[r].secondary_p)
6446 	    continue;
6447 
6448 	  /* If find_reloads chose to use reload_in or reload_out as a reload
6449 	     register, we don't need to chose one.  Otherwise, try even if it
6450 	     found one since we might save an insn if we find the value lying
6451 	     around.
6452 	     Try also when reload_in is a pseudo without a hard reg.  */
6453 	  if (rld[r].in != 0 && rld[r].reg_rtx != 0
6454 	      && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
6455 		  || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
6456 		      && !MEM_P (rld[r].in)
6457 		      && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
6458 	    continue;
6459 
6460 #if 0 /* No longer needed for correct operation.
6461 	 It might give better code, or might not; worth an experiment?  */
6462 	  /* If this is an optional reload, we can't inherit from earlier insns
6463 	     until we are sure that any non-optional reloads have been allocated.
6464 	     The following code takes advantage of the fact that optional reloads
6465 	     are at the end of reload_order.  */
6466 	  if (rld[r].optional != 0)
6467 	    for (i = 0; i < j; i++)
6468 	      if ((rld[reload_order[i]].out != 0
6469 		   || rld[reload_order[i]].in != 0
6470 		   || rld[reload_order[i]].secondary_p)
6471 		  && ! rld[reload_order[i]].optional
6472 		  && rld[reload_order[i]].reg_rtx == 0)
6473 		allocate_reload_reg (chain, reload_order[i], 0);
6474 #endif
6475 
6476 	  /* First see if this pseudo is already available as reloaded
6477 	     for a previous insn.  We cannot try to inherit for reloads
6478 	     that are smaller than the maximum number of registers needed
6479 	     for groups unless the register we would allocate cannot be used
6480 	     for the groups.
6481 
6482 	     We could check here to see if this is a secondary reload for
6483 	     an object that is already in a register of the desired class.
6484 	     This would avoid the need for the secondary reload register.
6485 	     But this is complex because we can't easily determine what
6486 	     objects might want to be loaded via this reload.  So let a
6487 	     register be allocated here.  In `emit_reload_insns' we suppress
6488 	     one of the loads in the case described above.  */
6489 
6490 	  if (inheritance)
6491 	    {
6492 	      int byte = 0;
6493 	      int regno = -1;
6494 	      enum machine_mode mode = VOIDmode;
6495 
6496 	      if (rld[r].in == 0)
6497 		;
6498 	      else if (REG_P (rld[r].in))
6499 		{
6500 		  regno = REGNO (rld[r].in);
6501 		  mode = GET_MODE (rld[r].in);
6502 		}
6503 	      else if (REG_P (rld[r].in_reg))
6504 		{
6505 		  regno = REGNO (rld[r].in_reg);
6506 		  mode = GET_MODE (rld[r].in_reg);
6507 		}
6508 	      else if (GET_CODE (rld[r].in_reg) == SUBREG
6509 		       && REG_P (SUBREG_REG (rld[r].in_reg)))
6510 		{
6511 		  regno = REGNO (SUBREG_REG (rld[r].in_reg));
6512 		  if (regno < FIRST_PSEUDO_REGISTER)
6513 		    regno = subreg_regno (rld[r].in_reg);
6514 		  else
6515 		    byte = SUBREG_BYTE (rld[r].in_reg);
6516 		  mode = GET_MODE (rld[r].in_reg);
6517 		}
6518 #ifdef AUTO_INC_DEC
6519 	      else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6520 		       && REG_P (XEXP (rld[r].in_reg, 0)))
6521 		{
6522 		  regno = REGNO (XEXP (rld[r].in_reg, 0));
6523 		  mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6524 		  rld[r].out = rld[r].in;
6525 		}
6526 #endif
6527 #if 0
6528 	      /* This won't work, since REGNO can be a pseudo reg number.
6529 		 Also, it takes much more hair to keep track of all the things
6530 		 that can invalidate an inherited reload of part of a pseudoreg.  */
6531 	      else if (GET_CODE (rld[r].in) == SUBREG
6532 		       && REG_P (SUBREG_REG (rld[r].in)))
6533 		regno = subreg_regno (rld[r].in);
6534 #endif
6535 
6536 	      if (regno >= 0
6537 		  && reg_last_reload_reg[regno] != 0
6538 		  && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
6539 		      >= GET_MODE_SIZE (mode) + byte)
6540 #ifdef CANNOT_CHANGE_MODE_CLASS
6541 		  /* Verify that the register it's in can be used in
6542 		     mode MODE.  */
6543 		  && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
6544 						GET_MODE (reg_last_reload_reg[regno]),
6545 						mode)
6546 #endif
6547 		  )
6548 		{
6549 		  enum reg_class rclass = rld[r].rclass, last_class;
6550 		  rtx last_reg = reg_last_reload_reg[regno];
6551 
6552 		  i = REGNO (last_reg);
6553 		  i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6554 		  last_class = REGNO_REG_CLASS (i);
6555 
6556 		  if (reg_reloaded_contents[i] == regno
6557 		      && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6558 		      && HARD_REGNO_MODE_OK (i, rld[r].mode)
6559 		      && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6560 			  /* Even if we can't use this register as a reload
6561 			     register, we might use it for reload_override_in,
6562 			     if copying it to the desired class is cheap
6563 			     enough.  */
6564 			  || ((register_move_cost (mode, last_class, rclass)
6565 			       < memory_move_cost (mode, rclass, true))
6566 			      && (secondary_reload_class (1, rclass, mode,
6567 							  last_reg)
6568 				  == NO_REGS)
6569 #ifdef SECONDARY_MEMORY_NEEDED
6570 			      && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
6571 							    mode)
6572 #endif
6573 			      ))
6574 
6575 		      && (rld[r].nregs == max_group_size
6576 			  || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6577 						  i))
6578 		      && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6579 					   rld[r].when_needed, rld[r].in,
6580 					   const0_rtx, r, 1))
6581 		    {
6582 		      /* If a group is needed, verify that all the subsequent
6583 			 registers still have their values intact.  */
6584 		      int nr = hard_regno_nregs[i][rld[r].mode];
6585 		      int k;
6586 
6587 		      for (k = 1; k < nr; k++)
6588 			if (reg_reloaded_contents[i + k] != regno
6589 			    || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6590 			  break;
6591 
6592 		      if (k == nr)
6593 			{
6594 			  int i1;
6595 			  int bad_for_class;
6596 
6597 			  last_reg = (GET_MODE (last_reg) == mode
6598 				      ? last_reg : gen_rtx_REG (mode, i));
6599 
6600 			  bad_for_class = 0;
6601 			  for (k = 0; k < nr; k++)
6602 			    bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6603 								  i+k);
6604 
6605 			  /* We found a register that contains the
6606 			     value we need.  If this register is the
6607 			     same as an `earlyclobber' operand of the
6608 			     current insn, just mark it as a place to
6609 			     reload from since we can't use it as the
6610 			     reload register itself.  */
6611 
6612 			  for (i1 = 0; i1 < n_earlyclobbers; i1++)
6613 			    if (reg_overlap_mentioned_for_reload_p
6614 				(reg_last_reload_reg[regno],
6615 				 reload_earlyclobbers[i1]))
6616 			      break;
6617 
6618 			  if (i1 != n_earlyclobbers
6619 			      || ! (free_for_value_p (i, rld[r].mode,
6620 						      rld[r].opnum,
6621 						      rld[r].when_needed, rld[r].in,
6622 						      rld[r].out, r, 1))
6623 			      /* Don't use it if we'd clobber a pseudo reg.  */
6624 			      || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6625 				  && rld[r].out
6626 				  && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6627 			      /* Don't clobber the frame pointer.  */
6628 			      || (i == HARD_FRAME_POINTER_REGNUM
6629 				  && frame_pointer_needed
6630 				  && rld[r].out)
6631 			      /* Don't really use the inherited spill reg
6632 				 if we need it wider than we've got it.  */
6633 			      || (GET_MODE_SIZE (rld[r].mode)
6634 				  > GET_MODE_SIZE (mode))
6635 			      || bad_for_class
6636 
6637 			      /* If find_reloads chose reload_out as reload
6638 				 register, stay with it - that leaves the
6639 				 inherited register for subsequent reloads.  */
6640 			      || (rld[r].out && rld[r].reg_rtx
6641 				  && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6642 			    {
6643 			      if (! rld[r].optional)
6644 				{
6645 				  reload_override_in[r] = last_reg;
6646 				  reload_inheritance_insn[r]
6647 				    = reg_reloaded_insn[i];
6648 				}
6649 			    }
6650 			  else
6651 			    {
6652 			      int k;
6653 			      /* We can use this as a reload reg.  */
6654 			      /* Mark the register as in use for this part of
6655 				 the insn.  */
6656 			      mark_reload_reg_in_use (i,
6657 						      rld[r].opnum,
6658 						      rld[r].when_needed,
6659 						      rld[r].mode);
6660 			      rld[r].reg_rtx = last_reg;
6661 			      reload_inherited[r] = 1;
6662 			      reload_inheritance_insn[r]
6663 				= reg_reloaded_insn[i];
6664 			      reload_spill_index[r] = i;
6665 			      for (k = 0; k < nr; k++)
6666 				SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6667 						  i + k);
6668 			    }
6669 			}
6670 		    }
6671 		}
6672 	    }
6673 
6674 	  /* Here's another way to see if the value is already lying around.  */
6675 	  if (inheritance
6676 	      && rld[r].in != 0
6677 	      && ! reload_inherited[r]
6678 	      && rld[r].out == 0
6679 	      && (CONSTANT_P (rld[r].in)
6680 		  || GET_CODE (rld[r].in) == PLUS
6681 		  || REG_P (rld[r].in)
6682 		  || MEM_P (rld[r].in))
6683 	      && (rld[r].nregs == max_group_size
6684 		  || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6685 	    search_equiv = rld[r].in;
6686 
6687 	  if (search_equiv)
6688 	    {
6689 	      rtx equiv
6690 		= find_equiv_reg (search_equiv, insn, rld[r].rclass,
6691 				  -1, NULL, 0, rld[r].mode);
6692 	      int regno = 0;
6693 
6694 	      if (equiv != 0)
6695 		{
6696 		  if (REG_P (equiv))
6697 		    regno = REGNO (equiv);
6698 		  else
6699 		    {
6700 		      /* This must be a SUBREG of a hard register.
6701 			 Make a new REG since this might be used in an
6702 			 address and not all machines support SUBREGs
6703 			 there.  */
6704 		      gcc_assert (GET_CODE (equiv) == SUBREG);
6705 		      regno = subreg_regno (equiv);
6706 		      equiv = gen_rtx_REG (rld[r].mode, regno);
6707 		      /* If we choose EQUIV as the reload register, but the
6708 			 loop below decides to cancel the inheritance, we'll
6709 			 end up reloading EQUIV in rld[r].mode, not the mode
6710 			 it had originally.  That isn't safe when EQUIV isn't
6711 			 available as a spill register since its value might
6712 			 still be live at this point.  */
6713 		      for (i = regno; i < regno + (int) rld[r].nregs; i++)
6714 			if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6715 			  equiv = 0;
6716 		    }
6717 		}
6718 
6719 	      /* If we found a spill reg, reject it unless it is free
6720 		 and of the desired class.  */
6721 	      if (equiv != 0)
6722 		{
6723 		  int regs_used = 0;
6724 		  int bad_for_class = 0;
6725 		  int max_regno = regno + rld[r].nregs;
6726 
6727 		  for (i = regno; i < max_regno; i++)
6728 		    {
6729 		      regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6730 						      i);
6731 		      bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6732 							   i);
6733 		    }
6734 
6735 		  if ((regs_used
6736 		       && ! free_for_value_p (regno, rld[r].mode,
6737 					      rld[r].opnum, rld[r].when_needed,
6738 					      rld[r].in, rld[r].out, r, 1))
6739 		      || bad_for_class)
6740 		    equiv = 0;
6741 		}
6742 
6743 	      if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6744 		equiv = 0;
6745 
6746 	      /* We found a register that contains the value we need.
6747 		 If this register is the same as an `earlyclobber' operand
6748 		 of the current insn, just mark it as a place to reload from
6749 		 since we can't use it as the reload register itself.  */
6750 
6751 	      if (equiv != 0)
6752 		for (i = 0; i < n_earlyclobbers; i++)
6753 		  if (reg_overlap_mentioned_for_reload_p (equiv,
6754 							  reload_earlyclobbers[i]))
6755 		    {
6756 		      if (! rld[r].optional)
6757 			reload_override_in[r] = equiv;
6758 		      equiv = 0;
6759 		      break;
6760 		    }
6761 
6762 	      /* If the equiv register we have found is explicitly clobbered
6763 		 in the current insn, it depends on the reload type if we
6764 		 can use it, use it for reload_override_in, or not at all.
6765 		 In particular, we then can't use EQUIV for a
6766 		 RELOAD_FOR_OUTPUT_ADDRESS reload.  */
6767 
6768 	      if (equiv != 0)
6769 		{
6770 		  if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6771 		    switch (rld[r].when_needed)
6772 		      {
6773 		      case RELOAD_FOR_OTHER_ADDRESS:
6774 		      case RELOAD_FOR_INPADDR_ADDRESS:
6775 		      case RELOAD_FOR_INPUT_ADDRESS:
6776 		      case RELOAD_FOR_OPADDR_ADDR:
6777 			break;
6778 		      case RELOAD_OTHER:
6779 		      case RELOAD_FOR_INPUT:
6780 		      case RELOAD_FOR_OPERAND_ADDRESS:
6781 			if (! rld[r].optional)
6782 			  reload_override_in[r] = equiv;
6783 			/* Fall through.  */
6784 		      default:
6785 			equiv = 0;
6786 			break;
6787 		      }
6788 		  else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6789 		    switch (rld[r].when_needed)
6790 		      {
6791 		      case RELOAD_FOR_OTHER_ADDRESS:
6792 		      case RELOAD_FOR_INPADDR_ADDRESS:
6793 		      case RELOAD_FOR_INPUT_ADDRESS:
6794 		      case RELOAD_FOR_OPADDR_ADDR:
6795 		      case RELOAD_FOR_OPERAND_ADDRESS:
6796 		      case RELOAD_FOR_INPUT:
6797 			break;
6798 		      case RELOAD_OTHER:
6799 			if (! rld[r].optional)
6800 			  reload_override_in[r] = equiv;
6801 			/* Fall through.  */
6802 		      default:
6803 			equiv = 0;
6804 			break;
6805 		      }
6806 		}
6807 
6808 	      /* If we found an equivalent reg, say no code need be generated
6809 		 to load it, and use it as our reload reg.  */
6810 	      if (equiv != 0
6811 		  && (regno != HARD_FRAME_POINTER_REGNUM
6812 		      || !frame_pointer_needed))
6813 		{
6814 		  int nr = hard_regno_nregs[regno][rld[r].mode];
6815 		  int k;
6816 		  rld[r].reg_rtx = equiv;
6817 		  reload_spill_index[r] = regno;
6818 		  reload_inherited[r] = 1;
6819 
6820 		  /* If reg_reloaded_valid is not set for this register,
6821 		     there might be a stale spill_reg_store lying around.
6822 		     We must clear it, since otherwise emit_reload_insns
6823 		     might delete the store.  */
6824 		  if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6825 		    spill_reg_store[regno] = NULL_RTX;
6826 		  /* If any of the hard registers in EQUIV are spill
6827 		     registers, mark them as in use for this insn.  */
6828 		  for (k = 0; k < nr; k++)
6829 		    {
6830 		      i = spill_reg_order[regno + k];
6831 		      if (i >= 0)
6832 			{
6833 			  mark_reload_reg_in_use (regno, rld[r].opnum,
6834 						  rld[r].when_needed,
6835 						  rld[r].mode);
6836 			  SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6837 					    regno + k);
6838 			}
6839 		    }
6840 		}
6841 	    }
6842 
6843 	  /* If we found a register to use already, or if this is an optional
6844 	     reload, we are done.  */
6845 	  if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6846 	    continue;
6847 
6848 #if 0
6849 	  /* No longer needed for correct operation.  Might or might
6850 	     not give better code on the average.  Want to experiment?  */
6851 
6852 	  /* See if there is a later reload that has a class different from our
6853 	     class that intersects our class or that requires less register
6854 	     than our reload.  If so, we must allocate a register to this
6855 	     reload now, since that reload might inherit a previous reload
6856 	     and take the only available register in our class.  Don't do this
6857 	     for optional reloads since they will force all previous reloads
6858 	     to be allocated.  Also don't do this for reloads that have been
6859 	     turned off.  */
6860 
6861 	  for (i = j + 1; i < n_reloads; i++)
6862 	    {
6863 	      int s = reload_order[i];
6864 
6865 	      if ((rld[s].in == 0 && rld[s].out == 0
6866 		   && ! rld[s].secondary_p)
6867 		  || rld[s].optional)
6868 		continue;
6869 
6870 	      if ((rld[s].rclass != rld[r].rclass
6871 		   && reg_classes_intersect_p (rld[r].rclass,
6872 					       rld[s].rclass))
6873 		  || rld[s].nregs < rld[r].nregs)
6874 		break;
6875 	    }
6876 
6877 	  if (i == n_reloads)
6878 	    continue;
6879 
6880 	  allocate_reload_reg (chain, r, j == n_reloads - 1);
6881 #endif
6882 	}
6883 
6884       /* Now allocate reload registers for anything non-optional that
6885 	 didn't get one yet.  */
6886       for (j = 0; j < n_reloads; j++)
6887 	{
6888 	  int r = reload_order[j];
6889 
6890 	  /* Ignore reloads that got marked inoperative.  */
6891 	  if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6892 	    continue;
6893 
6894 	  /* Skip reloads that already have a register allocated or are
6895 	     optional.  */
6896 	  if (rld[r].reg_rtx != 0 || rld[r].optional)
6897 	    continue;
6898 
6899 	  if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6900 	    break;
6901 	}
6902 
6903       /* If that loop got all the way, we have won.  */
6904       if (j == n_reloads)
6905 	{
6906 	  win = 1;
6907 	  break;
6908 	}
6909 
6910       /* Loop around and try without any inheritance.  */
6911     }
6912 
6913   if (! win)
6914     {
6915       /* First undo everything done by the failed attempt
6916 	 to allocate with inheritance.  */
6917       choose_reload_regs_init (chain, save_reload_reg_rtx);
6918 
6919       /* Some sanity tests to verify that the reloads found in the first
6920 	 pass are identical to the ones we have now.  */
6921       gcc_assert (chain->n_reloads == n_reloads);
6922 
6923       for (i = 0; i < n_reloads; i++)
6924 	{
6925 	  if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6926 	    continue;
6927 	  gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6928 	  for (j = 0; j < n_spills; j++)
6929 	    if (spill_regs[j] == chain->rld[i].regno)
6930 	      if (! set_reload_reg (j, i))
6931 		failed_reload (chain->insn, i);
6932 	}
6933     }
6934 
6935   /* If we thought we could inherit a reload, because it seemed that
6936      nothing else wanted the same reload register earlier in the insn,
6937      verify that assumption, now that all reloads have been assigned.
6938      Likewise for reloads where reload_override_in has been set.  */
6939 
6940   /* If doing expensive optimizations, do one preliminary pass that doesn't
6941      cancel any inheritance, but removes reloads that have been needed only
6942      for reloads that we know can be inherited.  */
6943   for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6944     {
6945       for (j = 0; j < n_reloads; j++)
6946 	{
6947 	  int r = reload_order[j];
6948 	  rtx check_reg;
6949 	  if (reload_inherited[r] && rld[r].reg_rtx)
6950 	    check_reg = rld[r].reg_rtx;
6951 	  else if (reload_override_in[r]
6952 		   && (REG_P (reload_override_in[r])
6953 		       || GET_CODE (reload_override_in[r]) == SUBREG))
6954 	    check_reg = reload_override_in[r];
6955 	  else
6956 	    continue;
6957 	  if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6958 				  rld[r].opnum, rld[r].when_needed, rld[r].in,
6959 				  (reload_inherited[r]
6960 				   ? rld[r].out : const0_rtx),
6961 				  r, 1))
6962 	    {
6963 	      if (pass)
6964 		continue;
6965 	      reload_inherited[r] = 0;
6966 	      reload_override_in[r] = 0;
6967 	    }
6968 	  /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6969 	     reload_override_in, then we do not need its related
6970 	     RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6971 	     likewise for other reload types.
6972 	     We handle this by removing a reload when its only replacement
6973 	     is mentioned in reload_in of the reload we are going to inherit.
6974 	     A special case are auto_inc expressions; even if the input is
6975 	     inherited, we still need the address for the output.  We can
6976 	     recognize them because they have RELOAD_OUT set to RELOAD_IN.
6977 	     If we succeeded removing some reload and we are doing a preliminary
6978 	     pass just to remove such reloads, make another pass, since the
6979 	     removal of one reload might allow us to inherit another one.  */
6980 	  else if (rld[r].in
6981 		   && rld[r].out != rld[r].in
6982 		   && remove_address_replacements (rld[r].in) && pass)
6983 	    pass = 2;
6984 	}
6985     }
6986 
6987   /* Now that reload_override_in is known valid,
6988      actually override reload_in.  */
6989   for (j = 0; j < n_reloads; j++)
6990     if (reload_override_in[j])
6991       rld[j].in = reload_override_in[j];
6992 
6993   /* If this reload won't be done because it has been canceled or is
6994      optional and not inherited, clear reload_reg_rtx so other
6995      routines (such as subst_reloads) don't get confused.  */
6996   for (j = 0; j < n_reloads; j++)
6997     if (rld[j].reg_rtx != 0
6998 	&& ((rld[j].optional && ! reload_inherited[j])
6999 	    || (rld[j].in == 0 && rld[j].out == 0
7000 		&& ! rld[j].secondary_p)))
7001       {
7002 	int regno = true_regnum (rld[j].reg_rtx);
7003 
7004 	if (spill_reg_order[regno] >= 0)
7005 	  clear_reload_reg_in_use (regno, rld[j].opnum,
7006 				   rld[j].when_needed, rld[j].mode);
7007 	rld[j].reg_rtx = 0;
7008 	reload_spill_index[j] = -1;
7009       }
7010 
7011   /* Record which pseudos and which spill regs have output reloads.  */
7012   for (j = 0; j < n_reloads; j++)
7013     {
7014       int r = reload_order[j];
7015 
7016       i = reload_spill_index[r];
7017 
7018       /* I is nonneg if this reload uses a register.
7019 	 If rld[r].reg_rtx is 0, this is an optional reload
7020 	 that we opted to ignore.  */
7021       if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
7022 	  && rld[r].reg_rtx != 0)
7023 	{
7024 	  int nregno = REGNO (rld[r].out_reg);
7025 	  int nr = 1;
7026 
7027 	  if (nregno < FIRST_PSEUDO_REGISTER)
7028 	    nr = hard_regno_nregs[nregno][rld[r].mode];
7029 
7030 	  while (--nr >= 0)
7031 	    SET_REGNO_REG_SET (&reg_has_output_reload,
7032 			       nregno + nr);
7033 
7034 	  if (i >= 0)
7035 	    add_to_hard_reg_set (&reg_is_output_reload, rld[r].mode, i);
7036 
7037 	  gcc_assert (rld[r].when_needed == RELOAD_OTHER
7038 		      || rld[r].when_needed == RELOAD_FOR_OUTPUT
7039 		      || rld[r].when_needed == RELOAD_FOR_INSN);
7040 	}
7041     }
7042 }
7043 
7044 /* Deallocate the reload register for reload R.  This is called from
7045    remove_address_replacements.  */
7046 
7047 void
deallocate_reload_reg(int r)7048 deallocate_reload_reg (int r)
7049 {
7050   int regno;
7051 
7052   if (! rld[r].reg_rtx)
7053     return;
7054   regno = true_regnum (rld[r].reg_rtx);
7055   rld[r].reg_rtx = 0;
7056   if (spill_reg_order[regno] >= 0)
7057     clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
7058 			     rld[r].mode);
7059   reload_spill_index[r] = -1;
7060 }
7061 
7062 /* These arrays are filled by emit_reload_insns and its subroutines.  */
7063 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
7064 static rtx other_input_address_reload_insns = 0;
7065 static rtx other_input_reload_insns = 0;
7066 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
7067 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7068 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
7069 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
7070 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7071 static rtx operand_reload_insns = 0;
7072 static rtx other_operand_reload_insns = 0;
7073 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
7074 
7075 /* Values to be put in spill_reg_store are put here first.  Instructions
7076    must only be placed here if the associated reload register reaches
7077    the end of the instruction's reload sequence.  */
7078 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
7079 static HARD_REG_SET reg_reloaded_died;
7080 
7081 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7082    of class NEW_CLASS with mode NEW_MODE.  Or alternatively, if alt_reload_reg
7083    is nonzero, if that is suitable.  On success, change *RELOAD_REG to the
7084    adjusted register, and return true.  Otherwise, return false.  */
7085 static bool
reload_adjust_reg_for_temp(rtx * reload_reg,rtx alt_reload_reg,enum reg_class new_class,enum machine_mode new_mode)7086 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
7087 			    enum reg_class new_class,
7088 			    enum machine_mode new_mode)
7089 
7090 {
7091   rtx reg;
7092 
7093   for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
7094     {
7095       unsigned regno = REGNO (reg);
7096 
7097       if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
7098 	continue;
7099       if (GET_MODE (reg) != new_mode)
7100 	{
7101 	  if (!HARD_REGNO_MODE_OK (regno, new_mode))
7102 	    continue;
7103 	  if (hard_regno_nregs[regno][new_mode]
7104 	      > hard_regno_nregs[regno][GET_MODE (reg)])
7105 	    continue;
7106 	  reg = reload_adjust_reg_for_mode (reg, new_mode);
7107 	}
7108       *reload_reg = reg;
7109       return true;
7110     }
7111   return false;
7112 }
7113 
7114 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7115    pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7116    nonzero, if that is suitable.  On success, change *RELOAD_REG to the
7117    adjusted register, and return true.  Otherwise, return false.  */
7118 static bool
reload_adjust_reg_for_icode(rtx * reload_reg,rtx alt_reload_reg,enum insn_code icode)7119 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
7120 			     enum insn_code icode)
7121 
7122 {
7123   enum reg_class new_class = scratch_reload_class (icode);
7124   enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
7125 
7126   return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
7127 				     new_class, new_mode);
7128 }
7129 
7130 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7131    has the number J.  OLD contains the value to be used as input.  */
7132 
7133 static void
emit_input_reload_insns(struct insn_chain * chain,struct reload * rl,rtx old,int j)7134 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
7135 			 rtx old, int j)
7136 {
7137   rtx insn = chain->insn;
7138   rtx reloadreg;
7139   rtx oldequiv_reg = 0;
7140   rtx oldequiv = 0;
7141   int special = 0;
7142   enum machine_mode mode;
7143   rtx *where;
7144 
7145   /* delete_output_reload is only invoked properly if old contains
7146      the original pseudo register.  Since this is replaced with a
7147      hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7148      find the pseudo in RELOAD_IN_REG.  */
7149   if (reload_override_in[j]
7150       && REG_P (rl->in_reg))
7151     {
7152       oldequiv = old;
7153       old = rl->in_reg;
7154     }
7155   if (oldequiv == 0)
7156     oldequiv = old;
7157   else if (REG_P (oldequiv))
7158     oldequiv_reg = oldequiv;
7159   else if (GET_CODE (oldequiv) == SUBREG)
7160     oldequiv_reg = SUBREG_REG (oldequiv);
7161 
7162   reloadreg = reload_reg_rtx_for_input[j];
7163   mode = GET_MODE (reloadreg);
7164 
7165   /* If we are reloading from a register that was recently stored in
7166      with an output-reload, see if we can prove there was
7167      actually no need to store the old value in it.  */
7168 
7169   if (optimize && REG_P (oldequiv)
7170       && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
7171       && spill_reg_store[REGNO (oldequiv)]
7172       && REG_P (old)
7173       && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
7174 	  || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
7175 			  rl->out_reg)))
7176     delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
7177 
7178   /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7179      OLDEQUIV.  */
7180 
7181   while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
7182     oldequiv = SUBREG_REG (oldequiv);
7183   if (GET_MODE (oldequiv) != VOIDmode
7184       && mode != GET_MODE (oldequiv))
7185     oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
7186 
7187   /* Switch to the right place to emit the reload insns.  */
7188   switch (rl->when_needed)
7189     {
7190     case RELOAD_OTHER:
7191       where = &other_input_reload_insns;
7192       break;
7193     case RELOAD_FOR_INPUT:
7194       where = &input_reload_insns[rl->opnum];
7195       break;
7196     case RELOAD_FOR_INPUT_ADDRESS:
7197       where = &input_address_reload_insns[rl->opnum];
7198       break;
7199     case RELOAD_FOR_INPADDR_ADDRESS:
7200       where = &inpaddr_address_reload_insns[rl->opnum];
7201       break;
7202     case RELOAD_FOR_OUTPUT_ADDRESS:
7203       where = &output_address_reload_insns[rl->opnum];
7204       break;
7205     case RELOAD_FOR_OUTADDR_ADDRESS:
7206       where = &outaddr_address_reload_insns[rl->opnum];
7207       break;
7208     case RELOAD_FOR_OPERAND_ADDRESS:
7209       where = &operand_reload_insns;
7210       break;
7211     case RELOAD_FOR_OPADDR_ADDR:
7212       where = &other_operand_reload_insns;
7213       break;
7214     case RELOAD_FOR_OTHER_ADDRESS:
7215       where = &other_input_address_reload_insns;
7216       break;
7217     default:
7218       gcc_unreachable ();
7219     }
7220 
7221   push_to_sequence (*where);
7222 
7223   /* Auto-increment addresses must be reloaded in a special way.  */
7224   if (rl->out && ! rl->out_reg)
7225     {
7226       /* We are not going to bother supporting the case where a
7227 	 incremented register can't be copied directly from
7228 	 OLDEQUIV since this seems highly unlikely.  */
7229       gcc_assert (rl->secondary_in_reload < 0);
7230 
7231       if (reload_inherited[j])
7232 	oldequiv = reloadreg;
7233 
7234       old = XEXP (rl->in_reg, 0);
7235 
7236       /* Prevent normal processing of this reload.  */
7237       special = 1;
7238       /* Output a special code sequence for this case.  */
7239       inc_for_reload (reloadreg, oldequiv, rl->out, rl->inc);
7240     }
7241 
7242   /* If we are reloading a pseudo-register that was set by the previous
7243      insn, see if we can get rid of that pseudo-register entirely
7244      by redirecting the previous insn into our reload register.  */
7245 
7246   else if (optimize && REG_P (old)
7247 	   && REGNO (old) >= FIRST_PSEUDO_REGISTER
7248 	   && dead_or_set_p (insn, old)
7249 	   /* This is unsafe if some other reload
7250 	      uses the same reg first.  */
7251 	   && ! conflicts_with_override (reloadreg)
7252 	   && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
7253 				rl->when_needed, old, rl->out, j, 0))
7254     {
7255       rtx temp = PREV_INSN (insn);
7256       while (temp && (NOTE_P (temp) || DEBUG_INSN_P (temp)))
7257 	temp = PREV_INSN (temp);
7258       if (temp
7259 	  && NONJUMP_INSN_P (temp)
7260 	  && GET_CODE (PATTERN (temp)) == SET
7261 	  && SET_DEST (PATTERN (temp)) == old
7262 	  /* Make sure we can access insn_operand_constraint.  */
7263 	  && asm_noperands (PATTERN (temp)) < 0
7264 	  /* This is unsafe if operand occurs more than once in current
7265 	     insn.  Perhaps some occurrences aren't reloaded.  */
7266 	  && count_occurrences (PATTERN (insn), old, 0) == 1)
7267 	{
7268 	  rtx old = SET_DEST (PATTERN (temp));
7269 	  /* Store into the reload register instead of the pseudo.  */
7270 	  SET_DEST (PATTERN (temp)) = reloadreg;
7271 
7272 	  /* Verify that resulting insn is valid.  */
7273 	  extract_insn (temp);
7274 	  if (constrain_operands (1))
7275 	    {
7276 	      /* If the previous insn is an output reload, the source is
7277 		 a reload register, and its spill_reg_store entry will
7278 		 contain the previous destination.  This is now
7279 		 invalid.  */
7280 	      if (REG_P (SET_SRC (PATTERN (temp)))
7281 		  && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
7282 		{
7283 		  spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7284 		  spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7285 		}
7286 
7287 	      /* If these are the only uses of the pseudo reg,
7288 		 pretend for GDB it lives in the reload reg we used.  */
7289 	      if (REG_N_DEATHS (REGNO (old)) == 1
7290 		  && REG_N_SETS (REGNO (old)) == 1)
7291 		{
7292 		  reg_renumber[REGNO (old)] = REGNO (reloadreg);
7293 		  if (ira_conflicts_p)
7294 		    /* Inform IRA about the change.  */
7295 		    ira_mark_allocation_change (REGNO (old));
7296 		  alter_reg (REGNO (old), -1, false);
7297 		}
7298 	      special = 1;
7299 
7300 	      /* Adjust any debug insns between temp and insn.  */
7301 	      while ((temp = NEXT_INSN (temp)) != insn)
7302 		if (DEBUG_INSN_P (temp))
7303 		  replace_rtx (PATTERN (temp), old, reloadreg);
7304 		else
7305 		  gcc_assert (NOTE_P (temp));
7306 	    }
7307 	  else
7308 	    {
7309 	      SET_DEST (PATTERN (temp)) = old;
7310 	    }
7311 	}
7312     }
7313 
7314   /* We can't do that, so output an insn to load RELOADREG.  */
7315 
7316   /* If we have a secondary reload, pick up the secondary register
7317      and icode, if any.  If OLDEQUIV and OLD are different or
7318      if this is an in-out reload, recompute whether or not we
7319      still need a secondary register and what the icode should
7320      be.  If we still need a secondary register and the class or
7321      icode is different, go back to reloading from OLD if using
7322      OLDEQUIV means that we got the wrong type of register.  We
7323      cannot have different class or icode due to an in-out reload
7324      because we don't make such reloads when both the input and
7325      output need secondary reload registers.  */
7326 
7327   if (! special && rl->secondary_in_reload >= 0)
7328     {
7329       rtx second_reload_reg = 0;
7330       rtx third_reload_reg = 0;
7331       int secondary_reload = rl->secondary_in_reload;
7332       rtx real_oldequiv = oldequiv;
7333       rtx real_old = old;
7334       rtx tmp;
7335       enum insn_code icode;
7336       enum insn_code tertiary_icode = CODE_FOR_nothing;
7337 
7338       /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7339 	 and similarly for OLD.
7340 	 See comments in get_secondary_reload in reload.c.  */
7341       /* If it is a pseudo that cannot be replaced with its
7342 	 equivalent MEM, we must fall back to reload_in, which
7343 	 will have all the necessary substitutions registered.
7344 	 Likewise for a pseudo that can't be replaced with its
7345 	 equivalent constant.
7346 
7347 	 Take extra care for subregs of such pseudos.  Note that
7348 	 we cannot use reg_equiv_mem in this case because it is
7349 	 not in the right mode.  */
7350 
7351       tmp = oldequiv;
7352       if (GET_CODE (tmp) == SUBREG)
7353 	tmp = SUBREG_REG (tmp);
7354       if (REG_P (tmp)
7355 	  && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7356 	  && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7357 	      || reg_equiv_constant (REGNO (tmp)) != 0))
7358 	{
7359 	  if (! reg_equiv_mem (REGNO (tmp))
7360 	      || num_not_at_initial_offset
7361 	      || GET_CODE (oldequiv) == SUBREG)
7362 	    real_oldequiv = rl->in;
7363 	  else
7364 	    real_oldequiv = reg_equiv_mem (REGNO (tmp));
7365 	}
7366 
7367       tmp = old;
7368       if (GET_CODE (tmp) == SUBREG)
7369 	tmp = SUBREG_REG (tmp);
7370       if (REG_P (tmp)
7371 	  && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7372 	  && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7373 	      || reg_equiv_constant (REGNO (tmp)) != 0))
7374 	{
7375 	  if (! reg_equiv_mem (REGNO (tmp))
7376 	      || num_not_at_initial_offset
7377 	      || GET_CODE (old) == SUBREG)
7378 	    real_old = rl->in;
7379 	  else
7380 	    real_old = reg_equiv_mem (REGNO (tmp));
7381 	}
7382 
7383       second_reload_reg = rld[secondary_reload].reg_rtx;
7384       if (rld[secondary_reload].secondary_in_reload >= 0)
7385 	{
7386 	  int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7387 
7388 	  third_reload_reg = rld[tertiary_reload].reg_rtx;
7389 	  tertiary_icode = rld[secondary_reload].secondary_in_icode;
7390 	  /* We'd have to add more code for quartary reloads.  */
7391 	  gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7392 	}
7393       icode = rl->secondary_in_icode;
7394 
7395       if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7396 	  || (rl->in != 0 && rl->out != 0))
7397 	{
7398 	  secondary_reload_info sri, sri2;
7399 	  enum reg_class new_class, new_t_class;
7400 
7401 	  sri.icode = CODE_FOR_nothing;
7402 	  sri.prev_sri = NULL;
7403 	  new_class
7404 	    = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7405 							 rl->rclass, mode,
7406 							 &sri);
7407 
7408 	  if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7409 	    second_reload_reg = 0;
7410 	  else if (new_class == NO_REGS)
7411 	    {
7412 	      if (reload_adjust_reg_for_icode (&second_reload_reg,
7413 					       third_reload_reg,
7414 					       (enum insn_code) sri.icode))
7415 		{
7416 		  icode = (enum insn_code) sri.icode;
7417 		  third_reload_reg = 0;
7418 		}
7419 	      else
7420 		{
7421 		  oldequiv = old;
7422 		  real_oldequiv = real_old;
7423 		}
7424 	    }
7425 	  else if (sri.icode != CODE_FOR_nothing)
7426 	    /* We currently lack a way to express this in reloads.  */
7427 	    gcc_unreachable ();
7428 	  else
7429 	    {
7430 	      sri2.icode = CODE_FOR_nothing;
7431 	      sri2.prev_sri = &sri;
7432 	      new_t_class
7433 		= (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7434 							     new_class, mode,
7435 							     &sri);
7436 	      if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7437 		{
7438 		  if (reload_adjust_reg_for_temp (&second_reload_reg,
7439 						  third_reload_reg,
7440 						  new_class, mode))
7441 		    {
7442 		      third_reload_reg = 0;
7443 		      tertiary_icode = (enum insn_code) sri2.icode;
7444 		    }
7445 		  else
7446 		    {
7447 		      oldequiv = old;
7448 		      real_oldequiv = real_old;
7449 		    }
7450 		}
7451 	      else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7452 		{
7453 		  rtx intermediate = second_reload_reg;
7454 
7455 		  if (reload_adjust_reg_for_temp (&intermediate, NULL,
7456 						  new_class, mode)
7457 		      && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7458 						      ((enum insn_code)
7459 						       sri2.icode)))
7460 		    {
7461 		      second_reload_reg = intermediate;
7462 		      tertiary_icode = (enum insn_code) sri2.icode;
7463 		    }
7464 		  else
7465 		    {
7466 		      oldequiv = old;
7467 		      real_oldequiv = real_old;
7468 		    }
7469 		}
7470 	      else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7471 		{
7472 		  rtx intermediate = second_reload_reg;
7473 
7474 		  if (reload_adjust_reg_for_temp (&intermediate, NULL,
7475 						  new_class, mode)
7476 		      && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7477 						      new_t_class, mode))
7478 		    {
7479 		      second_reload_reg = intermediate;
7480 		      tertiary_icode = (enum insn_code) sri2.icode;
7481 		    }
7482 		  else
7483 		    {
7484 		      oldequiv = old;
7485 		      real_oldequiv = real_old;
7486 		    }
7487 		}
7488 	      else
7489 		{
7490 		  /* This could be handled more intelligently too.  */
7491 		  oldequiv = old;
7492 		  real_oldequiv = real_old;
7493 		}
7494 	    }
7495 	}
7496 
7497       /* If we still need a secondary reload register, check
7498 	 to see if it is being used as a scratch or intermediate
7499 	 register and generate code appropriately.  If we need
7500 	 a scratch register, use REAL_OLDEQUIV since the form of
7501 	 the insn may depend on the actual address if it is
7502 	 a MEM.  */
7503 
7504       if (second_reload_reg)
7505 	{
7506 	  if (icode != CODE_FOR_nothing)
7507 	    {
7508 	      /* We'd have to add extra code to handle this case.  */
7509 	      gcc_assert (!third_reload_reg);
7510 
7511 	      emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7512 					  second_reload_reg));
7513 	      special = 1;
7514 	    }
7515 	  else
7516 	    {
7517 	      /* See if we need a scratch register to load the
7518 		 intermediate register (a tertiary reload).  */
7519 	      if (tertiary_icode != CODE_FOR_nothing)
7520 		{
7521 		  emit_insn ((GEN_FCN (tertiary_icode)
7522 			      (second_reload_reg, real_oldequiv,
7523 			       third_reload_reg)));
7524 		}
7525 	      else if (third_reload_reg)
7526 		{
7527 		  gen_reload (third_reload_reg, real_oldequiv,
7528 			      rl->opnum,
7529 			      rl->when_needed);
7530 		  gen_reload (second_reload_reg, third_reload_reg,
7531 			      rl->opnum,
7532 			      rl->when_needed);
7533 		}
7534 	      else
7535 		gen_reload (second_reload_reg, real_oldequiv,
7536 			    rl->opnum,
7537 			    rl->when_needed);
7538 
7539 	      oldequiv = second_reload_reg;
7540 	    }
7541 	}
7542     }
7543 
7544   if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7545     {
7546       rtx real_oldequiv = oldequiv;
7547 
7548       if ((REG_P (oldequiv)
7549 	   && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7550 	   && (reg_equiv_memory_loc (REGNO (oldequiv)) != 0
7551 	       || reg_equiv_constant (REGNO (oldequiv)) != 0))
7552 	  || (GET_CODE (oldequiv) == SUBREG
7553 	      && REG_P (SUBREG_REG (oldequiv))
7554 	      && (REGNO (SUBREG_REG (oldequiv))
7555 		  >= FIRST_PSEUDO_REGISTER)
7556 	      && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv))) != 0)
7557 		  || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv))) != 0)))
7558 	  || (CONSTANT_P (oldequiv)
7559 	      && (targetm.preferred_reload_class (oldequiv,
7560 						  REGNO_REG_CLASS (REGNO (reloadreg)))
7561 		  == NO_REGS)))
7562 	real_oldequiv = rl->in;
7563       gen_reload (reloadreg, real_oldequiv, rl->opnum,
7564 		  rl->when_needed);
7565     }
7566 
7567   if (cfun->can_throw_non_call_exceptions)
7568     copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7569 
7570   /* End this sequence.  */
7571   *where = get_insns ();
7572   end_sequence ();
7573 
7574   /* Update reload_override_in so that delete_address_reloads_1
7575      can see the actual register usage.  */
7576   if (oldequiv_reg)
7577     reload_override_in[j] = oldequiv;
7578 }
7579 
7580 /* Generate insns to for the output reload RL, which is for the insn described
7581    by CHAIN and has the number J.  */
7582 static void
emit_output_reload_insns(struct insn_chain * chain,struct reload * rl,int j)7583 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7584 			  int j)
7585 {
7586   rtx reloadreg;
7587   rtx insn = chain->insn;
7588   int special = 0;
7589   rtx old = rl->out;
7590   enum machine_mode mode;
7591   rtx p;
7592   rtx rl_reg_rtx;
7593 
7594   if (rl->when_needed == RELOAD_OTHER)
7595     start_sequence ();
7596   else
7597     push_to_sequence (output_reload_insns[rl->opnum]);
7598 
7599   rl_reg_rtx = reload_reg_rtx_for_output[j];
7600   mode = GET_MODE (rl_reg_rtx);
7601 
7602   reloadreg = rl_reg_rtx;
7603 
7604   /* If we need two reload regs, set RELOADREG to the intermediate
7605      one, since it will be stored into OLD.  We might need a secondary
7606      register only for an input reload, so check again here.  */
7607 
7608   if (rl->secondary_out_reload >= 0)
7609     {
7610       rtx real_old = old;
7611       int secondary_reload = rl->secondary_out_reload;
7612       int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7613 
7614       if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7615 	  && reg_equiv_mem (REGNO (old)) != 0)
7616 	real_old = reg_equiv_mem (REGNO (old));
7617 
7618       if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7619 	{
7620 	  rtx second_reloadreg = reloadreg;
7621 	  reloadreg = rld[secondary_reload].reg_rtx;
7622 
7623 	  /* See if RELOADREG is to be used as a scratch register
7624 	     or as an intermediate register.  */
7625 	  if (rl->secondary_out_icode != CODE_FOR_nothing)
7626 	    {
7627 	      /* We'd have to add extra code to handle this case.  */
7628 	      gcc_assert (tertiary_reload < 0);
7629 
7630 	      emit_insn ((GEN_FCN (rl->secondary_out_icode)
7631 			  (real_old, second_reloadreg, reloadreg)));
7632 	      special = 1;
7633 	    }
7634 	  else
7635 	    {
7636 	      /* See if we need both a scratch and intermediate reload
7637 		 register.  */
7638 
7639 	      enum insn_code tertiary_icode
7640 		= rld[secondary_reload].secondary_out_icode;
7641 
7642 	      /* We'd have to add more code for quartary reloads.  */
7643 	      gcc_assert (tertiary_reload < 0
7644 			  || rld[tertiary_reload].secondary_out_reload < 0);
7645 
7646 	      if (GET_MODE (reloadreg) != mode)
7647 		reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7648 
7649 	      if (tertiary_icode != CODE_FOR_nothing)
7650 		{
7651 		  rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7652 
7653 		  /* Copy primary reload reg to secondary reload reg.
7654 		     (Note that these have been swapped above, then
7655 		     secondary reload reg to OLD using our insn.)  */
7656 
7657 		  /* If REAL_OLD is a paradoxical SUBREG, remove it
7658 		     and try to put the opposite SUBREG on
7659 		     RELOADREG.  */
7660 		  strip_paradoxical_subreg (&real_old, &reloadreg);
7661 
7662 		  gen_reload (reloadreg, second_reloadreg,
7663 			      rl->opnum, rl->when_needed);
7664 		  emit_insn ((GEN_FCN (tertiary_icode)
7665 			      (real_old, reloadreg, third_reloadreg)));
7666 		  special = 1;
7667 		}
7668 
7669 	      else
7670 		{
7671 		  /* Copy between the reload regs here and then to
7672 		     OUT later.  */
7673 
7674 		  gen_reload (reloadreg, second_reloadreg,
7675 			      rl->opnum, rl->when_needed);
7676 		  if (tertiary_reload >= 0)
7677 		    {
7678 		      rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7679 
7680 		      gen_reload (third_reloadreg, reloadreg,
7681 				  rl->opnum, rl->when_needed);
7682 		      reloadreg = third_reloadreg;
7683 		    }
7684 		}
7685 	    }
7686 	}
7687     }
7688 
7689   /* Output the last reload insn.  */
7690   if (! special)
7691     {
7692       rtx set;
7693 
7694       /* Don't output the last reload if OLD is not the dest of
7695 	 INSN and is in the src and is clobbered by INSN.  */
7696       if (! flag_expensive_optimizations
7697 	  || !REG_P (old)
7698 	  || !(set = single_set (insn))
7699 	  || rtx_equal_p (old, SET_DEST (set))
7700 	  || !reg_mentioned_p (old, SET_SRC (set))
7701 	  || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7702 	       && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7703 	gen_reload (old, reloadreg, rl->opnum,
7704 		    rl->when_needed);
7705     }
7706 
7707   /* Look at all insns we emitted, just to be safe.  */
7708   for (p = get_insns (); p; p = NEXT_INSN (p))
7709     if (INSN_P (p))
7710       {
7711 	rtx pat = PATTERN (p);
7712 
7713 	/* If this output reload doesn't come from a spill reg,
7714 	   clear any memory of reloaded copies of the pseudo reg.
7715 	   If this output reload comes from a spill reg,
7716 	   reg_has_output_reload will make this do nothing.  */
7717 	note_stores (pat, forget_old_reloads_1, NULL);
7718 
7719 	if (reg_mentioned_p (rl_reg_rtx, pat))
7720 	  {
7721 	    rtx set = single_set (insn);
7722 	    if (reload_spill_index[j] < 0
7723 		&& set
7724 		&& SET_SRC (set) == rl_reg_rtx)
7725 	      {
7726 		int src = REGNO (SET_SRC (set));
7727 
7728 		reload_spill_index[j] = src;
7729 		SET_HARD_REG_BIT (reg_is_output_reload, src);
7730 		if (find_regno_note (insn, REG_DEAD, src))
7731 		  SET_HARD_REG_BIT (reg_reloaded_died, src);
7732 	      }
7733 	    if (HARD_REGISTER_P (rl_reg_rtx))
7734 	      {
7735 		int s = rl->secondary_out_reload;
7736 		set = single_set (p);
7737 		/* If this reload copies only to the secondary reload
7738 		   register, the secondary reload does the actual
7739 		   store.  */
7740 		if (s >= 0 && set == NULL_RTX)
7741 		  /* We can't tell what function the secondary reload
7742 		     has and where the actual store to the pseudo is
7743 		     made; leave new_spill_reg_store alone.  */
7744 		  ;
7745 		else if (s >= 0
7746 			 && SET_SRC (set) == rl_reg_rtx
7747 			 && SET_DEST (set) == rld[s].reg_rtx)
7748 		  {
7749 		    /* Usually the next instruction will be the
7750 		       secondary reload insn;  if we can confirm
7751 		       that it is, setting new_spill_reg_store to
7752 		       that insn will allow an extra optimization.  */
7753 		    rtx s_reg = rld[s].reg_rtx;
7754 		    rtx next = NEXT_INSN (p);
7755 		    rld[s].out = rl->out;
7756 		    rld[s].out_reg = rl->out_reg;
7757 		    set = single_set (next);
7758 		    if (set && SET_SRC (set) == s_reg
7759 			&& reload_reg_rtx_reaches_end_p (s_reg, s))
7760 		      {
7761 			SET_HARD_REG_BIT (reg_is_output_reload,
7762 					  REGNO (s_reg));
7763 			new_spill_reg_store[REGNO (s_reg)] = next;
7764 		      }
7765 		  }
7766 		else if (reload_reg_rtx_reaches_end_p (rl_reg_rtx, j))
7767 		  new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7768 	      }
7769 	  }
7770       }
7771 
7772   if (rl->when_needed == RELOAD_OTHER)
7773     {
7774       emit_insn (other_output_reload_insns[rl->opnum]);
7775       other_output_reload_insns[rl->opnum] = get_insns ();
7776     }
7777   else
7778     output_reload_insns[rl->opnum] = get_insns ();
7779 
7780   if (cfun->can_throw_non_call_exceptions)
7781     copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7782 
7783   end_sequence ();
7784 }
7785 
7786 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7787    and has the number J.  */
7788 static void
do_input_reload(struct insn_chain * chain,struct reload * rl,int j)7789 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7790 {
7791   rtx insn = chain->insn;
7792   rtx old = (rl->in && MEM_P (rl->in)
7793 	     ? rl->in_reg : rl->in);
7794   rtx reg_rtx = rl->reg_rtx;
7795 
7796   if (old && reg_rtx)
7797     {
7798       enum machine_mode mode;
7799 
7800       /* Determine the mode to reload in.
7801 	 This is very tricky because we have three to choose from.
7802 	 There is the mode the insn operand wants (rl->inmode).
7803 	 There is the mode of the reload register RELOADREG.
7804 	 There is the intrinsic mode of the operand, which we could find
7805 	 by stripping some SUBREGs.
7806 	 It turns out that RELOADREG's mode is irrelevant:
7807 	 we can change that arbitrarily.
7808 
7809 	 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7810 	 then the reload reg may not support QImode moves, so use SImode.
7811 	 If foo is in memory due to spilling a pseudo reg, this is safe,
7812 	 because the QImode value is in the least significant part of a
7813 	 slot big enough for a SImode.  If foo is some other sort of
7814 	 memory reference, then it is impossible to reload this case,
7815 	 so previous passes had better make sure this never happens.
7816 
7817 	 Then consider a one-word union which has SImode and one of its
7818 	 members is a float, being fetched as (SUBREG:SF union:SI).
7819 	 We must fetch that as SFmode because we could be loading into
7820 	 a float-only register.  In this case OLD's mode is correct.
7821 
7822 	 Consider an immediate integer: it has VOIDmode.  Here we need
7823 	 to get a mode from something else.
7824 
7825 	 In some cases, there is a fourth mode, the operand's
7826 	 containing mode.  If the insn specifies a containing mode for
7827 	 this operand, it overrides all others.
7828 
7829 	 I am not sure whether the algorithm here is always right,
7830 	 but it does the right things in those cases.  */
7831 
7832       mode = GET_MODE (old);
7833       if (mode == VOIDmode)
7834 	mode = rl->inmode;
7835 
7836       /* We cannot use gen_lowpart_common since it can do the wrong thing
7837 	 when REG_RTX has a multi-word mode.  Note that REG_RTX must
7838 	 always be a REG here.  */
7839       if (GET_MODE (reg_rtx) != mode)
7840 	reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7841     }
7842   reload_reg_rtx_for_input[j] = reg_rtx;
7843 
7844   if (old != 0
7845       /* AUTO_INC reloads need to be handled even if inherited.  We got an
7846 	 AUTO_INC reload if reload_out is set but reload_out_reg isn't.  */
7847       && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7848       && ! rtx_equal_p (reg_rtx, old)
7849       && reg_rtx != 0)
7850     emit_input_reload_insns (chain, rld + j, old, j);
7851 
7852   /* When inheriting a wider reload, we have a MEM in rl->in,
7853      e.g. inheriting a SImode output reload for
7854      (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10)))  */
7855   if (optimize && reload_inherited[j] && rl->in
7856       && MEM_P (rl->in)
7857       && MEM_P (rl->in_reg)
7858       && reload_spill_index[j] >= 0
7859       && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7860     rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7861 
7862   /* If we are reloading a register that was recently stored in with an
7863      output-reload, see if we can prove there was
7864      actually no need to store the old value in it.  */
7865 
7866   if (optimize
7867       && (reload_inherited[j] || reload_override_in[j])
7868       && reg_rtx
7869       && REG_P (reg_rtx)
7870       && spill_reg_store[REGNO (reg_rtx)] != 0
7871 #if 0
7872       /* There doesn't seem to be any reason to restrict this to pseudos
7873 	 and doing so loses in the case where we are copying from a
7874 	 register of the wrong class.  */
7875       && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7876 #endif
7877       /* The insn might have already some references to stackslots
7878 	 replaced by MEMs, while reload_out_reg still names the
7879 	 original pseudo.  */
7880       && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7881 	  || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7882     delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7883 }
7884 
7885 /* Do output reloading for reload RL, which is for the insn described by
7886    CHAIN and has the number J.
7887    ??? At some point we need to support handling output reloads of
7888    JUMP_INSNs or insns that set cc0.  */
7889 static void
do_output_reload(struct insn_chain * chain,struct reload * rl,int j)7890 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7891 {
7892   rtx note, old;
7893   rtx insn = chain->insn;
7894   /* If this is an output reload that stores something that is
7895      not loaded in this same reload, see if we can eliminate a previous
7896      store.  */
7897   rtx pseudo = rl->out_reg;
7898   rtx reg_rtx = rl->reg_rtx;
7899 
7900   if (rl->out && reg_rtx)
7901     {
7902       enum machine_mode mode;
7903 
7904       /* Determine the mode to reload in.
7905 	 See comments above (for input reloading).  */
7906       mode = GET_MODE (rl->out);
7907       if (mode == VOIDmode)
7908 	{
7909 	  /* VOIDmode should never happen for an output.  */
7910 	  if (asm_noperands (PATTERN (insn)) < 0)
7911 	    /* It's the compiler's fault.  */
7912 	    fatal_insn ("VOIDmode on an output", insn);
7913 	  error_for_asm (insn, "output operand is constant in %<asm%>");
7914 	  /* Prevent crash--use something we know is valid.  */
7915 	  mode = word_mode;
7916 	  rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7917 	}
7918       if (GET_MODE (reg_rtx) != mode)
7919 	reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7920     }
7921   reload_reg_rtx_for_output[j] = reg_rtx;
7922 
7923   if (pseudo
7924       && optimize
7925       && REG_P (pseudo)
7926       && ! rtx_equal_p (rl->in_reg, pseudo)
7927       && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7928       && reg_last_reload_reg[REGNO (pseudo)])
7929     {
7930       int pseudo_no = REGNO (pseudo);
7931       int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7932 
7933       /* We don't need to test full validity of last_regno for
7934 	 inherit here; we only want to know if the store actually
7935 	 matches the pseudo.  */
7936       if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7937 	  && reg_reloaded_contents[last_regno] == pseudo_no
7938 	  && spill_reg_store[last_regno]
7939 	  && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7940 	delete_output_reload (insn, j, last_regno, reg_rtx);
7941     }
7942 
7943   old = rl->out_reg;
7944   if (old == 0
7945       || reg_rtx == 0
7946       || rtx_equal_p (old, reg_rtx))
7947     return;
7948 
7949   /* An output operand that dies right away does need a reload,
7950      but need not be copied from it.  Show the new location in the
7951      REG_UNUSED note.  */
7952   if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7953       && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7954     {
7955       XEXP (note, 0) = reg_rtx;
7956       return;
7957     }
7958   /* Likewise for a SUBREG of an operand that dies.  */
7959   else if (GET_CODE (old) == SUBREG
7960 	   && REG_P (SUBREG_REG (old))
7961 	   && 0 != (note = find_reg_note (insn, REG_UNUSED,
7962 					  SUBREG_REG (old))))
7963     {
7964       XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7965       return;
7966     }
7967   else if (GET_CODE (old) == SCRATCH)
7968     /* If we aren't optimizing, there won't be a REG_UNUSED note,
7969        but we don't want to make an output reload.  */
7970     return;
7971 
7972   /* If is a JUMP_INSN, we can't support output reloads yet.  */
7973   gcc_assert (NONJUMP_INSN_P (insn));
7974 
7975   emit_output_reload_insns (chain, rld + j, j);
7976 }
7977 
7978 /* A reload copies values of MODE from register SRC to register DEST.
7979    Return true if it can be treated for inheritance purposes like a
7980    group of reloads, each one reloading a single hard register.  The
7981    caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7982    occupy the same number of hard registers.  */
7983 
7984 static bool
inherit_piecemeal_p(int dest ATTRIBUTE_UNUSED,int src ATTRIBUTE_UNUSED,enum machine_mode mode ATTRIBUTE_UNUSED)7985 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
7986 		     int src ATTRIBUTE_UNUSED,
7987 		     enum machine_mode mode ATTRIBUTE_UNUSED)
7988 {
7989 #ifdef CANNOT_CHANGE_MODE_CLASS
7990   return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
7991 	  && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
7992 #else
7993   return true;
7994 #endif
7995 }
7996 
7997 /* Output insns to reload values in and out of the chosen reload regs.  */
7998 
7999 static void
emit_reload_insns(struct insn_chain * chain)8000 emit_reload_insns (struct insn_chain *chain)
8001 {
8002   rtx insn = chain->insn;
8003 
8004   int j;
8005 
8006   CLEAR_HARD_REG_SET (reg_reloaded_died);
8007 
8008   for (j = 0; j < reload_n_operands; j++)
8009     input_reload_insns[j] = input_address_reload_insns[j]
8010       = inpaddr_address_reload_insns[j]
8011       = output_reload_insns[j] = output_address_reload_insns[j]
8012       = outaddr_address_reload_insns[j]
8013       = other_output_reload_insns[j] = 0;
8014   other_input_address_reload_insns = 0;
8015   other_input_reload_insns = 0;
8016   operand_reload_insns = 0;
8017   other_operand_reload_insns = 0;
8018 
8019   /* Dump reloads into the dump file.  */
8020   if (dump_file)
8021     {
8022       fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
8023       debug_reload_to_stream (dump_file);
8024     }
8025 
8026   for (j = 0; j < n_reloads; j++)
8027     if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
8028       {
8029 	unsigned int i;
8030 
8031 	for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
8032 	  new_spill_reg_store[i] = 0;
8033       }
8034 
8035   /* Now output the instructions to copy the data into and out of the
8036      reload registers.  Do these in the order that the reloads were reported,
8037      since reloads of base and index registers precede reloads of operands
8038      and the operands may need the base and index registers reloaded.  */
8039 
8040   for (j = 0; j < n_reloads; j++)
8041     {
8042       do_input_reload (chain, rld + j, j);
8043       do_output_reload (chain, rld + j, j);
8044     }
8045 
8046   /* Now write all the insns we made for reloads in the order expected by
8047      the allocation functions.  Prior to the insn being reloaded, we write
8048      the following reloads:
8049 
8050      RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8051 
8052      RELOAD_OTHER reloads.
8053 
8054      For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8055      by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8056      RELOAD_FOR_INPUT reload for the operand.
8057 
8058      RELOAD_FOR_OPADDR_ADDRS reloads.
8059 
8060      RELOAD_FOR_OPERAND_ADDRESS reloads.
8061 
8062      After the insn being reloaded, we write the following:
8063 
8064      For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8065      by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8066      RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8067      reloads for the operand.  The RELOAD_OTHER output reloads are
8068      output in descending order by reload number.  */
8069 
8070   emit_insn_before (other_input_address_reload_insns, insn);
8071   emit_insn_before (other_input_reload_insns, insn);
8072 
8073   for (j = 0; j < reload_n_operands; j++)
8074     {
8075       emit_insn_before (inpaddr_address_reload_insns[j], insn);
8076       emit_insn_before (input_address_reload_insns[j], insn);
8077       emit_insn_before (input_reload_insns[j], insn);
8078     }
8079 
8080   emit_insn_before (other_operand_reload_insns, insn);
8081   emit_insn_before (operand_reload_insns, insn);
8082 
8083   for (j = 0; j < reload_n_operands; j++)
8084     {
8085       rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
8086       x = emit_insn_after (output_address_reload_insns[j], x);
8087       x = emit_insn_after (output_reload_insns[j], x);
8088       emit_insn_after (other_output_reload_insns[j], x);
8089     }
8090 
8091   /* For all the spill regs newly reloaded in this instruction,
8092      record what they were reloaded from, so subsequent instructions
8093      can inherit the reloads.
8094 
8095      Update spill_reg_store for the reloads of this insn.
8096      Copy the elements that were updated in the loop above.  */
8097 
8098   for (j = 0; j < n_reloads; j++)
8099     {
8100       int r = reload_order[j];
8101       int i = reload_spill_index[r];
8102 
8103       /* If this is a non-inherited input reload from a pseudo, we must
8104 	 clear any memory of a previous store to the same pseudo.  Only do
8105 	 something if there will not be an output reload for the pseudo
8106 	 being reloaded.  */
8107       if (rld[r].in_reg != 0
8108 	  && ! (reload_inherited[r] || reload_override_in[r]))
8109 	{
8110 	  rtx reg = rld[r].in_reg;
8111 
8112 	  if (GET_CODE (reg) == SUBREG)
8113 	    reg = SUBREG_REG (reg);
8114 
8115 	  if (REG_P (reg)
8116 	      && REGNO (reg) >= FIRST_PSEUDO_REGISTER
8117 	      && !REGNO_REG_SET_P (&reg_has_output_reload, REGNO (reg)))
8118 	    {
8119 	      int nregno = REGNO (reg);
8120 
8121 	      if (reg_last_reload_reg[nregno])
8122 		{
8123 		  int last_regno = REGNO (reg_last_reload_reg[nregno]);
8124 
8125 		  if (reg_reloaded_contents[last_regno] == nregno)
8126 		    spill_reg_store[last_regno] = 0;
8127 		}
8128 	    }
8129 	}
8130 
8131       /* I is nonneg if this reload used a register.
8132 	 If rld[r].reg_rtx is 0, this is an optional reload
8133 	 that we opted to ignore.  */
8134 
8135       if (i >= 0 && rld[r].reg_rtx != 0)
8136 	{
8137 	  int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
8138 	  int k;
8139 
8140 	  /* For a multi register reload, we need to check if all or part
8141 	     of the value lives to the end.  */
8142 	  for (k = 0; k < nr; k++)
8143 	    if (reload_reg_reaches_end_p (i + k, r))
8144 	      CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
8145 
8146 	  /* Maybe the spill reg contains a copy of reload_out.  */
8147 	  if (rld[r].out != 0
8148 	      && (REG_P (rld[r].out)
8149 		  || (rld[r].out_reg
8150 		      ? REG_P (rld[r].out_reg)
8151 		      /* The reload value is an auto-modification of
8152 			 some kind.  For PRE_INC, POST_INC, PRE_DEC
8153 			 and POST_DEC, we record an equivalence
8154 			 between the reload register and the operand
8155 			 on the optimistic assumption that we can make
8156 			 the equivalence hold.  reload_as_needed must
8157 			 then either make it hold or invalidate the
8158 			 equivalence.
8159 
8160 			 PRE_MODIFY and POST_MODIFY addresses are reloaded
8161 			 somewhat differently, and allowing them here leads
8162 			 to problems.  */
8163 		      : (GET_CODE (rld[r].out) != POST_MODIFY
8164 			 && GET_CODE (rld[r].out) != PRE_MODIFY))))
8165 	    {
8166 	      rtx reg;
8167 
8168 	      reg = reload_reg_rtx_for_output[r];
8169 	      if (reload_reg_rtx_reaches_end_p (reg, r))
8170 		{
8171 		  enum machine_mode mode = GET_MODE (reg);
8172 		  int regno = REGNO (reg);
8173 		  int nregs = hard_regno_nregs[regno][mode];
8174 		  rtx out = (REG_P (rld[r].out)
8175 			     ? rld[r].out
8176 			     : rld[r].out_reg
8177 			     ? rld[r].out_reg
8178 /* AUTO_INC */		     : XEXP (rld[r].in_reg, 0));
8179 		  int out_regno = REGNO (out);
8180 		  int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
8181 				   : hard_regno_nregs[out_regno][mode]);
8182 		  bool piecemeal;
8183 
8184 		  spill_reg_store[regno] = new_spill_reg_store[regno];
8185 		  spill_reg_stored_to[regno] = out;
8186 		  reg_last_reload_reg[out_regno] = reg;
8187 
8188 		  piecemeal = (HARD_REGISTER_NUM_P (out_regno)
8189 			       && nregs == out_nregs
8190 			       && inherit_piecemeal_p (out_regno, regno, mode));
8191 
8192 		  /* If OUT_REGNO is a hard register, it may occupy more than
8193 		     one register.  If it does, say what is in the
8194 		     rest of the registers assuming that both registers
8195 		     agree on how many words the object takes.  If not,
8196 		     invalidate the subsequent registers.  */
8197 
8198 		  if (HARD_REGISTER_NUM_P (out_regno))
8199 		    for (k = 1; k < out_nregs; k++)
8200 		      reg_last_reload_reg[out_regno + k]
8201 			= (piecemeal ? regno_reg_rtx[regno + k] : 0);
8202 
8203 		  /* Now do the inverse operation.  */
8204 		  for (k = 0; k < nregs; k++)
8205 		    {
8206 		      CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8207 		      reg_reloaded_contents[regno + k]
8208 			= (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
8209 			   ? out_regno
8210 			   : out_regno + k);
8211 		      reg_reloaded_insn[regno + k] = insn;
8212 		      SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8213 		      if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8214 			SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8215 					  regno + k);
8216 		      else
8217 			CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8218 					    regno + k);
8219 		    }
8220 		}
8221 	    }
8222 	  /* Maybe the spill reg contains a copy of reload_in.  Only do
8223 	     something if there will not be an output reload for
8224 	     the register being reloaded.  */
8225 	  else if (rld[r].out_reg == 0
8226 		   && rld[r].in != 0
8227 		   && ((REG_P (rld[r].in)
8228 			&& !HARD_REGISTER_P (rld[r].in)
8229 			&& !REGNO_REG_SET_P (&reg_has_output_reload,
8230 					     REGNO (rld[r].in)))
8231 		       || (REG_P (rld[r].in_reg)
8232 			   && !REGNO_REG_SET_P (&reg_has_output_reload,
8233 						REGNO (rld[r].in_reg))))
8234 		   && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
8235 	    {
8236 	      rtx reg;
8237 
8238 	      reg = reload_reg_rtx_for_input[r];
8239 	      if (reload_reg_rtx_reaches_end_p (reg, r))
8240 		{
8241 		  enum machine_mode mode;
8242 		  int regno;
8243 		  int nregs;
8244 		  int in_regno;
8245 		  int in_nregs;
8246 		  rtx in;
8247 		  bool piecemeal;
8248 
8249 		  mode = GET_MODE (reg);
8250 		  regno = REGNO (reg);
8251 		  nregs = hard_regno_nregs[regno][mode];
8252 		  if (REG_P (rld[r].in)
8253 		      && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
8254 		    in = rld[r].in;
8255 		  else if (REG_P (rld[r].in_reg))
8256 		    in = rld[r].in_reg;
8257 		  else
8258 		    in = XEXP (rld[r].in_reg, 0);
8259 		  in_regno = REGNO (in);
8260 
8261 		  in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
8262 			      : hard_regno_nregs[in_regno][mode]);
8263 
8264 		  reg_last_reload_reg[in_regno] = reg;
8265 
8266 		  piecemeal = (HARD_REGISTER_NUM_P (in_regno)
8267 			       && nregs == in_nregs
8268 			       && inherit_piecemeal_p (regno, in_regno, mode));
8269 
8270 		  if (HARD_REGISTER_NUM_P (in_regno))
8271 		    for (k = 1; k < in_nregs; k++)
8272 		      reg_last_reload_reg[in_regno + k]
8273 			= (piecemeal ? regno_reg_rtx[regno + k] : 0);
8274 
8275 		  /* Unless we inherited this reload, show we haven't
8276 		     recently done a store.
8277 		     Previous stores of inherited auto_inc expressions
8278 		     also have to be discarded.  */
8279 		  if (! reload_inherited[r]
8280 		      || (rld[r].out && ! rld[r].out_reg))
8281 		    spill_reg_store[regno] = 0;
8282 
8283 		  for (k = 0; k < nregs; k++)
8284 		    {
8285 		      CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8286 		      reg_reloaded_contents[regno + k]
8287 			= (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
8288 			   ? in_regno
8289 			   : in_regno + k);
8290 		      reg_reloaded_insn[regno + k] = insn;
8291 		      SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8292 		      if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8293 			SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8294 					  regno + k);
8295 		      else
8296 			CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8297 					    regno + k);
8298 		    }
8299 		}
8300 	    }
8301 	}
8302 
8303       /* The following if-statement was #if 0'd in 1.34 (or before...).
8304 	 It's reenabled in 1.35 because supposedly nothing else
8305 	 deals with this problem.  */
8306 
8307       /* If a register gets output-reloaded from a non-spill register,
8308 	 that invalidates any previous reloaded copy of it.
8309 	 But forget_old_reloads_1 won't get to see it, because
8310 	 it thinks only about the original insn.  So invalidate it here.
8311 	 Also do the same thing for RELOAD_OTHER constraints where the
8312 	 output is discarded.  */
8313       if (i < 0
8314 	  && ((rld[r].out != 0
8315 	       && (REG_P (rld[r].out)
8316 		   || (MEM_P (rld[r].out)
8317 		       && REG_P (rld[r].out_reg))))
8318 	      || (rld[r].out == 0 && rld[r].out_reg
8319 		  && REG_P (rld[r].out_reg))))
8320 	{
8321 	  rtx out = ((rld[r].out && REG_P (rld[r].out))
8322 		     ? rld[r].out : rld[r].out_reg);
8323 	  int out_regno = REGNO (out);
8324 	  enum machine_mode mode = GET_MODE (out);
8325 
8326 	  /* REG_RTX is now set or clobbered by the main instruction.
8327 	     As the comment above explains, forget_old_reloads_1 only
8328 	     sees the original instruction, and there is no guarantee
8329 	     that the original instruction also clobbered REG_RTX.
8330 	     For example, if find_reloads sees that the input side of
8331 	     a matched operand pair dies in this instruction, it may
8332 	     use the input register as the reload register.
8333 
8334 	     Calling forget_old_reloads_1 is a waste of effort if
8335 	     REG_RTX is also the output register.
8336 
8337 	     If we know that REG_RTX holds the value of a pseudo
8338 	     register, the code after the call will record that fact.  */
8339 	  if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8340 	    forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8341 
8342 	  if (!HARD_REGISTER_NUM_P (out_regno))
8343 	    {
8344 	      rtx src_reg, store_insn = NULL_RTX;
8345 
8346 	      reg_last_reload_reg[out_regno] = 0;
8347 
8348 	      /* If we can find a hard register that is stored, record
8349 		 the storing insn so that we may delete this insn with
8350 		 delete_output_reload.  */
8351 	      src_reg = reload_reg_rtx_for_output[r];
8352 
8353 	      if (src_reg)
8354 		{
8355 		  if (reload_reg_rtx_reaches_end_p (src_reg, r))
8356 		    store_insn = new_spill_reg_store[REGNO (src_reg)];
8357 		  else
8358 		    src_reg = NULL_RTX;
8359 		}
8360 	      else
8361 		{
8362 		  /* If this is an optional reload, try to find the
8363 		     source reg from an input reload.  */
8364 		  rtx set = single_set (insn);
8365 		  if (set && SET_DEST (set) == rld[r].out)
8366 		    {
8367 		      int k;
8368 
8369 		      src_reg = SET_SRC (set);
8370 		      store_insn = insn;
8371 		      for (k = 0; k < n_reloads; k++)
8372 			{
8373 			  if (rld[k].in == src_reg)
8374 			    {
8375 			      src_reg = reload_reg_rtx_for_input[k];
8376 			      break;
8377 			    }
8378 			}
8379 		    }
8380 		}
8381 	      if (src_reg && REG_P (src_reg)
8382 		  && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8383 		{
8384 		  int src_regno, src_nregs, k;
8385 		  rtx note;
8386 
8387 		  gcc_assert (GET_MODE (src_reg) == mode);
8388 		  src_regno = REGNO (src_reg);
8389 		  src_nregs = hard_regno_nregs[src_regno][mode];
8390 		  /* The place where to find a death note varies with
8391 		     PRESERVE_DEATH_INFO_REGNO_P .  The condition is not
8392 		     necessarily checked exactly in the code that moves
8393 		     notes, so just check both locations.  */
8394 		  note = find_regno_note (insn, REG_DEAD, src_regno);
8395 		  if (! note && store_insn)
8396 		    note = find_regno_note (store_insn, REG_DEAD, src_regno);
8397 		  for (k = 0; k < src_nregs; k++)
8398 		    {
8399 		      spill_reg_store[src_regno + k] = store_insn;
8400 		      spill_reg_stored_to[src_regno + k] = out;
8401 		      reg_reloaded_contents[src_regno + k] = out_regno;
8402 		      reg_reloaded_insn[src_regno + k] = store_insn;
8403 		      CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8404 		      SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8405 		      if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
8406 							  mode))
8407 			SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8408 					  src_regno + k);
8409 		      else
8410 			CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8411 					    src_regno + k);
8412 		      SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8413 		      if (note)
8414 			SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8415 		      else
8416 			CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8417 		    }
8418 		  reg_last_reload_reg[out_regno] = src_reg;
8419 		  /* We have to set reg_has_output_reload here, or else
8420 		     forget_old_reloads_1 will clear reg_last_reload_reg
8421 		     right away.  */
8422 		  SET_REGNO_REG_SET (&reg_has_output_reload,
8423 				     out_regno);
8424 		}
8425 	    }
8426 	  else
8427 	    {
8428 	      int k, out_nregs = hard_regno_nregs[out_regno][mode];
8429 
8430 	      for (k = 0; k < out_nregs; k++)
8431 		reg_last_reload_reg[out_regno + k] = 0;
8432 	    }
8433 	}
8434     }
8435   IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
8436 }
8437 
8438 /* Go through the motions to emit INSN and test if it is strictly valid.
8439    Return the emitted insn if valid, else return NULL.  */
8440 
8441 static rtx
emit_insn_if_valid_for_reload(rtx insn)8442 emit_insn_if_valid_for_reload (rtx insn)
8443 {
8444   rtx last = get_last_insn ();
8445   int code;
8446 
8447   insn = emit_insn (insn);
8448   code = recog_memoized (insn);
8449 
8450   if (code >= 0)
8451     {
8452       extract_insn (insn);
8453       /* We want constrain operands to treat this insn strictly in its
8454 	 validity determination, i.e., the way it would after reload has
8455 	 completed.  */
8456       if (constrain_operands (1))
8457 	return insn;
8458     }
8459 
8460   delete_insns_since (last);
8461   return NULL;
8462 }
8463 
8464 /* Emit code to perform a reload from IN (which may be a reload register) to
8465    OUT (which may also be a reload register).  IN or OUT is from operand
8466    OPNUM with reload type TYPE.
8467 
8468    Returns first insn emitted.  */
8469 
8470 static rtx
gen_reload(rtx out,rtx in,int opnum,enum reload_type type)8471 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8472 {
8473   rtx last = get_last_insn ();
8474   rtx tem;
8475 
8476   /* If IN is a paradoxical SUBREG, remove it and try to put the
8477      opposite SUBREG on OUT.  Likewise for a paradoxical SUBREG on OUT.  */
8478   if (!strip_paradoxical_subreg (&in, &out))
8479     strip_paradoxical_subreg (&out, &in);
8480 
8481   /* How to do this reload can get quite tricky.  Normally, we are being
8482      asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8483      register that didn't get a hard register.  In that case we can just
8484      call emit_move_insn.
8485 
8486      We can also be asked to reload a PLUS that adds a register or a MEM to
8487      another register, constant or MEM.  This can occur during frame pointer
8488      elimination and while reloading addresses.  This case is handled by
8489      trying to emit a single insn to perform the add.  If it is not valid,
8490      we use a two insn sequence.
8491 
8492      Or we can be asked to reload an unary operand that was a fragment of
8493      an addressing mode, into a register.  If it isn't recognized as-is,
8494      we try making the unop operand and the reload-register the same:
8495      (set reg:X (unop:X expr:Y))
8496      -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8497 
8498      Finally, we could be called to handle an 'o' constraint by putting
8499      an address into a register.  In that case, we first try to do this
8500      with a named pattern of "reload_load_address".  If no such pattern
8501      exists, we just emit a SET insn and hope for the best (it will normally
8502      be valid on machines that use 'o').
8503 
8504      This entire process is made complex because reload will never
8505      process the insns we generate here and so we must ensure that
8506      they will fit their constraints and also by the fact that parts of
8507      IN might be being reloaded separately and replaced with spill registers.
8508      Because of this, we are, in some sense, just guessing the right approach
8509      here.  The one listed above seems to work.
8510 
8511      ??? At some point, this whole thing needs to be rethought.  */
8512 
8513   if (GET_CODE (in) == PLUS
8514       && (REG_P (XEXP (in, 0))
8515 	  || GET_CODE (XEXP (in, 0)) == SUBREG
8516 	  || MEM_P (XEXP (in, 0)))
8517       && (REG_P (XEXP (in, 1))
8518 	  || GET_CODE (XEXP (in, 1)) == SUBREG
8519 	  || CONSTANT_P (XEXP (in, 1))
8520 	  || MEM_P (XEXP (in, 1))))
8521     {
8522       /* We need to compute the sum of a register or a MEM and another
8523 	 register, constant, or MEM, and put it into the reload
8524 	 register.  The best possible way of doing this is if the machine
8525 	 has a three-operand ADD insn that accepts the required operands.
8526 
8527 	 The simplest approach is to try to generate such an insn and see if it
8528 	 is recognized and matches its constraints.  If so, it can be used.
8529 
8530 	 It might be better not to actually emit the insn unless it is valid,
8531 	 but we need to pass the insn as an operand to `recog' and
8532 	 `extract_insn' and it is simpler to emit and then delete the insn if
8533 	 not valid than to dummy things up.  */
8534 
8535       rtx op0, op1, tem, insn;
8536       enum insn_code code;
8537 
8538       op0 = find_replacement (&XEXP (in, 0));
8539       op1 = find_replacement (&XEXP (in, 1));
8540 
8541       /* Since constraint checking is strict, commutativity won't be
8542 	 checked, so we need to do that here to avoid spurious failure
8543 	 if the add instruction is two-address and the second operand
8544 	 of the add is the same as the reload reg, which is frequently
8545 	 the case.  If the insn would be A = B + A, rearrange it so
8546 	 it will be A = A + B as constrain_operands expects.  */
8547 
8548       if (REG_P (XEXP (in, 1))
8549 	  && REGNO (out) == REGNO (XEXP (in, 1)))
8550 	tem = op0, op0 = op1, op1 = tem;
8551 
8552       if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8553 	in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8554 
8555       insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8556       if (insn)
8557 	return insn;
8558 
8559       /* If that failed, we must use a conservative two-insn sequence.
8560 
8561 	 Use a move to copy one operand into the reload register.  Prefer
8562 	 to reload a constant, MEM or pseudo since the move patterns can
8563 	 handle an arbitrary operand.  If OP1 is not a constant, MEM or
8564 	 pseudo and OP1 is not a valid operand for an add instruction, then
8565 	 reload OP1.
8566 
8567 	 After reloading one of the operands into the reload register, add
8568 	 the reload register to the output register.
8569 
8570 	 If there is another way to do this for a specific machine, a
8571 	 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8572 	 we emit below.  */
8573 
8574       code = optab_handler (add_optab, GET_MODE (out));
8575 
8576       if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8577 	  || (REG_P (op1)
8578 	      && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8579 	  || (code != CODE_FOR_nothing
8580 	      && !insn_operand_matches (code, 2, op1)))
8581 	tem = op0, op0 = op1, op1 = tem;
8582 
8583       gen_reload (out, op0, opnum, type);
8584 
8585       /* If OP0 and OP1 are the same, we can use OUT for OP1.
8586 	 This fixes a problem on the 32K where the stack pointer cannot
8587 	 be used as an operand of an add insn.  */
8588 
8589       if (rtx_equal_p (op0, op1))
8590 	op1 = out;
8591 
8592       insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8593       if (insn)
8594 	{
8595 	  /* Add a REG_EQUIV note so that find_equiv_reg can find it.  */
8596 	  set_dst_reg_note (insn, REG_EQUIV, in, out);
8597 	  return insn;
8598 	}
8599 
8600       /* If that failed, copy the address register to the reload register.
8601 	 Then add the constant to the reload register.  */
8602 
8603       gcc_assert (!reg_overlap_mentioned_p (out, op0));
8604       gen_reload (out, op1, opnum, type);
8605       insn = emit_insn (gen_add2_insn (out, op0));
8606       set_dst_reg_note (insn, REG_EQUIV, in, out);
8607     }
8608 
8609 #ifdef SECONDARY_MEMORY_NEEDED
8610   /* If we need a memory location to do the move, do it that way.  */
8611   else if ((REG_P (in)
8612             || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
8613 	   && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
8614 	   && (REG_P (out)
8615 	       || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
8616 	   && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
8617 	   && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
8618 				       REGNO_REG_CLASS (reg_or_subregno (out)),
8619 				       GET_MODE (out)))
8620     {
8621       /* Get the memory to use and rewrite both registers to its mode.  */
8622       rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8623 
8624       if (GET_MODE (loc) != GET_MODE (out))
8625 	out = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (out));
8626 
8627       if (GET_MODE (loc) != GET_MODE (in))
8628 	in = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (in));
8629 
8630       gen_reload (loc, in, opnum, type);
8631       gen_reload (out, loc, opnum, type);
8632     }
8633 #endif
8634   else if (REG_P (out) && UNARY_P (in))
8635     {
8636       rtx insn;
8637       rtx op1;
8638       rtx out_moded;
8639       rtx set;
8640 
8641       op1 = find_replacement (&XEXP (in, 0));
8642       if (op1 != XEXP (in, 0))
8643 	in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8644 
8645       /* First, try a plain SET.  */
8646       set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8647       if (set)
8648 	return set;
8649 
8650       /* If that failed, move the inner operand to the reload
8651 	 register, and try the same unop with the inner expression
8652 	 replaced with the reload register.  */
8653 
8654       if (GET_MODE (op1) != GET_MODE (out))
8655 	out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8656       else
8657 	out_moded = out;
8658 
8659       gen_reload (out_moded, op1, opnum, type);
8660 
8661       insn
8662 	= gen_rtx_SET (VOIDmode, out,
8663 		       gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8664 				      out_moded));
8665       insn = emit_insn_if_valid_for_reload (insn);
8666       if (insn)
8667 	{
8668 	  set_unique_reg_note (insn, REG_EQUIV, in);
8669 	  return insn;
8670 	}
8671 
8672       fatal_insn ("failure trying to reload:", set);
8673     }
8674   /* If IN is a simple operand, use gen_move_insn.  */
8675   else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8676     {
8677       tem = emit_insn (gen_move_insn (out, in));
8678       /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note.  */
8679       mark_jump_label (in, tem, 0);
8680     }
8681 
8682 #ifdef HAVE_reload_load_address
8683   else if (HAVE_reload_load_address)
8684     emit_insn (gen_reload_load_address (out, in));
8685 #endif
8686 
8687   /* Otherwise, just write (set OUT IN) and hope for the best.  */
8688   else
8689     emit_insn (gen_rtx_SET (VOIDmode, out, in));
8690 
8691   /* Return the first insn emitted.
8692      We can not just return get_last_insn, because there may have
8693      been multiple instructions emitted.  Also note that gen_move_insn may
8694      emit more than one insn itself, so we can not assume that there is one
8695      insn emitted per emit_insn_before call.  */
8696 
8697   return last ? NEXT_INSN (last) : get_insns ();
8698 }
8699 
8700 /* Delete a previously made output-reload whose result we now believe
8701    is not needed.  First we double-check.
8702 
8703    INSN is the insn now being processed.
8704    LAST_RELOAD_REG is the hard register number for which we want to delete
8705    the last output reload.
8706    J is the reload-number that originally used REG.  The caller has made
8707    certain that reload J doesn't use REG any longer for input.
8708    NEW_RELOAD_REG is reload register that reload J is using for REG.  */
8709 
8710 static void
delete_output_reload(rtx insn,int j,int last_reload_reg,rtx new_reload_reg)8711 delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg)
8712 {
8713   rtx output_reload_insn = spill_reg_store[last_reload_reg];
8714   rtx reg = spill_reg_stored_to[last_reload_reg];
8715   int k;
8716   int n_occurrences;
8717   int n_inherited = 0;
8718   rtx i1;
8719   rtx substed;
8720   unsigned regno;
8721   int nregs;
8722 
8723   /* It is possible that this reload has been only used to set another reload
8724      we eliminated earlier and thus deleted this instruction too.  */
8725   if (INSN_DELETED_P (output_reload_insn))
8726     return;
8727 
8728   /* Get the raw pseudo-register referred to.  */
8729 
8730   while (GET_CODE (reg) == SUBREG)
8731     reg = SUBREG_REG (reg);
8732   substed = reg_equiv_memory_loc (REGNO (reg));
8733 
8734   /* This is unsafe if the operand occurs more often in the current
8735      insn than it is inherited.  */
8736   for (k = n_reloads - 1; k >= 0; k--)
8737     {
8738       rtx reg2 = rld[k].in;
8739       if (! reg2)
8740 	continue;
8741       if (MEM_P (reg2) || reload_override_in[k])
8742 	reg2 = rld[k].in_reg;
8743 #ifdef AUTO_INC_DEC
8744       if (rld[k].out && ! rld[k].out_reg)
8745 	reg2 = XEXP (rld[k].in_reg, 0);
8746 #endif
8747       while (GET_CODE (reg2) == SUBREG)
8748 	reg2 = SUBREG_REG (reg2);
8749       if (rtx_equal_p (reg2, reg))
8750 	{
8751 	  if (reload_inherited[k] || reload_override_in[k] || k == j)
8752 	    n_inherited++;
8753 	  else
8754 	    return;
8755 	}
8756     }
8757   n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8758   if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8759     n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8760 					reg, 0);
8761   if (substed)
8762     n_occurrences += count_occurrences (PATTERN (insn),
8763 					eliminate_regs (substed, VOIDmode,
8764 							NULL_RTX), 0);
8765   for (i1 = reg_equiv_alt_mem_list (REGNO (reg)); i1; i1 = XEXP (i1, 1))
8766     {
8767       gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8768       n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8769     }
8770   if (n_occurrences > n_inherited)
8771     return;
8772 
8773   regno = REGNO (reg);
8774   if (regno >= FIRST_PSEUDO_REGISTER)
8775     nregs = 1;
8776   else
8777     nregs = hard_regno_nregs[regno][GET_MODE (reg)];
8778 
8779   /* If the pseudo-reg we are reloading is no longer referenced
8780      anywhere between the store into it and here,
8781      and we're within the same basic block, then the value can only
8782      pass through the reload reg and end up here.
8783      Otherwise, give up--return.  */
8784   for (i1 = NEXT_INSN (output_reload_insn);
8785        i1 != insn; i1 = NEXT_INSN (i1))
8786     {
8787       if (NOTE_INSN_BASIC_BLOCK_P (i1))
8788 	return;
8789       if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8790 	  && refers_to_regno_p (regno, regno + nregs, PATTERN (i1), NULL))
8791 	{
8792 	  /* If this is USE in front of INSN, we only have to check that
8793 	     there are no more references than accounted for by inheritance.  */
8794 	  while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8795 	    {
8796 	      n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8797 	      i1 = NEXT_INSN (i1);
8798 	    }
8799 	  if (n_occurrences <= n_inherited && i1 == insn)
8800 	    break;
8801 	  return;
8802 	}
8803     }
8804 
8805   /* We will be deleting the insn.  Remove the spill reg information.  */
8806   for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8807     {
8808       spill_reg_store[last_reload_reg + k] = 0;
8809       spill_reg_stored_to[last_reload_reg + k] = 0;
8810     }
8811 
8812   /* The caller has already checked that REG dies or is set in INSN.
8813      It has also checked that we are optimizing, and thus some
8814      inaccuracies in the debugging information are acceptable.
8815      So we could just delete output_reload_insn.  But in some cases
8816      we can improve the debugging information without sacrificing
8817      optimization - maybe even improving the code: See if the pseudo
8818      reg has been completely replaced with reload regs.  If so, delete
8819      the store insn and forget we had a stack slot for the pseudo.  */
8820   if (rld[j].out != rld[j].in
8821       && REG_N_DEATHS (REGNO (reg)) == 1
8822       && REG_N_SETS (REGNO (reg)) == 1
8823       && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8824       && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8825     {
8826       rtx i2;
8827 
8828       /* We know that it was used only between here and the beginning of
8829 	 the current basic block.  (We also know that the last use before
8830 	 INSN was the output reload we are thinking of deleting, but never
8831 	 mind that.)  Search that range; see if any ref remains.  */
8832       for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8833 	{
8834 	  rtx set = single_set (i2);
8835 
8836 	  /* Uses which just store in the pseudo don't count,
8837 	     since if they are the only uses, they are dead.  */
8838 	  if (set != 0 && SET_DEST (set) == reg)
8839 	    continue;
8840 	  if (LABEL_P (i2)
8841 	      || JUMP_P (i2))
8842 	    break;
8843 	  if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8844 	      && reg_mentioned_p (reg, PATTERN (i2)))
8845 	    {
8846 	      /* Some other ref remains; just delete the output reload we
8847 		 know to be dead.  */
8848 	      delete_address_reloads (output_reload_insn, insn);
8849 	      delete_insn (output_reload_insn);
8850 	      return;
8851 	    }
8852 	}
8853 
8854       /* Delete the now-dead stores into this pseudo.  Note that this
8855 	 loop also takes care of deleting output_reload_insn.  */
8856       for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8857 	{
8858 	  rtx set = single_set (i2);
8859 
8860 	  if (set != 0 && SET_DEST (set) == reg)
8861 	    {
8862 	      delete_address_reloads (i2, insn);
8863 	      delete_insn (i2);
8864 	    }
8865 	  if (LABEL_P (i2)
8866 	      || JUMP_P (i2))
8867 	    break;
8868 	}
8869 
8870       /* For the debugging info, say the pseudo lives in this reload reg.  */
8871       reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8872       if (ira_conflicts_p)
8873 	/* Inform IRA about the change.  */
8874 	ira_mark_allocation_change (REGNO (reg));
8875       alter_reg (REGNO (reg), -1, false);
8876     }
8877   else
8878     {
8879       delete_address_reloads (output_reload_insn, insn);
8880       delete_insn (output_reload_insn);
8881     }
8882 }
8883 
8884 /* We are going to delete DEAD_INSN.  Recursively delete loads of
8885    reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8886    CURRENT_INSN is being reloaded, so we have to check its reloads too.  */
8887 static void
delete_address_reloads(rtx dead_insn,rtx current_insn)8888 delete_address_reloads (rtx dead_insn, rtx current_insn)
8889 {
8890   rtx set = single_set (dead_insn);
8891   rtx set2, dst, prev, next;
8892   if (set)
8893     {
8894       rtx dst = SET_DEST (set);
8895       if (MEM_P (dst))
8896 	delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8897     }
8898   /* If we deleted the store from a reloaded post_{in,de}c expression,
8899      we can delete the matching adds.  */
8900   prev = PREV_INSN (dead_insn);
8901   next = NEXT_INSN (dead_insn);
8902   if (! prev || ! next)
8903     return;
8904   set = single_set (next);
8905   set2 = single_set (prev);
8906   if (! set || ! set2
8907       || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8908       || !CONST_INT_P (XEXP (SET_SRC (set), 1))
8909       || !CONST_INT_P (XEXP (SET_SRC (set2), 1)))
8910     return;
8911   dst = SET_DEST (set);
8912   if (! rtx_equal_p (dst, SET_DEST (set2))
8913       || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8914       || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8915       || (INTVAL (XEXP (SET_SRC (set), 1))
8916 	  != -INTVAL (XEXP (SET_SRC (set2), 1))))
8917     return;
8918   delete_related_insns (prev);
8919   delete_related_insns (next);
8920 }
8921 
8922 /* Subfunction of delete_address_reloads: process registers found in X.  */
8923 static void
delete_address_reloads_1(rtx dead_insn,rtx x,rtx current_insn)8924 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8925 {
8926   rtx prev, set, dst, i2;
8927   int i, j;
8928   enum rtx_code code = GET_CODE (x);
8929 
8930   if (code != REG)
8931     {
8932       const char *fmt = GET_RTX_FORMAT (code);
8933       for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8934 	{
8935 	  if (fmt[i] == 'e')
8936 	    delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8937 	  else if (fmt[i] == 'E')
8938 	    {
8939 	      for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8940 		delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8941 					  current_insn);
8942 	    }
8943 	}
8944       return;
8945     }
8946 
8947   if (spill_reg_order[REGNO (x)] < 0)
8948     return;
8949 
8950   /* Scan backwards for the insn that sets x.  This might be a way back due
8951      to inheritance.  */
8952   for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8953     {
8954       code = GET_CODE (prev);
8955       if (code == CODE_LABEL || code == JUMP_INSN)
8956 	return;
8957       if (!INSN_P (prev))
8958 	continue;
8959       if (reg_set_p (x, PATTERN (prev)))
8960 	break;
8961       if (reg_referenced_p (x, PATTERN (prev)))
8962 	return;
8963     }
8964   if (! prev || INSN_UID (prev) < reload_first_uid)
8965     return;
8966   /* Check that PREV only sets the reload register.  */
8967   set = single_set (prev);
8968   if (! set)
8969     return;
8970   dst = SET_DEST (set);
8971   if (!REG_P (dst)
8972       || ! rtx_equal_p (dst, x))
8973     return;
8974   if (! reg_set_p (dst, PATTERN (dead_insn)))
8975     {
8976       /* Check if DST was used in a later insn -
8977 	 it might have been inherited.  */
8978       for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8979 	{
8980 	  if (LABEL_P (i2))
8981 	    break;
8982 	  if (! INSN_P (i2))
8983 	    continue;
8984 	  if (reg_referenced_p (dst, PATTERN (i2)))
8985 	    {
8986 	      /* If there is a reference to the register in the current insn,
8987 		 it might be loaded in a non-inherited reload.  If no other
8988 		 reload uses it, that means the register is set before
8989 		 referenced.  */
8990 	      if (i2 == current_insn)
8991 		{
8992 		  for (j = n_reloads - 1; j >= 0; j--)
8993 		    if ((rld[j].reg_rtx == dst && reload_inherited[j])
8994 			|| reload_override_in[j] == dst)
8995 		      return;
8996 		  for (j = n_reloads - 1; j >= 0; j--)
8997 		    if (rld[j].in && rld[j].reg_rtx == dst)
8998 		      break;
8999 		  if (j >= 0)
9000 		    break;
9001 		}
9002 	      return;
9003 	    }
9004 	  if (JUMP_P (i2))
9005 	    break;
9006 	  /* If DST is still live at CURRENT_INSN, check if it is used for
9007 	     any reload.  Note that even if CURRENT_INSN sets DST, we still
9008 	     have to check the reloads.  */
9009 	  if (i2 == current_insn)
9010 	    {
9011 	      for (j = n_reloads - 1; j >= 0; j--)
9012 		if ((rld[j].reg_rtx == dst && reload_inherited[j])
9013 		    || reload_override_in[j] == dst)
9014 		  return;
9015 	      /* ??? We can't finish the loop here, because dst might be
9016 		 allocated to a pseudo in this block if no reload in this
9017 		 block needs any of the classes containing DST - see
9018 		 spill_hard_reg.  There is no easy way to tell this, so we
9019 		 have to scan till the end of the basic block.  */
9020 	    }
9021 	  if (reg_set_p (dst, PATTERN (i2)))
9022 	    break;
9023 	}
9024     }
9025   delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
9026   reg_reloaded_contents[REGNO (dst)] = -1;
9027   delete_insn (prev);
9028 }
9029 
9030 /* Output reload-insns to reload VALUE into RELOADREG.
9031    VALUE is an autoincrement or autodecrement RTX whose operand
9032    is a register or memory location;
9033    so reloading involves incrementing that location.
9034    IN is either identical to VALUE, or some cheaper place to reload from.
9035 
9036    INC_AMOUNT is the number to increment or decrement by (always positive).
9037    This cannot be deduced from VALUE.  */
9038 
9039 static void
inc_for_reload(rtx reloadreg,rtx in,rtx value,int inc_amount)9040 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
9041 {
9042   /* REG or MEM to be copied and incremented.  */
9043   rtx incloc = find_replacement (&XEXP (value, 0));
9044   /* Nonzero if increment after copying.  */
9045   int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
9046 	      || GET_CODE (value) == POST_MODIFY);
9047   rtx last;
9048   rtx inc;
9049   rtx add_insn;
9050   int code;
9051   rtx real_in = in == value ? incloc : in;
9052 
9053   /* No hard register is equivalent to this register after
9054      inc/dec operation.  If REG_LAST_RELOAD_REG were nonzero,
9055      we could inc/dec that register as well (maybe even using it for
9056      the source), but I'm not sure it's worth worrying about.  */
9057   if (REG_P (incloc))
9058     reg_last_reload_reg[REGNO (incloc)] = 0;
9059 
9060   if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
9061     {
9062       gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
9063       inc = find_replacement (&XEXP (XEXP (value, 1), 1));
9064     }
9065   else
9066     {
9067       if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
9068 	inc_amount = -inc_amount;
9069 
9070       inc = GEN_INT (inc_amount);
9071     }
9072 
9073   /* If this is post-increment, first copy the location to the reload reg.  */
9074   if (post && real_in != reloadreg)
9075     emit_insn (gen_move_insn (reloadreg, real_in));
9076 
9077   if (in == value)
9078     {
9079       /* See if we can directly increment INCLOC.  Use a method similar to
9080 	 that in gen_reload.  */
9081 
9082       last = get_last_insn ();
9083       add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
9084 					 gen_rtx_PLUS (GET_MODE (incloc),
9085 						       incloc, inc)));
9086 
9087       code = recog_memoized (add_insn);
9088       if (code >= 0)
9089 	{
9090 	  extract_insn (add_insn);
9091 	  if (constrain_operands (1))
9092 	    {
9093 	      /* If this is a pre-increment and we have incremented the value
9094 		 where it lives, copy the incremented value to RELOADREG to
9095 		 be used as an address.  */
9096 
9097 	      if (! post)
9098 		emit_insn (gen_move_insn (reloadreg, incloc));
9099 	      return;
9100 	    }
9101 	}
9102       delete_insns_since (last);
9103     }
9104 
9105   /* If couldn't do the increment directly, must increment in RELOADREG.
9106      The way we do this depends on whether this is pre- or post-increment.
9107      For pre-increment, copy INCLOC to the reload register, increment it
9108      there, then save back.  */
9109 
9110   if (! post)
9111     {
9112       if (in != reloadreg)
9113 	emit_insn (gen_move_insn (reloadreg, real_in));
9114       emit_insn (gen_add2_insn (reloadreg, inc));
9115       emit_insn (gen_move_insn (incloc, reloadreg));
9116     }
9117   else
9118     {
9119       /* Postincrement.
9120 	 Because this might be a jump insn or a compare, and because RELOADREG
9121 	 may not be available after the insn in an input reload, we must do
9122 	 the incrementation before the insn being reloaded for.
9123 
9124 	 We have already copied IN to RELOADREG.  Increment the copy in
9125 	 RELOADREG, save that back, then decrement RELOADREG so it has
9126 	 the original value.  */
9127 
9128       emit_insn (gen_add2_insn (reloadreg, inc));
9129       emit_insn (gen_move_insn (incloc, reloadreg));
9130       if (CONST_INT_P (inc))
9131 	emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
9132       else
9133 	emit_insn (gen_sub2_insn (reloadreg, inc));
9134     }
9135 }
9136 
9137 #ifdef AUTO_INC_DEC
9138 static void
add_auto_inc_notes(rtx insn,rtx x)9139 add_auto_inc_notes (rtx insn, rtx x)
9140 {
9141   enum rtx_code code = GET_CODE (x);
9142   const char *fmt;
9143   int i, j;
9144 
9145   if (code == MEM && auto_inc_p (XEXP (x, 0)))
9146     {
9147       add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
9148       return;
9149     }
9150 
9151   /* Scan all the operand sub-expressions.  */
9152   fmt = GET_RTX_FORMAT (code);
9153   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9154     {
9155       if (fmt[i] == 'e')
9156 	add_auto_inc_notes (insn, XEXP (x, i));
9157       else if (fmt[i] == 'E')
9158 	for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9159 	  add_auto_inc_notes (insn, XVECEXP (x, i, j));
9160     }
9161 }
9162 #endif
9163