1 /*
2 * vfio based device assignment support
3 *
4 * Copyright Red Hat, Inc. 2012
5 *
6 * Authors:
7 * Alex Williamson <alex.williamson@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
12 * Based on qemu-kvm device-assignment:
13 * Adapted for KVM by Qumranet.
14 * Copyright (c) 2007, Neocleus, Alex Novik (alex@neocleus.com)
15 * Copyright (c) 2007, Neocleus, Guy Zana (guy@neocleus.com)
16 * Copyright (C) 2008, Qumranet, Amit Shah (amit.shah@qumranet.com)
17 * Copyright (C) 2008, Red Hat, Amit Shah (amit.shah@redhat.com)
18 * Copyright (C) 2008, IBM, Muli Ben-Yehuda (muli@il.ibm.com)
19 */
20
21 #include "qemu/osdep.h"
22 #include CONFIG_DEVICES /* CONFIG_IOMMUFD */
23 #include <linux/vfio.h>
24 #include <sys/ioctl.h>
25
26 #include "hw/hw.h"
27 #include "hw/pci/msi.h"
28 #include "hw/pci/msix.h"
29 #include "hw/pci/pci_bridge.h"
30 #include "hw/qdev-properties.h"
31 #include "hw/qdev-properties-system.h"
32 #include "migration/vmstate.h"
33 #include "qapi/qmp/qdict.h"
34 #include "qemu/error-report.h"
35 #include "qemu/main-loop.h"
36 #include "qemu/module.h"
37 #include "qemu/range.h"
38 #include "qemu/units.h"
39 #include "sysemu/kvm.h"
40 #include "sysemu/runstate.h"
41 #include "pci.h"
42 #include "trace.h"
43 #include "qapi/error.h"
44 #include "migration/blocker.h"
45 #include "migration/qemu-file.h"
46 #include "sysemu/iommufd.h"
47
48 #define TYPE_VFIO_PCI_NOHOTPLUG "vfio-pci-nohotplug"
49
50 /* Protected by BQL */
51 static KVMRouteChange vfio_route_change;
52
53 static void vfio_disable_interrupts(VFIOPCIDevice *vdev);
54 static void vfio_mmap_set_enabled(VFIOPCIDevice *vdev, bool enabled);
55 static void vfio_msi_disable_common(VFIOPCIDevice *vdev);
56
57 /*
58 * Disabling BAR mmaping can be slow, but toggling it around INTx can
59 * also be a huge overhead. We try to get the best of both worlds by
60 * waiting until an interrupt to disable mmaps (subsequent transitions
61 * to the same state are effectively no overhead). If the interrupt has
62 * been serviced and the time gap is long enough, we re-enable mmaps for
63 * performance. This works well for things like graphics cards, which
64 * may not use their interrupt at all and are penalized to an unusable
65 * level by read/write BAR traps. Other devices, like NICs, have more
66 * regular interrupts and see much better latency by staying in non-mmap
67 * mode. We therefore set the default mmap_timeout such that a ping
68 * is just enough to keep the mmap disabled. Users can experiment with
69 * other options with the x-intx-mmap-timeout-ms parameter (a value of
70 * zero disables the timer).
71 */
vfio_intx_mmap_enable(void * opaque)72 static void vfio_intx_mmap_enable(void *opaque)
73 {
74 VFIOPCIDevice *vdev = opaque;
75
76 if (vdev->intx.pending) {
77 timer_mod(vdev->intx.mmap_timer,
78 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + vdev->intx.mmap_timeout);
79 return;
80 }
81
82 vfio_mmap_set_enabled(vdev, true);
83 }
84
vfio_intx_interrupt(void * opaque)85 static void vfio_intx_interrupt(void *opaque)
86 {
87 VFIOPCIDevice *vdev = opaque;
88
89 if (!event_notifier_test_and_clear(&vdev->intx.interrupt)) {
90 return;
91 }
92
93 trace_vfio_intx_interrupt(vdev->vbasedev.name, 'A' + vdev->intx.pin);
94
95 vdev->intx.pending = true;
96 pci_irq_assert(&vdev->pdev);
97 vfio_mmap_set_enabled(vdev, false);
98 if (vdev->intx.mmap_timeout) {
99 timer_mod(vdev->intx.mmap_timer,
100 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + vdev->intx.mmap_timeout);
101 }
102 }
103
vfio_intx_eoi(VFIODevice * vbasedev)104 static void vfio_intx_eoi(VFIODevice *vbasedev)
105 {
106 VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev);
107
108 if (!vdev->intx.pending) {
109 return;
110 }
111
112 trace_vfio_intx_eoi(vbasedev->name);
113
114 vdev->intx.pending = false;
115 pci_irq_deassert(&vdev->pdev);
116 vfio_unmask_single_irqindex(vbasedev, VFIO_PCI_INTX_IRQ_INDEX);
117 }
118
vfio_intx_enable_kvm(VFIOPCIDevice * vdev,Error ** errp)119 static void vfio_intx_enable_kvm(VFIOPCIDevice *vdev, Error **errp)
120 {
121 #ifdef CONFIG_KVM
122 int irq_fd = event_notifier_get_fd(&vdev->intx.interrupt);
123
124 if (vdev->no_kvm_intx || !kvm_irqfds_enabled() ||
125 vdev->intx.route.mode != PCI_INTX_ENABLED ||
126 !kvm_resamplefds_enabled()) {
127 return;
128 }
129
130 /* Get to a known interrupt state */
131 qemu_set_fd_handler(irq_fd, NULL, NULL, vdev);
132 vfio_mask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX);
133 vdev->intx.pending = false;
134 pci_irq_deassert(&vdev->pdev);
135
136 /* Get an eventfd for resample/unmask */
137 if (event_notifier_init(&vdev->intx.unmask, 0)) {
138 error_setg(errp, "event_notifier_init failed eoi");
139 goto fail;
140 }
141
142 if (kvm_irqchip_add_irqfd_notifier_gsi(kvm_state,
143 &vdev->intx.interrupt,
144 &vdev->intx.unmask,
145 vdev->intx.route.irq)) {
146 error_setg_errno(errp, errno, "failed to setup resample irqfd");
147 goto fail_irqfd;
148 }
149
150 if (vfio_set_irq_signaling(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX, 0,
151 VFIO_IRQ_SET_ACTION_UNMASK,
152 event_notifier_get_fd(&vdev->intx.unmask),
153 errp)) {
154 goto fail_vfio;
155 }
156
157 /* Let'em rip */
158 vfio_unmask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX);
159
160 vdev->intx.kvm_accel = true;
161
162 trace_vfio_intx_enable_kvm(vdev->vbasedev.name);
163
164 return;
165
166 fail_vfio:
167 kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, &vdev->intx.interrupt,
168 vdev->intx.route.irq);
169 fail_irqfd:
170 event_notifier_cleanup(&vdev->intx.unmask);
171 fail:
172 qemu_set_fd_handler(irq_fd, vfio_intx_interrupt, NULL, vdev);
173 vfio_unmask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX);
174 #endif
175 }
176
vfio_intx_disable_kvm(VFIOPCIDevice * vdev)177 static void vfio_intx_disable_kvm(VFIOPCIDevice *vdev)
178 {
179 #ifdef CONFIG_KVM
180 if (!vdev->intx.kvm_accel) {
181 return;
182 }
183
184 /*
185 * Get to a known state, hardware masked, QEMU ready to accept new
186 * interrupts, QEMU IRQ de-asserted.
187 */
188 vfio_mask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX);
189 vdev->intx.pending = false;
190 pci_irq_deassert(&vdev->pdev);
191
192 /* Tell KVM to stop listening for an INTx irqfd */
193 if (kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, &vdev->intx.interrupt,
194 vdev->intx.route.irq)) {
195 error_report("vfio: Error: Failed to disable INTx irqfd: %m");
196 }
197
198 /* We only need to close the eventfd for VFIO to cleanup the kernel side */
199 event_notifier_cleanup(&vdev->intx.unmask);
200
201 /* QEMU starts listening for interrupt events. */
202 qemu_set_fd_handler(event_notifier_get_fd(&vdev->intx.interrupt),
203 vfio_intx_interrupt, NULL, vdev);
204
205 vdev->intx.kvm_accel = false;
206
207 /* If we've missed an event, let it re-fire through QEMU */
208 vfio_unmask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX);
209
210 trace_vfio_intx_disable_kvm(vdev->vbasedev.name);
211 #endif
212 }
213
vfio_intx_update(VFIOPCIDevice * vdev,PCIINTxRoute * route)214 static void vfio_intx_update(VFIOPCIDevice *vdev, PCIINTxRoute *route)
215 {
216 Error *err = NULL;
217
218 trace_vfio_intx_update(vdev->vbasedev.name,
219 vdev->intx.route.irq, route->irq);
220
221 vfio_intx_disable_kvm(vdev);
222
223 vdev->intx.route = *route;
224
225 if (route->mode != PCI_INTX_ENABLED) {
226 return;
227 }
228
229 vfio_intx_enable_kvm(vdev, &err);
230 if (err) {
231 warn_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name);
232 }
233
234 /* Re-enable the interrupt in cased we missed an EOI */
235 vfio_intx_eoi(&vdev->vbasedev);
236 }
237
vfio_intx_routing_notifier(PCIDevice * pdev)238 static void vfio_intx_routing_notifier(PCIDevice *pdev)
239 {
240 VFIOPCIDevice *vdev = VFIO_PCI(pdev);
241 PCIINTxRoute route;
242
243 if (vdev->interrupt != VFIO_INT_INTx) {
244 return;
245 }
246
247 route = pci_device_route_intx_to_irq(&vdev->pdev, vdev->intx.pin);
248
249 if (pci_intx_route_changed(&vdev->intx.route, &route)) {
250 vfio_intx_update(vdev, &route);
251 }
252 }
253
vfio_irqchip_change(Notifier * notify,void * data)254 static void vfio_irqchip_change(Notifier *notify, void *data)
255 {
256 VFIOPCIDevice *vdev = container_of(notify, VFIOPCIDevice,
257 irqchip_change_notifier);
258
259 vfio_intx_update(vdev, &vdev->intx.route);
260 }
261
vfio_intx_enable(VFIOPCIDevice * vdev,Error ** errp)262 static int vfio_intx_enable(VFIOPCIDevice *vdev, Error **errp)
263 {
264 uint8_t pin = vfio_pci_read_config(&vdev->pdev, PCI_INTERRUPT_PIN, 1);
265 Error *err = NULL;
266 int32_t fd;
267 int ret;
268
269
270 if (!pin) {
271 return 0;
272 }
273
274 vfio_disable_interrupts(vdev);
275
276 vdev->intx.pin = pin - 1; /* Pin A (1) -> irq[0] */
277 pci_config_set_interrupt_pin(vdev->pdev.config, pin);
278
279 #ifdef CONFIG_KVM
280 /*
281 * Only conditional to avoid generating error messages on platforms
282 * where we won't actually use the result anyway.
283 */
284 if (kvm_irqfds_enabled() && kvm_resamplefds_enabled()) {
285 vdev->intx.route = pci_device_route_intx_to_irq(&vdev->pdev,
286 vdev->intx.pin);
287 }
288 #endif
289
290 ret = event_notifier_init(&vdev->intx.interrupt, 0);
291 if (ret) {
292 error_setg_errno(errp, -ret, "event_notifier_init failed");
293 return ret;
294 }
295 fd = event_notifier_get_fd(&vdev->intx.interrupt);
296 qemu_set_fd_handler(fd, vfio_intx_interrupt, NULL, vdev);
297
298 if (vfio_set_irq_signaling(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX, 0,
299 VFIO_IRQ_SET_ACTION_TRIGGER, fd, errp)) {
300 qemu_set_fd_handler(fd, NULL, NULL, vdev);
301 event_notifier_cleanup(&vdev->intx.interrupt);
302 return -errno;
303 }
304
305 vfio_intx_enable_kvm(vdev, &err);
306 if (err) {
307 warn_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name);
308 }
309
310 vdev->interrupt = VFIO_INT_INTx;
311
312 trace_vfio_intx_enable(vdev->vbasedev.name);
313 return 0;
314 }
315
vfio_intx_disable(VFIOPCIDevice * vdev)316 static void vfio_intx_disable(VFIOPCIDevice *vdev)
317 {
318 int fd;
319
320 timer_del(vdev->intx.mmap_timer);
321 vfio_intx_disable_kvm(vdev);
322 vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX);
323 vdev->intx.pending = false;
324 pci_irq_deassert(&vdev->pdev);
325 vfio_mmap_set_enabled(vdev, true);
326
327 fd = event_notifier_get_fd(&vdev->intx.interrupt);
328 qemu_set_fd_handler(fd, NULL, NULL, vdev);
329 event_notifier_cleanup(&vdev->intx.interrupt);
330
331 vdev->interrupt = VFIO_INT_NONE;
332
333 trace_vfio_intx_disable(vdev->vbasedev.name);
334 }
335
336 /*
337 * MSI/X
338 */
vfio_msi_interrupt(void * opaque)339 static void vfio_msi_interrupt(void *opaque)
340 {
341 VFIOMSIVector *vector = opaque;
342 VFIOPCIDevice *vdev = vector->vdev;
343 MSIMessage (*get_msg)(PCIDevice *dev, unsigned vector);
344 void (*notify)(PCIDevice *dev, unsigned vector);
345 MSIMessage msg;
346 int nr = vector - vdev->msi_vectors;
347
348 if (!event_notifier_test_and_clear(&vector->interrupt)) {
349 return;
350 }
351
352 if (vdev->interrupt == VFIO_INT_MSIX) {
353 get_msg = msix_get_message;
354 notify = msix_notify;
355
356 /* A masked vector firing needs to use the PBA, enable it */
357 if (msix_is_masked(&vdev->pdev, nr)) {
358 set_bit(nr, vdev->msix->pending);
359 memory_region_set_enabled(&vdev->pdev.msix_pba_mmio, true);
360 trace_vfio_msix_pba_enable(vdev->vbasedev.name);
361 }
362 } else if (vdev->interrupt == VFIO_INT_MSI) {
363 get_msg = msi_get_message;
364 notify = msi_notify;
365 } else {
366 abort();
367 }
368
369 msg = get_msg(&vdev->pdev, nr);
370 trace_vfio_msi_interrupt(vdev->vbasedev.name, nr, msg.address, msg.data);
371 notify(&vdev->pdev, nr);
372 }
373
374 /*
375 * Get MSI-X enabled, but no vector enabled, by setting vector 0 with an invalid
376 * fd to kernel.
377 */
vfio_enable_msix_no_vec(VFIOPCIDevice * vdev)378 static int vfio_enable_msix_no_vec(VFIOPCIDevice *vdev)
379 {
380 g_autofree struct vfio_irq_set *irq_set = NULL;
381 int ret = 0, argsz;
382 int32_t *fd;
383
384 argsz = sizeof(*irq_set) + sizeof(*fd);
385
386 irq_set = g_malloc0(argsz);
387 irq_set->argsz = argsz;
388 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD |
389 VFIO_IRQ_SET_ACTION_TRIGGER;
390 irq_set->index = VFIO_PCI_MSIX_IRQ_INDEX;
391 irq_set->start = 0;
392 irq_set->count = 1;
393 fd = (int32_t *)&irq_set->data;
394 *fd = -1;
395
396 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set);
397
398 return ret;
399 }
400
vfio_enable_vectors(VFIOPCIDevice * vdev,bool msix)401 static int vfio_enable_vectors(VFIOPCIDevice *vdev, bool msix)
402 {
403 struct vfio_irq_set *irq_set;
404 int ret = 0, i, argsz;
405 int32_t *fds;
406
407 /*
408 * If dynamic MSI-X allocation is supported, the vectors to be allocated
409 * and enabled can be scattered. Before kernel enabling MSI-X, setting
410 * nr_vectors causes all these vectors to be allocated on host.
411 *
412 * To keep allocation as needed, use vector 0 with an invalid fd to get
413 * MSI-X enabled first, then set vectors with a potentially sparse set of
414 * eventfds to enable interrupts only when enabled in guest.
415 */
416 if (msix && !vdev->msix->noresize) {
417 ret = vfio_enable_msix_no_vec(vdev);
418
419 if (ret) {
420 return ret;
421 }
422 }
423
424 argsz = sizeof(*irq_set) + (vdev->nr_vectors * sizeof(*fds));
425
426 irq_set = g_malloc0(argsz);
427 irq_set->argsz = argsz;
428 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_TRIGGER;
429 irq_set->index = msix ? VFIO_PCI_MSIX_IRQ_INDEX : VFIO_PCI_MSI_IRQ_INDEX;
430 irq_set->start = 0;
431 irq_set->count = vdev->nr_vectors;
432 fds = (int32_t *)&irq_set->data;
433
434 for (i = 0; i < vdev->nr_vectors; i++) {
435 int fd = -1;
436
437 /*
438 * MSI vs MSI-X - The guest has direct access to MSI mask and pending
439 * bits, therefore we always use the KVM signaling path when setup.
440 * MSI-X mask and pending bits are emulated, so we want to use the
441 * KVM signaling path only when configured and unmasked.
442 */
443 if (vdev->msi_vectors[i].use) {
444 if (vdev->msi_vectors[i].virq < 0 ||
445 (msix && msix_is_masked(&vdev->pdev, i))) {
446 fd = event_notifier_get_fd(&vdev->msi_vectors[i].interrupt);
447 } else {
448 fd = event_notifier_get_fd(&vdev->msi_vectors[i].kvm_interrupt);
449 }
450 }
451
452 fds[i] = fd;
453 }
454
455 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set);
456
457 g_free(irq_set);
458
459 return ret;
460 }
461
vfio_add_kvm_msi_virq(VFIOPCIDevice * vdev,VFIOMSIVector * vector,int vector_n,bool msix)462 static void vfio_add_kvm_msi_virq(VFIOPCIDevice *vdev, VFIOMSIVector *vector,
463 int vector_n, bool msix)
464 {
465 if ((msix && vdev->no_kvm_msix) || (!msix && vdev->no_kvm_msi)) {
466 return;
467 }
468
469 vector->virq = kvm_irqchip_add_msi_route(&vfio_route_change,
470 vector_n, &vdev->pdev);
471 }
472
vfio_connect_kvm_msi_virq(VFIOMSIVector * vector)473 static void vfio_connect_kvm_msi_virq(VFIOMSIVector *vector)
474 {
475 if (vector->virq < 0) {
476 return;
477 }
478
479 if (event_notifier_init(&vector->kvm_interrupt, 0)) {
480 goto fail_notifier;
481 }
482
483 if (kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, &vector->kvm_interrupt,
484 NULL, vector->virq) < 0) {
485 goto fail_kvm;
486 }
487
488 return;
489
490 fail_kvm:
491 event_notifier_cleanup(&vector->kvm_interrupt);
492 fail_notifier:
493 kvm_irqchip_release_virq(kvm_state, vector->virq);
494 vector->virq = -1;
495 }
496
vfio_remove_kvm_msi_virq(VFIOMSIVector * vector)497 static void vfio_remove_kvm_msi_virq(VFIOMSIVector *vector)
498 {
499 kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, &vector->kvm_interrupt,
500 vector->virq);
501 kvm_irqchip_release_virq(kvm_state, vector->virq);
502 vector->virq = -1;
503 event_notifier_cleanup(&vector->kvm_interrupt);
504 }
505
vfio_update_kvm_msi_virq(VFIOMSIVector * vector,MSIMessage msg,PCIDevice * pdev)506 static void vfio_update_kvm_msi_virq(VFIOMSIVector *vector, MSIMessage msg,
507 PCIDevice *pdev)
508 {
509 kvm_irqchip_update_msi_route(kvm_state, vector->virq, msg, pdev);
510 kvm_irqchip_commit_routes(kvm_state);
511 }
512
vfio_msix_vector_do_use(PCIDevice * pdev,unsigned int nr,MSIMessage * msg,IOHandler * handler)513 static int vfio_msix_vector_do_use(PCIDevice *pdev, unsigned int nr,
514 MSIMessage *msg, IOHandler *handler)
515 {
516 VFIOPCIDevice *vdev = VFIO_PCI(pdev);
517 VFIOMSIVector *vector;
518 int ret;
519 bool resizing = !!(vdev->nr_vectors < nr + 1);
520
521 trace_vfio_msix_vector_do_use(vdev->vbasedev.name, nr);
522
523 vector = &vdev->msi_vectors[nr];
524
525 if (!vector->use) {
526 vector->vdev = vdev;
527 vector->virq = -1;
528 if (event_notifier_init(&vector->interrupt, 0)) {
529 error_report("vfio: Error: event_notifier_init failed");
530 }
531 vector->use = true;
532 msix_vector_use(pdev, nr);
533 }
534
535 qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt),
536 handler, NULL, vector);
537
538 /*
539 * Attempt to enable route through KVM irqchip,
540 * default to userspace handling if unavailable.
541 */
542 if (vector->virq >= 0) {
543 if (!msg) {
544 vfio_remove_kvm_msi_virq(vector);
545 } else {
546 vfio_update_kvm_msi_virq(vector, *msg, pdev);
547 }
548 } else {
549 if (msg) {
550 if (vdev->defer_kvm_irq_routing) {
551 vfio_add_kvm_msi_virq(vdev, vector, nr, true);
552 } else {
553 vfio_route_change = kvm_irqchip_begin_route_changes(kvm_state);
554 vfio_add_kvm_msi_virq(vdev, vector, nr, true);
555 kvm_irqchip_commit_route_changes(&vfio_route_change);
556 vfio_connect_kvm_msi_virq(vector);
557 }
558 }
559 }
560
561 /*
562 * When dynamic allocation is not supported, we don't want to have the
563 * host allocate all possible MSI vectors for a device if they're not
564 * in use, so we shutdown and incrementally increase them as needed.
565 * nr_vectors represents the total number of vectors allocated.
566 *
567 * When dynamic allocation is supported, let the host only allocate
568 * and enable a vector when it is in use in guest. nr_vectors represents
569 * the upper bound of vectors being enabled (but not all of the ranges
570 * is allocated or enabled).
571 */
572 if (resizing) {
573 vdev->nr_vectors = nr + 1;
574 }
575
576 if (!vdev->defer_kvm_irq_routing) {
577 if (vdev->msix->noresize && resizing) {
578 vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_MSIX_IRQ_INDEX);
579 ret = vfio_enable_vectors(vdev, true);
580 if (ret) {
581 error_report("vfio: failed to enable vectors, %d", ret);
582 }
583 } else {
584 Error *err = NULL;
585 int32_t fd;
586
587 if (vector->virq >= 0) {
588 fd = event_notifier_get_fd(&vector->kvm_interrupt);
589 } else {
590 fd = event_notifier_get_fd(&vector->interrupt);
591 }
592
593 if (vfio_set_irq_signaling(&vdev->vbasedev,
594 VFIO_PCI_MSIX_IRQ_INDEX, nr,
595 VFIO_IRQ_SET_ACTION_TRIGGER, fd, &err)) {
596 error_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name);
597 }
598 }
599 }
600
601 /* Disable PBA emulation when nothing more is pending. */
602 clear_bit(nr, vdev->msix->pending);
603 if (find_first_bit(vdev->msix->pending,
604 vdev->nr_vectors) == vdev->nr_vectors) {
605 memory_region_set_enabled(&vdev->pdev.msix_pba_mmio, false);
606 trace_vfio_msix_pba_disable(vdev->vbasedev.name);
607 }
608
609 return 0;
610 }
611
vfio_msix_vector_use(PCIDevice * pdev,unsigned int nr,MSIMessage msg)612 static int vfio_msix_vector_use(PCIDevice *pdev,
613 unsigned int nr, MSIMessage msg)
614 {
615 return vfio_msix_vector_do_use(pdev, nr, &msg, vfio_msi_interrupt);
616 }
617
vfio_msix_vector_release(PCIDevice * pdev,unsigned int nr)618 static void vfio_msix_vector_release(PCIDevice *pdev, unsigned int nr)
619 {
620 VFIOPCIDevice *vdev = VFIO_PCI(pdev);
621 VFIOMSIVector *vector = &vdev->msi_vectors[nr];
622
623 trace_vfio_msix_vector_release(vdev->vbasedev.name, nr);
624
625 /*
626 * There are still old guests that mask and unmask vectors on every
627 * interrupt. If we're using QEMU bypass with a KVM irqfd, leave all of
628 * the KVM setup in place, simply switch VFIO to use the non-bypass
629 * eventfd. We'll then fire the interrupt through QEMU and the MSI-X
630 * core will mask the interrupt and set pending bits, allowing it to
631 * be re-asserted on unmask. Nothing to do if already using QEMU mode.
632 */
633 if (vector->virq >= 0) {
634 int32_t fd = event_notifier_get_fd(&vector->interrupt);
635 Error *err = NULL;
636
637 if (vfio_set_irq_signaling(&vdev->vbasedev, VFIO_PCI_MSIX_IRQ_INDEX, nr,
638 VFIO_IRQ_SET_ACTION_TRIGGER, fd, &err)) {
639 error_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name);
640 }
641 }
642 }
643
vfio_prepare_kvm_msi_virq_batch(VFIOPCIDevice * vdev)644 static void vfio_prepare_kvm_msi_virq_batch(VFIOPCIDevice *vdev)
645 {
646 assert(!vdev->defer_kvm_irq_routing);
647 vdev->defer_kvm_irq_routing = true;
648 vfio_route_change = kvm_irqchip_begin_route_changes(kvm_state);
649 }
650
vfio_commit_kvm_msi_virq_batch(VFIOPCIDevice * vdev)651 static void vfio_commit_kvm_msi_virq_batch(VFIOPCIDevice *vdev)
652 {
653 int i;
654
655 assert(vdev->defer_kvm_irq_routing);
656 vdev->defer_kvm_irq_routing = false;
657
658 kvm_irqchip_commit_route_changes(&vfio_route_change);
659
660 for (i = 0; i < vdev->nr_vectors; i++) {
661 vfio_connect_kvm_msi_virq(&vdev->msi_vectors[i]);
662 }
663 }
664
vfio_msix_enable(VFIOPCIDevice * vdev)665 static void vfio_msix_enable(VFIOPCIDevice *vdev)
666 {
667 int ret;
668
669 vfio_disable_interrupts(vdev);
670
671 vdev->msi_vectors = g_new0(VFIOMSIVector, vdev->msix->entries);
672
673 vdev->interrupt = VFIO_INT_MSIX;
674
675 /*
676 * Setting vector notifiers triggers synchronous vector-use
677 * callbacks for each active vector. Deferring to commit the KVM
678 * routes once rather than per vector provides a substantial
679 * performance improvement.
680 */
681 vfio_prepare_kvm_msi_virq_batch(vdev);
682
683 if (msix_set_vector_notifiers(&vdev->pdev, vfio_msix_vector_use,
684 vfio_msix_vector_release, NULL)) {
685 error_report("vfio: msix_set_vector_notifiers failed");
686 }
687
688 vfio_commit_kvm_msi_virq_batch(vdev);
689
690 if (vdev->nr_vectors) {
691 ret = vfio_enable_vectors(vdev, true);
692 if (ret) {
693 error_report("vfio: failed to enable vectors, %d", ret);
694 }
695 } else {
696 /*
697 * Some communication channels between VF & PF or PF & fw rely on the
698 * physical state of the device and expect that enabling MSI-X from the
699 * guest enables the same on the host. When our guest is Linux, the
700 * guest driver call to pci_enable_msix() sets the enabling bit in the
701 * MSI-X capability, but leaves the vector table masked. We therefore
702 * can't rely on a vector_use callback (from request_irq() in the guest)
703 * to switch the physical device into MSI-X mode because that may come a
704 * long time after pci_enable_msix(). This code sets vector 0 with an
705 * invalid fd to make the physical device MSI-X enabled, but with no
706 * vectors enabled, just like the guest view.
707 */
708 ret = vfio_enable_msix_no_vec(vdev);
709 if (ret) {
710 error_report("vfio: failed to enable MSI-X, %d", ret);
711 }
712 }
713
714 trace_vfio_msix_enable(vdev->vbasedev.name);
715 }
716
vfio_msi_enable(VFIOPCIDevice * vdev)717 static void vfio_msi_enable(VFIOPCIDevice *vdev)
718 {
719 int ret, i;
720
721 vfio_disable_interrupts(vdev);
722
723 vdev->nr_vectors = msi_nr_vectors_allocated(&vdev->pdev);
724 retry:
725 /*
726 * Setting vector notifiers needs to enable route for each vector.
727 * Deferring to commit the KVM routes once rather than per vector
728 * provides a substantial performance improvement.
729 */
730 vfio_prepare_kvm_msi_virq_batch(vdev);
731
732 vdev->msi_vectors = g_new0(VFIOMSIVector, vdev->nr_vectors);
733
734 for (i = 0; i < vdev->nr_vectors; i++) {
735 VFIOMSIVector *vector = &vdev->msi_vectors[i];
736
737 vector->vdev = vdev;
738 vector->virq = -1;
739 vector->use = true;
740
741 if (event_notifier_init(&vector->interrupt, 0)) {
742 error_report("vfio: Error: event_notifier_init failed");
743 }
744
745 qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt),
746 vfio_msi_interrupt, NULL, vector);
747
748 /*
749 * Attempt to enable route through KVM irqchip,
750 * default to userspace handling if unavailable.
751 */
752 vfio_add_kvm_msi_virq(vdev, vector, i, false);
753 }
754
755 vfio_commit_kvm_msi_virq_batch(vdev);
756
757 /* Set interrupt type prior to possible interrupts */
758 vdev->interrupt = VFIO_INT_MSI;
759
760 ret = vfio_enable_vectors(vdev, false);
761 if (ret) {
762 if (ret < 0) {
763 error_report("vfio: Error: Failed to setup MSI fds: %m");
764 } else {
765 error_report("vfio: Error: Failed to enable %d "
766 "MSI vectors, retry with %d", vdev->nr_vectors, ret);
767 }
768
769 vfio_msi_disable_common(vdev);
770
771 if (ret > 0) {
772 vdev->nr_vectors = ret;
773 goto retry;
774 }
775
776 /*
777 * Failing to setup MSI doesn't really fall within any specification.
778 * Let's try leaving interrupts disabled and hope the guest figures
779 * out to fall back to INTx for this device.
780 */
781 error_report("vfio: Error: Failed to enable MSI");
782
783 return;
784 }
785
786 trace_vfio_msi_enable(vdev->vbasedev.name, vdev->nr_vectors);
787 }
788
vfio_msi_disable_common(VFIOPCIDevice * vdev)789 static void vfio_msi_disable_common(VFIOPCIDevice *vdev)
790 {
791 int i;
792
793 for (i = 0; i < vdev->nr_vectors; i++) {
794 VFIOMSIVector *vector = &vdev->msi_vectors[i];
795 if (vdev->msi_vectors[i].use) {
796 if (vector->virq >= 0) {
797 vfio_remove_kvm_msi_virq(vector);
798 }
799 qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt),
800 NULL, NULL, NULL);
801 event_notifier_cleanup(&vector->interrupt);
802 }
803 }
804
805 g_free(vdev->msi_vectors);
806 vdev->msi_vectors = NULL;
807 vdev->nr_vectors = 0;
808 vdev->interrupt = VFIO_INT_NONE;
809 }
810
vfio_msix_disable(VFIOPCIDevice * vdev)811 static void vfio_msix_disable(VFIOPCIDevice *vdev)
812 {
813 Error *err = NULL;
814 int i;
815
816 msix_unset_vector_notifiers(&vdev->pdev);
817
818 /*
819 * MSI-X will only release vectors if MSI-X is still enabled on the
820 * device, check through the rest and release it ourselves if necessary.
821 */
822 for (i = 0; i < vdev->nr_vectors; i++) {
823 if (vdev->msi_vectors[i].use) {
824 vfio_msix_vector_release(&vdev->pdev, i);
825 msix_vector_unuse(&vdev->pdev, i);
826 }
827 }
828
829 /*
830 * Always clear MSI-X IRQ index. A PF device could have enabled
831 * MSI-X with no vectors. See vfio_msix_enable().
832 */
833 vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_MSIX_IRQ_INDEX);
834
835 vfio_msi_disable_common(vdev);
836 vfio_intx_enable(vdev, &err);
837 if (err) {
838 error_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name);
839 }
840
841 memset(vdev->msix->pending, 0,
842 BITS_TO_LONGS(vdev->msix->entries) * sizeof(unsigned long));
843
844 trace_vfio_msix_disable(vdev->vbasedev.name);
845 }
846
vfio_msi_disable(VFIOPCIDevice * vdev)847 static void vfio_msi_disable(VFIOPCIDevice *vdev)
848 {
849 Error *err = NULL;
850
851 vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_MSI_IRQ_INDEX);
852 vfio_msi_disable_common(vdev);
853 vfio_intx_enable(vdev, &err);
854 if (err) {
855 error_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name);
856 }
857
858 trace_vfio_msi_disable(vdev->vbasedev.name);
859 }
860
vfio_update_msi(VFIOPCIDevice * vdev)861 static void vfio_update_msi(VFIOPCIDevice *vdev)
862 {
863 int i;
864
865 for (i = 0; i < vdev->nr_vectors; i++) {
866 VFIOMSIVector *vector = &vdev->msi_vectors[i];
867 MSIMessage msg;
868
869 if (!vector->use || vector->virq < 0) {
870 continue;
871 }
872
873 msg = msi_get_message(&vdev->pdev, i);
874 vfio_update_kvm_msi_virq(vector, msg, &vdev->pdev);
875 }
876 }
877
vfio_pci_load_rom(VFIOPCIDevice * vdev)878 static void vfio_pci_load_rom(VFIOPCIDevice *vdev)
879 {
880 struct vfio_region_info *reg_info;
881 uint64_t size;
882 off_t off = 0;
883 ssize_t bytes;
884
885 if (vfio_get_region_info(&vdev->vbasedev,
886 VFIO_PCI_ROM_REGION_INDEX, ®_info)) {
887 error_report("vfio: Error getting ROM info: %m");
888 return;
889 }
890
891 trace_vfio_pci_load_rom(vdev->vbasedev.name, (unsigned long)reg_info->size,
892 (unsigned long)reg_info->offset,
893 (unsigned long)reg_info->flags);
894
895 vdev->rom_size = size = reg_info->size;
896 vdev->rom_offset = reg_info->offset;
897
898 g_free(reg_info);
899
900 if (!vdev->rom_size) {
901 vdev->rom_read_failed = true;
902 error_report("vfio-pci: Cannot read device rom at "
903 "%s", vdev->vbasedev.name);
904 error_printf("Device option ROM contents are probably invalid "
905 "(check dmesg).\nSkip option ROM probe with rombar=0, "
906 "or load from file with romfile=\n");
907 return;
908 }
909
910 vdev->rom = g_malloc(size);
911 memset(vdev->rom, 0xff, size);
912
913 while (size) {
914 bytes = pread(vdev->vbasedev.fd, vdev->rom + off,
915 size, vdev->rom_offset + off);
916 if (bytes == 0) {
917 break;
918 } else if (bytes > 0) {
919 off += bytes;
920 size -= bytes;
921 } else {
922 if (errno == EINTR || errno == EAGAIN) {
923 continue;
924 }
925 error_report("vfio: Error reading device ROM: %m");
926 break;
927 }
928 }
929
930 /*
931 * Test the ROM signature against our device, if the vendor is correct
932 * but the device ID doesn't match, store the correct device ID and
933 * recompute the checksum. Intel IGD devices need this and are known
934 * to have bogus checksums so we can't simply adjust the checksum.
935 */
936 if (pci_get_word(vdev->rom) == 0xaa55 &&
937 pci_get_word(vdev->rom + 0x18) + 8 < vdev->rom_size &&
938 !memcmp(vdev->rom + pci_get_word(vdev->rom + 0x18), "PCIR", 4)) {
939 uint16_t vid, did;
940
941 vid = pci_get_word(vdev->rom + pci_get_word(vdev->rom + 0x18) + 4);
942 did = pci_get_word(vdev->rom + pci_get_word(vdev->rom + 0x18) + 6);
943
944 if (vid == vdev->vendor_id && did != vdev->device_id) {
945 int i;
946 uint8_t csum, *data = vdev->rom;
947
948 pci_set_word(vdev->rom + pci_get_word(vdev->rom + 0x18) + 6,
949 vdev->device_id);
950 data[6] = 0;
951
952 for (csum = 0, i = 0; i < vdev->rom_size; i++) {
953 csum += data[i];
954 }
955
956 data[6] = -csum;
957 }
958 }
959 }
960
vfio_rom_read(void * opaque,hwaddr addr,unsigned size)961 static uint64_t vfio_rom_read(void *opaque, hwaddr addr, unsigned size)
962 {
963 VFIOPCIDevice *vdev = opaque;
964 union {
965 uint8_t byte;
966 uint16_t word;
967 uint32_t dword;
968 uint64_t qword;
969 } val;
970 uint64_t data = 0;
971
972 /* Load the ROM lazily when the guest tries to read it */
973 if (unlikely(!vdev->rom && !vdev->rom_read_failed)) {
974 vfio_pci_load_rom(vdev);
975 }
976
977 memcpy(&val, vdev->rom + addr,
978 (addr < vdev->rom_size) ? MIN(size, vdev->rom_size - addr) : 0);
979
980 switch (size) {
981 case 1:
982 data = val.byte;
983 break;
984 case 2:
985 data = le16_to_cpu(val.word);
986 break;
987 case 4:
988 data = le32_to_cpu(val.dword);
989 break;
990 default:
991 hw_error("vfio: unsupported read size, %d bytes\n", size);
992 break;
993 }
994
995 trace_vfio_rom_read(vdev->vbasedev.name, addr, size, data);
996
997 return data;
998 }
999
vfio_rom_write(void * opaque,hwaddr addr,uint64_t data,unsigned size)1000 static void vfio_rom_write(void *opaque, hwaddr addr,
1001 uint64_t data, unsigned size)
1002 {
1003 }
1004
1005 static const MemoryRegionOps vfio_rom_ops = {
1006 .read = vfio_rom_read,
1007 .write = vfio_rom_write,
1008 .endianness = DEVICE_LITTLE_ENDIAN,
1009 };
1010
vfio_pci_size_rom(VFIOPCIDevice * vdev)1011 static void vfio_pci_size_rom(VFIOPCIDevice *vdev)
1012 {
1013 uint32_t orig, size = cpu_to_le32((uint32_t)PCI_ROM_ADDRESS_MASK);
1014 off_t offset = vdev->config_offset + PCI_ROM_ADDRESS;
1015 DeviceState *dev = DEVICE(vdev);
1016 char *name;
1017 int fd = vdev->vbasedev.fd;
1018
1019 if (vdev->pdev.romfile || !vdev->pdev.rom_bar) {
1020 /* Since pci handles romfile, just print a message and return */
1021 if (vfio_opt_rom_in_denylist(vdev) && vdev->pdev.romfile) {
1022 warn_report("Device at %s is known to cause system instability"
1023 " issues during option rom execution",
1024 vdev->vbasedev.name);
1025 error_printf("Proceeding anyway since user specified romfile\n");
1026 }
1027 return;
1028 }
1029
1030 /*
1031 * Use the same size ROM BAR as the physical device. The contents
1032 * will get filled in later when the guest tries to read it.
1033 */
1034 if (pread(fd, &orig, 4, offset) != 4 ||
1035 pwrite(fd, &size, 4, offset) != 4 ||
1036 pread(fd, &size, 4, offset) != 4 ||
1037 pwrite(fd, &orig, 4, offset) != 4) {
1038 error_report("%s(%s) failed: %m", __func__, vdev->vbasedev.name);
1039 return;
1040 }
1041
1042 size = ~(le32_to_cpu(size) & PCI_ROM_ADDRESS_MASK) + 1;
1043
1044 if (!size) {
1045 return;
1046 }
1047
1048 if (vfio_opt_rom_in_denylist(vdev)) {
1049 if (dev->opts && qdict_haskey(dev->opts, "rombar")) {
1050 warn_report("Device at %s is known to cause system instability"
1051 " issues during option rom execution",
1052 vdev->vbasedev.name);
1053 error_printf("Proceeding anyway since user specified"
1054 " non zero value for rombar\n");
1055 } else {
1056 warn_report("Rom loading for device at %s has been disabled"
1057 " due to system instability issues",
1058 vdev->vbasedev.name);
1059 error_printf("Specify rombar=1 or romfile to force\n");
1060 return;
1061 }
1062 }
1063
1064 trace_vfio_pci_size_rom(vdev->vbasedev.name, size);
1065
1066 name = g_strdup_printf("vfio[%s].rom", vdev->vbasedev.name);
1067
1068 memory_region_init_io(&vdev->pdev.rom, OBJECT(vdev),
1069 &vfio_rom_ops, vdev, name, size);
1070 g_free(name);
1071
1072 pci_register_bar(&vdev->pdev, PCI_ROM_SLOT,
1073 PCI_BASE_ADDRESS_SPACE_MEMORY, &vdev->pdev.rom);
1074
1075 vdev->rom_read_failed = false;
1076 }
1077
vfio_vga_write(void * opaque,hwaddr addr,uint64_t data,unsigned size)1078 void vfio_vga_write(void *opaque, hwaddr addr,
1079 uint64_t data, unsigned size)
1080 {
1081 VFIOVGARegion *region = opaque;
1082 VFIOVGA *vga = container_of(region, VFIOVGA, region[region->nr]);
1083 union {
1084 uint8_t byte;
1085 uint16_t word;
1086 uint32_t dword;
1087 uint64_t qword;
1088 } buf;
1089 off_t offset = vga->fd_offset + region->offset + addr;
1090
1091 switch (size) {
1092 case 1:
1093 buf.byte = data;
1094 break;
1095 case 2:
1096 buf.word = cpu_to_le16(data);
1097 break;
1098 case 4:
1099 buf.dword = cpu_to_le32(data);
1100 break;
1101 default:
1102 hw_error("vfio: unsupported write size, %d bytes", size);
1103 break;
1104 }
1105
1106 if (pwrite(vga->fd, &buf, size, offset) != size) {
1107 error_report("%s(,0x%"HWADDR_PRIx", 0x%"PRIx64", %d) failed: %m",
1108 __func__, region->offset + addr, data, size);
1109 }
1110
1111 trace_vfio_vga_write(region->offset + addr, data, size);
1112 }
1113
vfio_vga_read(void * opaque,hwaddr addr,unsigned size)1114 uint64_t vfio_vga_read(void *opaque, hwaddr addr, unsigned size)
1115 {
1116 VFIOVGARegion *region = opaque;
1117 VFIOVGA *vga = container_of(region, VFIOVGA, region[region->nr]);
1118 union {
1119 uint8_t byte;
1120 uint16_t word;
1121 uint32_t dword;
1122 uint64_t qword;
1123 } buf;
1124 uint64_t data = 0;
1125 off_t offset = vga->fd_offset + region->offset + addr;
1126
1127 if (pread(vga->fd, &buf, size, offset) != size) {
1128 error_report("%s(,0x%"HWADDR_PRIx", %d) failed: %m",
1129 __func__, region->offset + addr, size);
1130 return (uint64_t)-1;
1131 }
1132
1133 switch (size) {
1134 case 1:
1135 data = buf.byte;
1136 break;
1137 case 2:
1138 data = le16_to_cpu(buf.word);
1139 break;
1140 case 4:
1141 data = le32_to_cpu(buf.dword);
1142 break;
1143 default:
1144 hw_error("vfio: unsupported read size, %d bytes", size);
1145 break;
1146 }
1147
1148 trace_vfio_vga_read(region->offset + addr, size, data);
1149
1150 return data;
1151 }
1152
1153 static const MemoryRegionOps vfio_vga_ops = {
1154 .read = vfio_vga_read,
1155 .write = vfio_vga_write,
1156 .endianness = DEVICE_LITTLE_ENDIAN,
1157 };
1158
1159 /*
1160 * Expand memory region of sub-page(size < PAGE_SIZE) MMIO BAR to page
1161 * size if the BAR is in an exclusive page in host so that we could map
1162 * this BAR to guest. But this sub-page BAR may not occupy an exclusive
1163 * page in guest. So we should set the priority of the expanded memory
1164 * region to zero in case of overlap with BARs which share the same page
1165 * with the sub-page BAR in guest. Besides, we should also recover the
1166 * size of this sub-page BAR when its base address is changed in guest
1167 * and not page aligned any more.
1168 */
vfio_sub_page_bar_update_mapping(PCIDevice * pdev,int bar)1169 static void vfio_sub_page_bar_update_mapping(PCIDevice *pdev, int bar)
1170 {
1171 VFIOPCIDevice *vdev = VFIO_PCI(pdev);
1172 VFIORegion *region = &vdev->bars[bar].region;
1173 MemoryRegion *mmap_mr, *region_mr, *base_mr;
1174 PCIIORegion *r;
1175 pcibus_t bar_addr;
1176 uint64_t size = region->size;
1177
1178 /* Make sure that the whole region is allowed to be mmapped */
1179 if (region->nr_mmaps != 1 || !region->mmaps[0].mmap ||
1180 region->mmaps[0].size != region->size) {
1181 return;
1182 }
1183
1184 r = &pdev->io_regions[bar];
1185 bar_addr = r->addr;
1186 base_mr = vdev->bars[bar].mr;
1187 region_mr = region->mem;
1188 mmap_mr = ®ion->mmaps[0].mem;
1189
1190 /* If BAR is mapped and page aligned, update to fill PAGE_SIZE */
1191 if (bar_addr != PCI_BAR_UNMAPPED &&
1192 !(bar_addr & ~qemu_real_host_page_mask())) {
1193 size = qemu_real_host_page_size();
1194 }
1195
1196 memory_region_transaction_begin();
1197
1198 if (vdev->bars[bar].size < size) {
1199 memory_region_set_size(base_mr, size);
1200 }
1201 memory_region_set_size(region_mr, size);
1202 memory_region_set_size(mmap_mr, size);
1203 if (size != vdev->bars[bar].size && memory_region_is_mapped(base_mr)) {
1204 memory_region_del_subregion(r->address_space, base_mr);
1205 memory_region_add_subregion_overlap(r->address_space,
1206 bar_addr, base_mr, 0);
1207 }
1208
1209 memory_region_transaction_commit();
1210 }
1211
1212 /*
1213 * PCI config space
1214 */
vfio_pci_read_config(PCIDevice * pdev,uint32_t addr,int len)1215 uint32_t vfio_pci_read_config(PCIDevice *pdev, uint32_t addr, int len)
1216 {
1217 VFIOPCIDevice *vdev = VFIO_PCI(pdev);
1218 uint32_t emu_bits = 0, emu_val = 0, phys_val = 0, val;
1219
1220 memcpy(&emu_bits, vdev->emulated_config_bits + addr, len);
1221 emu_bits = le32_to_cpu(emu_bits);
1222
1223 if (emu_bits) {
1224 emu_val = pci_default_read_config(pdev, addr, len);
1225 }
1226
1227 if (~emu_bits & (0xffffffffU >> (32 - len * 8))) {
1228 ssize_t ret;
1229
1230 ret = pread(vdev->vbasedev.fd, &phys_val, len,
1231 vdev->config_offset + addr);
1232 if (ret != len) {
1233 error_report("%s(%s, 0x%x, 0x%x) failed: %m",
1234 __func__, vdev->vbasedev.name, addr, len);
1235 return -errno;
1236 }
1237 phys_val = le32_to_cpu(phys_val);
1238 }
1239
1240 val = (emu_val & emu_bits) | (phys_val & ~emu_bits);
1241
1242 trace_vfio_pci_read_config(vdev->vbasedev.name, addr, len, val);
1243
1244 return val;
1245 }
1246
vfio_pci_write_config(PCIDevice * pdev,uint32_t addr,uint32_t val,int len)1247 void vfio_pci_write_config(PCIDevice *pdev,
1248 uint32_t addr, uint32_t val, int len)
1249 {
1250 VFIOPCIDevice *vdev = VFIO_PCI(pdev);
1251 uint32_t val_le = cpu_to_le32(val);
1252
1253 trace_vfio_pci_write_config(vdev->vbasedev.name, addr, val, len);
1254
1255 /* Write everything to VFIO, let it filter out what we can't write */
1256 if (pwrite(vdev->vbasedev.fd, &val_le, len, vdev->config_offset + addr)
1257 != len) {
1258 error_report("%s(%s, 0x%x, 0x%x, 0x%x) failed: %m",
1259 __func__, vdev->vbasedev.name, addr, val, len);
1260 }
1261
1262 /* MSI/MSI-X Enabling/Disabling */
1263 if (pdev->cap_present & QEMU_PCI_CAP_MSI &&
1264 ranges_overlap(addr, len, pdev->msi_cap, vdev->msi_cap_size)) {
1265 int is_enabled, was_enabled = msi_enabled(pdev);
1266
1267 pci_default_write_config(pdev, addr, val, len);
1268
1269 is_enabled = msi_enabled(pdev);
1270
1271 if (!was_enabled) {
1272 if (is_enabled) {
1273 vfio_msi_enable(vdev);
1274 }
1275 } else {
1276 if (!is_enabled) {
1277 vfio_msi_disable(vdev);
1278 } else {
1279 vfio_update_msi(vdev);
1280 }
1281 }
1282 } else if (pdev->cap_present & QEMU_PCI_CAP_MSIX &&
1283 ranges_overlap(addr, len, pdev->msix_cap, MSIX_CAP_LENGTH)) {
1284 int is_enabled, was_enabled = msix_enabled(pdev);
1285
1286 pci_default_write_config(pdev, addr, val, len);
1287
1288 is_enabled = msix_enabled(pdev);
1289
1290 if (!was_enabled && is_enabled) {
1291 vfio_msix_enable(vdev);
1292 } else if (was_enabled && !is_enabled) {
1293 vfio_msix_disable(vdev);
1294 }
1295 } else if (ranges_overlap(addr, len, PCI_BASE_ADDRESS_0, 24) ||
1296 range_covers_byte(addr, len, PCI_COMMAND)) {
1297 pcibus_t old_addr[PCI_NUM_REGIONS - 1];
1298 int bar;
1299
1300 for (bar = 0; bar < PCI_ROM_SLOT; bar++) {
1301 old_addr[bar] = pdev->io_regions[bar].addr;
1302 }
1303
1304 pci_default_write_config(pdev, addr, val, len);
1305
1306 for (bar = 0; bar < PCI_ROM_SLOT; bar++) {
1307 if (old_addr[bar] != pdev->io_regions[bar].addr &&
1308 vdev->bars[bar].region.size > 0 &&
1309 vdev->bars[bar].region.size < qemu_real_host_page_size()) {
1310 vfio_sub_page_bar_update_mapping(pdev, bar);
1311 }
1312 }
1313 } else {
1314 /* Write everything to QEMU to keep emulated bits correct */
1315 pci_default_write_config(pdev, addr, val, len);
1316 }
1317 }
1318
1319 /*
1320 * Interrupt setup
1321 */
vfio_disable_interrupts(VFIOPCIDevice * vdev)1322 static void vfio_disable_interrupts(VFIOPCIDevice *vdev)
1323 {
1324 /*
1325 * More complicated than it looks. Disabling MSI/X transitions the
1326 * device to INTx mode (if supported). Therefore we need to first
1327 * disable MSI/X and then cleanup by disabling INTx.
1328 */
1329 if (vdev->interrupt == VFIO_INT_MSIX) {
1330 vfio_msix_disable(vdev);
1331 } else if (vdev->interrupt == VFIO_INT_MSI) {
1332 vfio_msi_disable(vdev);
1333 }
1334
1335 if (vdev->interrupt == VFIO_INT_INTx) {
1336 vfio_intx_disable(vdev);
1337 }
1338 }
1339
vfio_msi_setup(VFIOPCIDevice * vdev,int pos,Error ** errp)1340 static int vfio_msi_setup(VFIOPCIDevice *vdev, int pos, Error **errp)
1341 {
1342 uint16_t ctrl;
1343 bool msi_64bit, msi_maskbit;
1344 int ret, entries;
1345 Error *err = NULL;
1346
1347 if (pread(vdev->vbasedev.fd, &ctrl, sizeof(ctrl),
1348 vdev->config_offset + pos + PCI_CAP_FLAGS) != sizeof(ctrl)) {
1349 error_setg_errno(errp, errno, "failed reading MSI PCI_CAP_FLAGS");
1350 return -errno;
1351 }
1352 ctrl = le16_to_cpu(ctrl);
1353
1354 msi_64bit = !!(ctrl & PCI_MSI_FLAGS_64BIT);
1355 msi_maskbit = !!(ctrl & PCI_MSI_FLAGS_MASKBIT);
1356 entries = 1 << ((ctrl & PCI_MSI_FLAGS_QMASK) >> 1);
1357
1358 trace_vfio_msi_setup(vdev->vbasedev.name, pos);
1359
1360 ret = msi_init(&vdev->pdev, pos, entries, msi_64bit, msi_maskbit, &err);
1361 if (ret < 0) {
1362 if (ret == -ENOTSUP) {
1363 return 0;
1364 }
1365 error_propagate_prepend(errp, err, "msi_init failed: ");
1366 return ret;
1367 }
1368 vdev->msi_cap_size = 0xa + (msi_maskbit ? 0xa : 0) + (msi_64bit ? 0x4 : 0);
1369
1370 return 0;
1371 }
1372
vfio_pci_fixup_msix_region(VFIOPCIDevice * vdev)1373 static void vfio_pci_fixup_msix_region(VFIOPCIDevice *vdev)
1374 {
1375 off_t start, end;
1376 VFIORegion *region = &vdev->bars[vdev->msix->table_bar].region;
1377
1378 /*
1379 * If the host driver allows mapping of a MSIX data, we are going to
1380 * do map the entire BAR and emulate MSIX table on top of that.
1381 */
1382 if (vfio_has_region_cap(&vdev->vbasedev, region->nr,
1383 VFIO_REGION_INFO_CAP_MSIX_MAPPABLE)) {
1384 return;
1385 }
1386
1387 /*
1388 * We expect to find a single mmap covering the whole BAR, anything else
1389 * means it's either unsupported or already setup.
1390 */
1391 if (region->nr_mmaps != 1 || region->mmaps[0].offset ||
1392 region->size != region->mmaps[0].size) {
1393 return;
1394 }
1395
1396 /* MSI-X table start and end aligned to host page size */
1397 start = vdev->msix->table_offset & qemu_real_host_page_mask();
1398 end = REAL_HOST_PAGE_ALIGN((uint64_t)vdev->msix->table_offset +
1399 (vdev->msix->entries * PCI_MSIX_ENTRY_SIZE));
1400
1401 /*
1402 * Does the MSI-X table cover the beginning of the BAR? The whole BAR?
1403 * NB - Host page size is necessarily a power of two and so is the PCI
1404 * BAR (not counting EA yet), therefore if we have host page aligned
1405 * @start and @end, then any remainder of the BAR before or after those
1406 * must be at least host page sized and therefore mmap'able.
1407 */
1408 if (!start) {
1409 if (end >= region->size) {
1410 region->nr_mmaps = 0;
1411 g_free(region->mmaps);
1412 region->mmaps = NULL;
1413 trace_vfio_msix_fixup(vdev->vbasedev.name,
1414 vdev->msix->table_bar, 0, 0);
1415 } else {
1416 region->mmaps[0].offset = end;
1417 region->mmaps[0].size = region->size - end;
1418 trace_vfio_msix_fixup(vdev->vbasedev.name,
1419 vdev->msix->table_bar, region->mmaps[0].offset,
1420 region->mmaps[0].offset + region->mmaps[0].size);
1421 }
1422
1423 /* Maybe it's aligned at the end of the BAR */
1424 } else if (end >= region->size) {
1425 region->mmaps[0].size = start;
1426 trace_vfio_msix_fixup(vdev->vbasedev.name,
1427 vdev->msix->table_bar, region->mmaps[0].offset,
1428 region->mmaps[0].offset + region->mmaps[0].size);
1429
1430 /* Otherwise it must split the BAR */
1431 } else {
1432 region->nr_mmaps = 2;
1433 region->mmaps = g_renew(VFIOMmap, region->mmaps, 2);
1434
1435 memcpy(®ion->mmaps[1], ®ion->mmaps[0], sizeof(VFIOMmap));
1436
1437 region->mmaps[0].size = start;
1438 trace_vfio_msix_fixup(vdev->vbasedev.name,
1439 vdev->msix->table_bar, region->mmaps[0].offset,
1440 region->mmaps[0].offset + region->mmaps[0].size);
1441
1442 region->mmaps[1].offset = end;
1443 region->mmaps[1].size = region->size - end;
1444 trace_vfio_msix_fixup(vdev->vbasedev.name,
1445 vdev->msix->table_bar, region->mmaps[1].offset,
1446 region->mmaps[1].offset + region->mmaps[1].size);
1447 }
1448 }
1449
vfio_pci_relocate_msix(VFIOPCIDevice * vdev,Error ** errp)1450 static void vfio_pci_relocate_msix(VFIOPCIDevice *vdev, Error **errp)
1451 {
1452 int target_bar = -1;
1453 size_t msix_sz;
1454
1455 if (!vdev->msix || vdev->msix_relo == OFF_AUTOPCIBAR_OFF) {
1456 return;
1457 }
1458
1459 /* The actual minimum size of MSI-X structures */
1460 msix_sz = (vdev->msix->entries * PCI_MSIX_ENTRY_SIZE) +
1461 (QEMU_ALIGN_UP(vdev->msix->entries, 64) / 8);
1462 /* Round up to host pages, we don't want to share a page */
1463 msix_sz = REAL_HOST_PAGE_ALIGN(msix_sz);
1464 /* PCI BARs must be a power of 2 */
1465 msix_sz = pow2ceil(msix_sz);
1466
1467 if (vdev->msix_relo == OFF_AUTOPCIBAR_AUTO) {
1468 /*
1469 * TODO: Lookup table for known devices.
1470 *
1471 * Logically we might use an algorithm here to select the BAR adding
1472 * the least additional MMIO space, but we cannot programmatically
1473 * predict the driver dependency on BAR ordering or sizing, therefore
1474 * 'auto' becomes a lookup for combinations reported to work.
1475 */
1476 if (target_bar < 0) {
1477 error_setg(errp, "No automatic MSI-X relocation available for "
1478 "device %04x:%04x", vdev->vendor_id, vdev->device_id);
1479 return;
1480 }
1481 } else {
1482 target_bar = (int)(vdev->msix_relo - OFF_AUTOPCIBAR_BAR0);
1483 }
1484
1485 /* I/O port BARs cannot host MSI-X structures */
1486 if (vdev->bars[target_bar].ioport) {
1487 error_setg(errp, "Invalid MSI-X relocation BAR %d, "
1488 "I/O port BAR", target_bar);
1489 return;
1490 }
1491
1492 /* Cannot use a BAR in the "shadow" of a 64-bit BAR */
1493 if (!vdev->bars[target_bar].size &&
1494 target_bar > 0 && vdev->bars[target_bar - 1].mem64) {
1495 error_setg(errp, "Invalid MSI-X relocation BAR %d, "
1496 "consumed by 64-bit BAR %d", target_bar, target_bar - 1);
1497 return;
1498 }
1499
1500 /* 2GB max size for 32-bit BARs, cannot double if already > 1G */
1501 if (vdev->bars[target_bar].size > 1 * GiB &&
1502 !vdev->bars[target_bar].mem64) {
1503 error_setg(errp, "Invalid MSI-X relocation BAR %d, "
1504 "no space to extend 32-bit BAR", target_bar);
1505 return;
1506 }
1507
1508 /*
1509 * If adding a new BAR, test if we can make it 64bit. We make it
1510 * prefetchable since QEMU MSI-X emulation has no read side effects
1511 * and doing so makes mapping more flexible.
1512 */
1513 if (!vdev->bars[target_bar].size) {
1514 if (target_bar < (PCI_ROM_SLOT - 1) &&
1515 !vdev->bars[target_bar + 1].size) {
1516 vdev->bars[target_bar].mem64 = true;
1517 vdev->bars[target_bar].type = PCI_BASE_ADDRESS_MEM_TYPE_64;
1518 }
1519 vdev->bars[target_bar].type |= PCI_BASE_ADDRESS_MEM_PREFETCH;
1520 vdev->bars[target_bar].size = msix_sz;
1521 vdev->msix->table_offset = 0;
1522 } else {
1523 vdev->bars[target_bar].size = MAX(vdev->bars[target_bar].size * 2,
1524 msix_sz * 2);
1525 /*
1526 * Due to above size calc, MSI-X always starts halfway into the BAR,
1527 * which will always be a separate host page.
1528 */
1529 vdev->msix->table_offset = vdev->bars[target_bar].size / 2;
1530 }
1531
1532 vdev->msix->table_bar = target_bar;
1533 vdev->msix->pba_bar = target_bar;
1534 /* Requires 8-byte alignment, but PCI_MSIX_ENTRY_SIZE guarantees that */
1535 vdev->msix->pba_offset = vdev->msix->table_offset +
1536 (vdev->msix->entries * PCI_MSIX_ENTRY_SIZE);
1537
1538 trace_vfio_msix_relo(vdev->vbasedev.name,
1539 vdev->msix->table_bar, vdev->msix->table_offset);
1540 }
1541
1542 /*
1543 * We don't have any control over how pci_add_capability() inserts
1544 * capabilities into the chain. In order to setup MSI-X we need a
1545 * MemoryRegion for the BAR. In order to setup the BAR and not
1546 * attempt to mmap the MSI-X table area, which VFIO won't allow, we
1547 * need to first look for where the MSI-X table lives. So we
1548 * unfortunately split MSI-X setup across two functions.
1549 */
vfio_msix_early_setup(VFIOPCIDevice * vdev,Error ** errp)1550 static void vfio_msix_early_setup(VFIOPCIDevice *vdev, Error **errp)
1551 {
1552 uint8_t pos;
1553 uint16_t ctrl;
1554 uint32_t table, pba;
1555 int ret, fd = vdev->vbasedev.fd;
1556 struct vfio_irq_info irq_info = { .argsz = sizeof(irq_info),
1557 .index = VFIO_PCI_MSIX_IRQ_INDEX };
1558 VFIOMSIXInfo *msix;
1559
1560 pos = pci_find_capability(&vdev->pdev, PCI_CAP_ID_MSIX);
1561 if (!pos) {
1562 return;
1563 }
1564
1565 if (pread(fd, &ctrl, sizeof(ctrl),
1566 vdev->config_offset + pos + PCI_MSIX_FLAGS) != sizeof(ctrl)) {
1567 error_setg_errno(errp, errno, "failed to read PCI MSIX FLAGS");
1568 return;
1569 }
1570
1571 if (pread(fd, &table, sizeof(table),
1572 vdev->config_offset + pos + PCI_MSIX_TABLE) != sizeof(table)) {
1573 error_setg_errno(errp, errno, "failed to read PCI MSIX TABLE");
1574 return;
1575 }
1576
1577 if (pread(fd, &pba, sizeof(pba),
1578 vdev->config_offset + pos + PCI_MSIX_PBA) != sizeof(pba)) {
1579 error_setg_errno(errp, errno, "failed to read PCI MSIX PBA");
1580 return;
1581 }
1582
1583 ctrl = le16_to_cpu(ctrl);
1584 table = le32_to_cpu(table);
1585 pba = le32_to_cpu(pba);
1586
1587 msix = g_malloc0(sizeof(*msix));
1588 msix->table_bar = table & PCI_MSIX_FLAGS_BIRMASK;
1589 msix->table_offset = table & ~PCI_MSIX_FLAGS_BIRMASK;
1590 msix->pba_bar = pba & PCI_MSIX_FLAGS_BIRMASK;
1591 msix->pba_offset = pba & ~PCI_MSIX_FLAGS_BIRMASK;
1592 msix->entries = (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
1593
1594 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_IRQ_INFO, &irq_info);
1595 if (ret < 0) {
1596 error_setg_errno(errp, -ret, "failed to get MSI-X irq info");
1597 g_free(msix);
1598 return;
1599 }
1600
1601 msix->noresize = !!(irq_info.flags & VFIO_IRQ_INFO_NORESIZE);
1602
1603 /*
1604 * Test the size of the pba_offset variable and catch if it extends outside
1605 * of the specified BAR. If it is the case, we need to apply a hardware
1606 * specific quirk if the device is known or we have a broken configuration.
1607 */
1608 if (msix->pba_offset >= vdev->bars[msix->pba_bar].region.size) {
1609 /*
1610 * Chelsio T5 Virtual Function devices are encoded as 0x58xx for T5
1611 * adapters. The T5 hardware returns an incorrect value of 0x8000 for
1612 * the VF PBA offset while the BAR itself is only 8k. The correct value
1613 * is 0x1000, so we hard code that here.
1614 */
1615 if (vdev->vendor_id == PCI_VENDOR_ID_CHELSIO &&
1616 (vdev->device_id & 0xff00) == 0x5800) {
1617 msix->pba_offset = 0x1000;
1618 /*
1619 * BAIDU KUNLUN Virtual Function devices for KUNLUN AI processor
1620 * return an incorrect value of 0x460000 for the VF PBA offset while
1621 * the BAR itself is only 0x10000. The correct value is 0xb400.
1622 */
1623 } else if (vfio_pci_is(vdev, PCI_VENDOR_ID_BAIDU,
1624 PCI_DEVICE_ID_KUNLUN_VF)) {
1625 msix->pba_offset = 0xb400;
1626 } else if (vdev->msix_relo == OFF_AUTOPCIBAR_OFF) {
1627 error_setg(errp, "hardware reports invalid configuration, "
1628 "MSIX PBA outside of specified BAR");
1629 g_free(msix);
1630 return;
1631 }
1632 }
1633
1634 trace_vfio_msix_early_setup(vdev->vbasedev.name, pos, msix->table_bar,
1635 msix->table_offset, msix->entries,
1636 msix->noresize);
1637 vdev->msix = msix;
1638
1639 vfio_pci_fixup_msix_region(vdev);
1640
1641 vfio_pci_relocate_msix(vdev, errp);
1642 }
1643
vfio_msix_setup(VFIOPCIDevice * vdev,int pos,Error ** errp)1644 static int vfio_msix_setup(VFIOPCIDevice *vdev, int pos, Error **errp)
1645 {
1646 int ret;
1647 Error *err = NULL;
1648
1649 vdev->msix->pending = g_new0(unsigned long,
1650 BITS_TO_LONGS(vdev->msix->entries));
1651 ret = msix_init(&vdev->pdev, vdev->msix->entries,
1652 vdev->bars[vdev->msix->table_bar].mr,
1653 vdev->msix->table_bar, vdev->msix->table_offset,
1654 vdev->bars[vdev->msix->pba_bar].mr,
1655 vdev->msix->pba_bar, vdev->msix->pba_offset, pos,
1656 &err);
1657 if (ret < 0) {
1658 if (ret == -ENOTSUP) {
1659 warn_report_err(err);
1660 return 0;
1661 }
1662
1663 error_propagate(errp, err);
1664 return ret;
1665 }
1666
1667 /*
1668 * The PCI spec suggests that devices provide additional alignment for
1669 * MSI-X structures and avoid overlapping non-MSI-X related registers.
1670 * For an assigned device, this hopefully means that emulation of MSI-X
1671 * structures does not affect the performance of the device. If devices
1672 * fail to provide that alignment, a significant performance penalty may
1673 * result, for instance Mellanox MT27500 VFs:
1674 * http://www.spinics.net/lists/kvm/msg125881.html
1675 *
1676 * The PBA is simply not that important for such a serious regression and
1677 * most drivers do not appear to look at it. The solution for this is to
1678 * disable the PBA MemoryRegion unless it's being used. We disable it
1679 * here and only enable it if a masked vector fires through QEMU. As the
1680 * vector-use notifier is called, which occurs on unmask, we test whether
1681 * PBA emulation is needed and again disable if not.
1682 */
1683 memory_region_set_enabled(&vdev->pdev.msix_pba_mmio, false);
1684
1685 /*
1686 * The emulated machine may provide a paravirt interface for MSIX setup
1687 * so it is not strictly necessary to emulate MSIX here. This becomes
1688 * helpful when frequently accessed MMIO registers are located in
1689 * subpages adjacent to the MSIX table but the MSIX data containing page
1690 * cannot be mapped because of a host page size bigger than the MSIX table
1691 * alignment.
1692 */
1693 if (object_property_get_bool(OBJECT(qdev_get_machine()),
1694 "vfio-no-msix-emulation", NULL)) {
1695 memory_region_set_enabled(&vdev->pdev.msix_table_mmio, false);
1696 }
1697
1698 return 0;
1699 }
1700
vfio_teardown_msi(VFIOPCIDevice * vdev)1701 static void vfio_teardown_msi(VFIOPCIDevice *vdev)
1702 {
1703 msi_uninit(&vdev->pdev);
1704
1705 if (vdev->msix) {
1706 msix_uninit(&vdev->pdev,
1707 vdev->bars[vdev->msix->table_bar].mr,
1708 vdev->bars[vdev->msix->pba_bar].mr);
1709 g_free(vdev->msix->pending);
1710 }
1711 }
1712
1713 /*
1714 * Resource setup
1715 */
vfio_mmap_set_enabled(VFIOPCIDevice * vdev,bool enabled)1716 static void vfio_mmap_set_enabled(VFIOPCIDevice *vdev, bool enabled)
1717 {
1718 int i;
1719
1720 for (i = 0; i < PCI_ROM_SLOT; i++) {
1721 vfio_region_mmaps_set_enabled(&vdev->bars[i].region, enabled);
1722 }
1723 }
1724
vfio_bar_prepare(VFIOPCIDevice * vdev,int nr)1725 static void vfio_bar_prepare(VFIOPCIDevice *vdev, int nr)
1726 {
1727 VFIOBAR *bar = &vdev->bars[nr];
1728
1729 uint32_t pci_bar;
1730 int ret;
1731
1732 /* Skip both unimplemented BARs and the upper half of 64bit BARS. */
1733 if (!bar->region.size) {
1734 return;
1735 }
1736
1737 /* Determine what type of BAR this is for registration */
1738 ret = pread(vdev->vbasedev.fd, &pci_bar, sizeof(pci_bar),
1739 vdev->config_offset + PCI_BASE_ADDRESS_0 + (4 * nr));
1740 if (ret != sizeof(pci_bar)) {
1741 error_report("vfio: Failed to read BAR %d (%m)", nr);
1742 return;
1743 }
1744
1745 pci_bar = le32_to_cpu(pci_bar);
1746 bar->ioport = (pci_bar & PCI_BASE_ADDRESS_SPACE_IO);
1747 bar->mem64 = bar->ioport ? 0 : (pci_bar & PCI_BASE_ADDRESS_MEM_TYPE_64);
1748 bar->type = pci_bar & (bar->ioport ? ~PCI_BASE_ADDRESS_IO_MASK :
1749 ~PCI_BASE_ADDRESS_MEM_MASK);
1750 bar->size = bar->region.size;
1751 }
1752
vfio_bars_prepare(VFIOPCIDevice * vdev)1753 static void vfio_bars_prepare(VFIOPCIDevice *vdev)
1754 {
1755 int i;
1756
1757 for (i = 0; i < PCI_ROM_SLOT; i++) {
1758 vfio_bar_prepare(vdev, i);
1759 }
1760 }
1761
vfio_bar_register(VFIOPCIDevice * vdev,int nr)1762 static void vfio_bar_register(VFIOPCIDevice *vdev, int nr)
1763 {
1764 VFIOBAR *bar = &vdev->bars[nr];
1765 char *name;
1766
1767 if (!bar->size) {
1768 return;
1769 }
1770
1771 bar->mr = g_new0(MemoryRegion, 1);
1772 name = g_strdup_printf("%s base BAR %d", vdev->vbasedev.name, nr);
1773 memory_region_init_io(bar->mr, OBJECT(vdev), NULL, NULL, name, bar->size);
1774 g_free(name);
1775
1776 if (bar->region.size) {
1777 memory_region_add_subregion(bar->mr, 0, bar->region.mem);
1778
1779 if (vfio_region_mmap(&bar->region)) {
1780 error_report("Failed to mmap %s BAR %d. Performance may be slow",
1781 vdev->vbasedev.name, nr);
1782 }
1783 }
1784
1785 pci_register_bar(&vdev->pdev, nr, bar->type, bar->mr);
1786 }
1787
vfio_bars_register(VFIOPCIDevice * vdev)1788 static void vfio_bars_register(VFIOPCIDevice *vdev)
1789 {
1790 int i;
1791
1792 for (i = 0; i < PCI_ROM_SLOT; i++) {
1793 vfio_bar_register(vdev, i);
1794 }
1795 }
1796
vfio_bars_exit(VFIOPCIDevice * vdev)1797 static void vfio_bars_exit(VFIOPCIDevice *vdev)
1798 {
1799 int i;
1800
1801 for (i = 0; i < PCI_ROM_SLOT; i++) {
1802 VFIOBAR *bar = &vdev->bars[i];
1803
1804 vfio_bar_quirk_exit(vdev, i);
1805 vfio_region_exit(&bar->region);
1806 if (bar->region.size) {
1807 memory_region_del_subregion(bar->mr, bar->region.mem);
1808 }
1809 }
1810
1811 if (vdev->vga) {
1812 pci_unregister_vga(&vdev->pdev);
1813 vfio_vga_quirk_exit(vdev);
1814 }
1815 }
1816
vfio_bars_finalize(VFIOPCIDevice * vdev)1817 static void vfio_bars_finalize(VFIOPCIDevice *vdev)
1818 {
1819 int i;
1820
1821 for (i = 0; i < PCI_ROM_SLOT; i++) {
1822 VFIOBAR *bar = &vdev->bars[i];
1823
1824 vfio_bar_quirk_finalize(vdev, i);
1825 vfio_region_finalize(&bar->region);
1826 if (bar->mr) {
1827 assert(bar->size);
1828 object_unparent(OBJECT(bar->mr));
1829 g_free(bar->mr);
1830 bar->mr = NULL;
1831 }
1832 }
1833
1834 if (vdev->vga) {
1835 vfio_vga_quirk_finalize(vdev);
1836 for (i = 0; i < ARRAY_SIZE(vdev->vga->region); i++) {
1837 object_unparent(OBJECT(&vdev->vga->region[i].mem));
1838 }
1839 g_free(vdev->vga);
1840 }
1841 }
1842
1843 /*
1844 * General setup
1845 */
vfio_std_cap_max_size(PCIDevice * pdev,uint8_t pos)1846 static uint8_t vfio_std_cap_max_size(PCIDevice *pdev, uint8_t pos)
1847 {
1848 uint8_t tmp;
1849 uint16_t next = PCI_CONFIG_SPACE_SIZE;
1850
1851 for (tmp = pdev->config[PCI_CAPABILITY_LIST]; tmp;
1852 tmp = pdev->config[tmp + PCI_CAP_LIST_NEXT]) {
1853 if (tmp > pos && tmp < next) {
1854 next = tmp;
1855 }
1856 }
1857
1858 return next - pos;
1859 }
1860
1861
vfio_ext_cap_max_size(const uint8_t * config,uint16_t pos)1862 static uint16_t vfio_ext_cap_max_size(const uint8_t *config, uint16_t pos)
1863 {
1864 uint16_t tmp, next = PCIE_CONFIG_SPACE_SIZE;
1865
1866 for (tmp = PCI_CONFIG_SPACE_SIZE; tmp;
1867 tmp = PCI_EXT_CAP_NEXT(pci_get_long(config + tmp))) {
1868 if (tmp > pos && tmp < next) {
1869 next = tmp;
1870 }
1871 }
1872
1873 return next - pos;
1874 }
1875
vfio_set_word_bits(uint8_t * buf,uint16_t val,uint16_t mask)1876 static void vfio_set_word_bits(uint8_t *buf, uint16_t val, uint16_t mask)
1877 {
1878 pci_set_word(buf, (pci_get_word(buf) & ~mask) | val);
1879 }
1880
vfio_add_emulated_word(VFIOPCIDevice * vdev,int pos,uint16_t val,uint16_t mask)1881 static void vfio_add_emulated_word(VFIOPCIDevice *vdev, int pos,
1882 uint16_t val, uint16_t mask)
1883 {
1884 vfio_set_word_bits(vdev->pdev.config + pos, val, mask);
1885 vfio_set_word_bits(vdev->pdev.wmask + pos, ~mask, mask);
1886 vfio_set_word_bits(vdev->emulated_config_bits + pos, mask, mask);
1887 }
1888
vfio_set_long_bits(uint8_t * buf,uint32_t val,uint32_t mask)1889 static void vfio_set_long_bits(uint8_t *buf, uint32_t val, uint32_t mask)
1890 {
1891 pci_set_long(buf, (pci_get_long(buf) & ~mask) | val);
1892 }
1893
vfio_add_emulated_long(VFIOPCIDevice * vdev,int pos,uint32_t val,uint32_t mask)1894 static void vfio_add_emulated_long(VFIOPCIDevice *vdev, int pos,
1895 uint32_t val, uint32_t mask)
1896 {
1897 vfio_set_long_bits(vdev->pdev.config + pos, val, mask);
1898 vfio_set_long_bits(vdev->pdev.wmask + pos, ~mask, mask);
1899 vfio_set_long_bits(vdev->emulated_config_bits + pos, mask, mask);
1900 }
1901
vfio_pci_enable_rp_atomics(VFIOPCIDevice * vdev)1902 static void vfio_pci_enable_rp_atomics(VFIOPCIDevice *vdev)
1903 {
1904 struct vfio_device_info_cap_pci_atomic_comp *cap;
1905 g_autofree struct vfio_device_info *info = NULL;
1906 PCIBus *bus = pci_get_bus(&vdev->pdev);
1907 PCIDevice *parent = bus->parent_dev;
1908 struct vfio_info_cap_header *hdr;
1909 uint32_t mask = 0;
1910 uint8_t *pos;
1911
1912 /*
1913 * PCIe Atomic Ops completer support is only added automatically for single
1914 * function devices downstream of a root port supporting DEVCAP2. Support
1915 * is added during realize and, if added, removed during device exit. The
1916 * single function requirement avoids conflicting requirements should a
1917 * slot be composed of multiple devices with differing capabilities.
1918 */
1919 if (pci_bus_is_root(bus) || !parent || !parent->exp.exp_cap ||
1920 pcie_cap_get_type(parent) != PCI_EXP_TYPE_ROOT_PORT ||
1921 pcie_cap_get_version(parent) != PCI_EXP_FLAGS_VER2 ||
1922 vdev->pdev.devfn ||
1923 vdev->pdev.cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
1924 return;
1925 }
1926
1927 pos = parent->config + parent->exp.exp_cap + PCI_EXP_DEVCAP2;
1928
1929 /* Abort if there'a already an Atomic Ops configuration on the root port */
1930 if (pci_get_long(pos) & (PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
1931 PCI_EXP_DEVCAP2_ATOMIC_COMP64 |
1932 PCI_EXP_DEVCAP2_ATOMIC_COMP128)) {
1933 return;
1934 }
1935
1936 info = vfio_get_device_info(vdev->vbasedev.fd);
1937 if (!info) {
1938 return;
1939 }
1940
1941 hdr = vfio_get_device_info_cap(info, VFIO_DEVICE_INFO_CAP_PCI_ATOMIC_COMP);
1942 if (!hdr) {
1943 return;
1944 }
1945
1946 cap = (void *)hdr;
1947 if (cap->flags & VFIO_PCI_ATOMIC_COMP32) {
1948 mask |= PCI_EXP_DEVCAP2_ATOMIC_COMP32;
1949 }
1950 if (cap->flags & VFIO_PCI_ATOMIC_COMP64) {
1951 mask |= PCI_EXP_DEVCAP2_ATOMIC_COMP64;
1952 }
1953 if (cap->flags & VFIO_PCI_ATOMIC_COMP128) {
1954 mask |= PCI_EXP_DEVCAP2_ATOMIC_COMP128;
1955 }
1956
1957 if (!mask) {
1958 return;
1959 }
1960
1961 pci_long_test_and_set_mask(pos, mask);
1962 vdev->clear_parent_atomics_on_exit = true;
1963 }
1964
vfio_pci_disable_rp_atomics(VFIOPCIDevice * vdev)1965 static void vfio_pci_disable_rp_atomics(VFIOPCIDevice *vdev)
1966 {
1967 if (vdev->clear_parent_atomics_on_exit) {
1968 PCIDevice *parent = pci_get_bus(&vdev->pdev)->parent_dev;
1969 uint8_t *pos = parent->config + parent->exp.exp_cap + PCI_EXP_DEVCAP2;
1970
1971 pci_long_test_and_clear_mask(pos, PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
1972 PCI_EXP_DEVCAP2_ATOMIC_COMP64 |
1973 PCI_EXP_DEVCAP2_ATOMIC_COMP128);
1974 }
1975 }
1976
vfio_setup_pcie_cap(VFIOPCIDevice * vdev,int pos,uint8_t size,Error ** errp)1977 static int vfio_setup_pcie_cap(VFIOPCIDevice *vdev, int pos, uint8_t size,
1978 Error **errp)
1979 {
1980 uint16_t flags;
1981 uint8_t type;
1982
1983 flags = pci_get_word(vdev->pdev.config + pos + PCI_CAP_FLAGS);
1984 type = (flags & PCI_EXP_FLAGS_TYPE) >> 4;
1985
1986 if (type != PCI_EXP_TYPE_ENDPOINT &&
1987 type != PCI_EXP_TYPE_LEG_END &&
1988 type != PCI_EXP_TYPE_RC_END) {
1989
1990 error_setg(errp, "assignment of PCIe type 0x%x "
1991 "devices is not currently supported", type);
1992 return -EINVAL;
1993 }
1994
1995 if (!pci_bus_is_express(pci_get_bus(&vdev->pdev))) {
1996 PCIBus *bus = pci_get_bus(&vdev->pdev);
1997 PCIDevice *bridge;
1998
1999 /*
2000 * Traditionally PCI device assignment exposes the PCIe capability
2001 * as-is on non-express buses. The reason being that some drivers
2002 * simply assume that it's there, for example tg3. However when
2003 * we're running on a native PCIe machine type, like Q35, we need
2004 * to hide the PCIe capability. The reason for this is twofold;
2005 * first Windows guests get a Code 10 error when the PCIe capability
2006 * is exposed in this configuration. Therefore express devices won't
2007 * work at all unless they're attached to express buses in the VM.
2008 * Second, a native PCIe machine introduces the possibility of fine
2009 * granularity IOMMUs supporting both translation and isolation.
2010 * Guest code to discover the IOMMU visibility of a device, such as
2011 * IOMMU grouping code on Linux, is very aware of device types and
2012 * valid transitions between bus types. An express device on a non-
2013 * express bus is not a valid combination on bare metal systems.
2014 *
2015 * Drivers that require a PCIe capability to make the device
2016 * functional are simply going to need to have their devices placed
2017 * on a PCIe bus in the VM.
2018 */
2019 while (!pci_bus_is_root(bus)) {
2020 bridge = pci_bridge_get_device(bus);
2021 bus = pci_get_bus(bridge);
2022 }
2023
2024 if (pci_bus_is_express(bus)) {
2025 return 0;
2026 }
2027
2028 } else if (pci_bus_is_root(pci_get_bus(&vdev->pdev))) {
2029 /*
2030 * On a Root Complex bus Endpoints become Root Complex Integrated
2031 * Endpoints, which changes the type and clears the LNK & LNK2 fields.
2032 */
2033 if (type == PCI_EXP_TYPE_ENDPOINT) {
2034 vfio_add_emulated_word(vdev, pos + PCI_CAP_FLAGS,
2035 PCI_EXP_TYPE_RC_END << 4,
2036 PCI_EXP_FLAGS_TYPE);
2037
2038 /* Link Capabilities, Status, and Control goes away */
2039 if (size > PCI_EXP_LNKCTL) {
2040 vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP, 0, ~0);
2041 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL, 0, ~0);
2042 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKSTA, 0, ~0);
2043
2044 #ifndef PCI_EXP_LNKCAP2
2045 #define PCI_EXP_LNKCAP2 44
2046 #endif
2047 #ifndef PCI_EXP_LNKSTA2
2048 #define PCI_EXP_LNKSTA2 50
2049 #endif
2050 /* Link 2 Capabilities, Status, and Control goes away */
2051 if (size > PCI_EXP_LNKCAP2) {
2052 vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP2, 0, ~0);
2053 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL2, 0, ~0);
2054 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKSTA2, 0, ~0);
2055 }
2056 }
2057
2058 } else if (type == PCI_EXP_TYPE_LEG_END) {
2059 /*
2060 * Legacy endpoints don't belong on the root complex. Windows
2061 * seems to be happier with devices if we skip the capability.
2062 */
2063 return 0;
2064 }
2065
2066 } else {
2067 /*
2068 * Convert Root Complex Integrated Endpoints to regular endpoints.
2069 * These devices don't support LNK/LNK2 capabilities, so make them up.
2070 */
2071 if (type == PCI_EXP_TYPE_RC_END) {
2072 vfio_add_emulated_word(vdev, pos + PCI_CAP_FLAGS,
2073 PCI_EXP_TYPE_ENDPOINT << 4,
2074 PCI_EXP_FLAGS_TYPE);
2075 vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP,
2076 QEMU_PCI_EXP_LNKCAP_MLW(QEMU_PCI_EXP_LNK_X1) |
2077 QEMU_PCI_EXP_LNKCAP_MLS(QEMU_PCI_EXP_LNK_2_5GT), ~0);
2078 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL, 0, ~0);
2079 }
2080
2081 vfio_pci_enable_rp_atomics(vdev);
2082 }
2083
2084 /*
2085 * Intel 82599 SR-IOV VFs report an invalid PCIe capability version 0
2086 * (Niantic errate #35) causing Windows to error with a Code 10 for the
2087 * device on Q35. Fixup any such devices to report version 1. If we
2088 * were to remove the capability entirely the guest would lose extended
2089 * config space.
2090 */
2091 if ((flags & PCI_EXP_FLAGS_VERS) == 0) {
2092 vfio_add_emulated_word(vdev, pos + PCI_CAP_FLAGS,
2093 1, PCI_EXP_FLAGS_VERS);
2094 }
2095
2096 pos = pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size,
2097 errp);
2098 if (pos < 0) {
2099 return pos;
2100 }
2101
2102 vdev->pdev.exp.exp_cap = pos;
2103
2104 return pos;
2105 }
2106
vfio_check_pcie_flr(VFIOPCIDevice * vdev,uint8_t pos)2107 static void vfio_check_pcie_flr(VFIOPCIDevice *vdev, uint8_t pos)
2108 {
2109 uint32_t cap = pci_get_long(vdev->pdev.config + pos + PCI_EXP_DEVCAP);
2110
2111 if (cap & PCI_EXP_DEVCAP_FLR) {
2112 trace_vfio_check_pcie_flr(vdev->vbasedev.name);
2113 vdev->has_flr = true;
2114 }
2115 }
2116
vfio_check_pm_reset(VFIOPCIDevice * vdev,uint8_t pos)2117 static void vfio_check_pm_reset(VFIOPCIDevice *vdev, uint8_t pos)
2118 {
2119 uint16_t csr = pci_get_word(vdev->pdev.config + pos + PCI_PM_CTRL);
2120
2121 if (!(csr & PCI_PM_CTRL_NO_SOFT_RESET)) {
2122 trace_vfio_check_pm_reset(vdev->vbasedev.name);
2123 vdev->has_pm_reset = true;
2124 }
2125 }
2126
vfio_check_af_flr(VFIOPCIDevice * vdev,uint8_t pos)2127 static void vfio_check_af_flr(VFIOPCIDevice *vdev, uint8_t pos)
2128 {
2129 uint8_t cap = pci_get_byte(vdev->pdev.config + pos + PCI_AF_CAP);
2130
2131 if ((cap & PCI_AF_CAP_TP) && (cap & PCI_AF_CAP_FLR)) {
2132 trace_vfio_check_af_flr(vdev->vbasedev.name);
2133 vdev->has_flr = true;
2134 }
2135 }
2136
vfio_add_std_cap(VFIOPCIDevice * vdev,uint8_t pos,Error ** errp)2137 static int vfio_add_std_cap(VFIOPCIDevice *vdev, uint8_t pos, Error **errp)
2138 {
2139 ERRP_GUARD();
2140 PCIDevice *pdev = &vdev->pdev;
2141 uint8_t cap_id, next, size;
2142 int ret;
2143
2144 cap_id = pdev->config[pos];
2145 next = pdev->config[pos + PCI_CAP_LIST_NEXT];
2146
2147 /*
2148 * If it becomes important to configure capabilities to their actual
2149 * size, use this as the default when it's something we don't recognize.
2150 * Since QEMU doesn't actually handle many of the config accesses,
2151 * exact size doesn't seem worthwhile.
2152 */
2153 size = vfio_std_cap_max_size(pdev, pos);
2154
2155 /*
2156 * pci_add_capability always inserts the new capability at the head
2157 * of the chain. Therefore to end up with a chain that matches the
2158 * physical device, we insert from the end by making this recursive.
2159 * This is also why we pre-calculate size above as cached config space
2160 * will be changed as we unwind the stack.
2161 */
2162 if (next) {
2163 ret = vfio_add_std_cap(vdev, next, errp);
2164 if (ret) {
2165 return ret;
2166 }
2167 } else {
2168 /* Begin the rebuild, use QEMU emulated list bits */
2169 pdev->config[PCI_CAPABILITY_LIST] = 0;
2170 vdev->emulated_config_bits[PCI_CAPABILITY_LIST] = 0xff;
2171 vdev->emulated_config_bits[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
2172
2173 ret = vfio_add_virt_caps(vdev, errp);
2174 if (ret) {
2175 return ret;
2176 }
2177 }
2178
2179 /* Scale down size, esp in case virt caps were added above */
2180 size = MIN(size, vfio_std_cap_max_size(pdev, pos));
2181
2182 /* Use emulated next pointer to allow dropping caps */
2183 pci_set_byte(vdev->emulated_config_bits + pos + PCI_CAP_LIST_NEXT, 0xff);
2184
2185 switch (cap_id) {
2186 case PCI_CAP_ID_MSI:
2187 ret = vfio_msi_setup(vdev, pos, errp);
2188 break;
2189 case PCI_CAP_ID_EXP:
2190 vfio_check_pcie_flr(vdev, pos);
2191 ret = vfio_setup_pcie_cap(vdev, pos, size, errp);
2192 break;
2193 case PCI_CAP_ID_MSIX:
2194 ret = vfio_msix_setup(vdev, pos, errp);
2195 break;
2196 case PCI_CAP_ID_PM:
2197 vfio_check_pm_reset(vdev, pos);
2198 vdev->pm_cap = pos;
2199 ret = pci_add_capability(pdev, cap_id, pos, size, errp);
2200 break;
2201 case PCI_CAP_ID_AF:
2202 vfio_check_af_flr(vdev, pos);
2203 ret = pci_add_capability(pdev, cap_id, pos, size, errp);
2204 break;
2205 default:
2206 ret = pci_add_capability(pdev, cap_id, pos, size, errp);
2207 break;
2208 }
2209
2210 if (ret < 0) {
2211 error_prepend(errp,
2212 "failed to add PCI capability 0x%x[0x%x]@0x%x: ",
2213 cap_id, size, pos);
2214 return ret;
2215 }
2216
2217 return 0;
2218 }
2219
vfio_setup_rebar_ecap(VFIOPCIDevice * vdev,uint16_t pos)2220 static int vfio_setup_rebar_ecap(VFIOPCIDevice *vdev, uint16_t pos)
2221 {
2222 uint32_t ctrl;
2223 int i, nbar;
2224
2225 ctrl = pci_get_long(vdev->pdev.config + pos + PCI_REBAR_CTRL);
2226 nbar = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >> PCI_REBAR_CTRL_NBAR_SHIFT;
2227
2228 for (i = 0; i < nbar; i++) {
2229 uint32_t cap;
2230 int size;
2231
2232 ctrl = pci_get_long(vdev->pdev.config + pos + PCI_REBAR_CTRL + (i * 8));
2233 size = (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> PCI_REBAR_CTRL_BAR_SHIFT;
2234
2235 /* The cap register reports sizes 1MB to 128TB, with 4 reserved bits */
2236 cap = size <= 27 ? 1U << (size + 4) : 0;
2237
2238 /*
2239 * The PCIe spec (v6.0.1, 7.8.6) requires HW to support at least one
2240 * size in the range 1MB to 512GB. We intend to mask all sizes except
2241 * the one currently enabled in the size field, therefore if it's
2242 * outside the range, hide the whole capability as this virtualization
2243 * trick won't work. If >512GB resizable BARs start to appear, we
2244 * might need an opt-in or reservation scheme in the kernel.
2245 */
2246 if (!(cap & PCI_REBAR_CAP_SIZES)) {
2247 return -EINVAL;
2248 }
2249
2250 /* Hide all sizes reported in the ctrl reg per above requirement. */
2251 ctrl &= (PCI_REBAR_CTRL_BAR_SIZE |
2252 PCI_REBAR_CTRL_NBAR_MASK |
2253 PCI_REBAR_CTRL_BAR_IDX);
2254
2255 /*
2256 * The BAR size field is RW, however we've mangled the capability
2257 * register such that we only report a single size, ie. the current
2258 * BAR size. A write of an unsupported value is undefined, therefore
2259 * the register field is essentially RO.
2260 */
2261 vfio_add_emulated_long(vdev, pos + PCI_REBAR_CAP + (i * 8), cap, ~0);
2262 vfio_add_emulated_long(vdev, pos + PCI_REBAR_CTRL + (i * 8), ctrl, ~0);
2263 }
2264
2265 return 0;
2266 }
2267
vfio_add_ext_cap(VFIOPCIDevice * vdev)2268 static void vfio_add_ext_cap(VFIOPCIDevice *vdev)
2269 {
2270 PCIDevice *pdev = &vdev->pdev;
2271 uint32_t header;
2272 uint16_t cap_id, next, size;
2273 uint8_t cap_ver;
2274 uint8_t *config;
2275
2276 /* Only add extended caps if we have them and the guest can see them */
2277 if (!pci_is_express(pdev) || !pci_bus_is_express(pci_get_bus(pdev)) ||
2278 !pci_get_long(pdev->config + PCI_CONFIG_SPACE_SIZE)) {
2279 return;
2280 }
2281
2282 /*
2283 * pcie_add_capability always inserts the new capability at the tail
2284 * of the chain. Therefore to end up with a chain that matches the
2285 * physical device, we cache the config space to avoid overwriting
2286 * the original config space when we parse the extended capabilities.
2287 */
2288 config = g_memdup(pdev->config, vdev->config_size);
2289
2290 /*
2291 * Extended capabilities are chained with each pointing to the next, so we
2292 * can drop anything other than the head of the chain simply by modifying
2293 * the previous next pointer. Seed the head of the chain here such that
2294 * we can simply skip any capabilities we want to drop below, regardless
2295 * of their position in the chain. If this stub capability still exists
2296 * after we add the capabilities we want to expose, update the capability
2297 * ID to zero. Note that we cannot seed with the capability header being
2298 * zero as this conflicts with definition of an absent capability chain
2299 * and prevents capabilities beyond the head of the list from being added.
2300 * By replacing the dummy capability ID with zero after walking the device
2301 * chain, we also transparently mark extended capabilities as absent if
2302 * no capabilities were added. Note that the PCIe spec defines an absence
2303 * of extended capabilities to be determined by a value of zero for the
2304 * capability ID, version, AND next pointer. A non-zero next pointer
2305 * should be sufficient to indicate additional capabilities are present,
2306 * which will occur if we call pcie_add_capability() below. The entire
2307 * first dword is emulated to support this.
2308 *
2309 * NB. The kernel side does similar masking, so be prepared that our
2310 * view of the device may also contain a capability ID zero in the head
2311 * of the chain. Skip it for the same reason that we cannot seed the
2312 * chain with a zero capability.
2313 */
2314 pci_set_long(pdev->config + PCI_CONFIG_SPACE_SIZE,
2315 PCI_EXT_CAP(0xFFFF, 0, 0));
2316 pci_set_long(pdev->wmask + PCI_CONFIG_SPACE_SIZE, 0);
2317 pci_set_long(vdev->emulated_config_bits + PCI_CONFIG_SPACE_SIZE, ~0);
2318
2319 for (next = PCI_CONFIG_SPACE_SIZE; next;
2320 next = PCI_EXT_CAP_NEXT(pci_get_long(config + next))) {
2321 header = pci_get_long(config + next);
2322 cap_id = PCI_EXT_CAP_ID(header);
2323 cap_ver = PCI_EXT_CAP_VER(header);
2324
2325 /*
2326 * If it becomes important to configure extended capabilities to their
2327 * actual size, use this as the default when it's something we don't
2328 * recognize. Since QEMU doesn't actually handle many of the config
2329 * accesses, exact size doesn't seem worthwhile.
2330 */
2331 size = vfio_ext_cap_max_size(config, next);
2332
2333 /* Use emulated next pointer to allow dropping extended caps */
2334 pci_long_test_and_set_mask(vdev->emulated_config_bits + next,
2335 PCI_EXT_CAP_NEXT_MASK);
2336
2337 switch (cap_id) {
2338 case 0: /* kernel masked capability */
2339 case PCI_EXT_CAP_ID_SRIOV: /* Read-only VF BARs confuse OVMF */
2340 case PCI_EXT_CAP_ID_ARI: /* XXX Needs next function virtualization */
2341 trace_vfio_add_ext_cap_dropped(vdev->vbasedev.name, cap_id, next);
2342 break;
2343 case PCI_EXT_CAP_ID_REBAR:
2344 if (!vfio_setup_rebar_ecap(vdev, next)) {
2345 pcie_add_capability(pdev, cap_id, cap_ver, next, size);
2346 }
2347 break;
2348 default:
2349 pcie_add_capability(pdev, cap_id, cap_ver, next, size);
2350 }
2351
2352 }
2353
2354 /* Cleanup chain head ID if necessary */
2355 if (pci_get_word(pdev->config + PCI_CONFIG_SPACE_SIZE) == 0xFFFF) {
2356 pci_set_word(pdev->config + PCI_CONFIG_SPACE_SIZE, 0);
2357 }
2358
2359 g_free(config);
2360 return;
2361 }
2362
vfio_add_capabilities(VFIOPCIDevice * vdev,Error ** errp)2363 static int vfio_add_capabilities(VFIOPCIDevice *vdev, Error **errp)
2364 {
2365 PCIDevice *pdev = &vdev->pdev;
2366 int ret;
2367
2368 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST) ||
2369 !pdev->config[PCI_CAPABILITY_LIST]) {
2370 return 0; /* Nothing to add */
2371 }
2372
2373 ret = vfio_add_std_cap(vdev, pdev->config[PCI_CAPABILITY_LIST], errp);
2374 if (ret) {
2375 return ret;
2376 }
2377
2378 vfio_add_ext_cap(vdev);
2379 return 0;
2380 }
2381
vfio_pci_pre_reset(VFIOPCIDevice * vdev)2382 void vfio_pci_pre_reset(VFIOPCIDevice *vdev)
2383 {
2384 PCIDevice *pdev = &vdev->pdev;
2385 uint16_t cmd;
2386
2387 vfio_disable_interrupts(vdev);
2388
2389 /* Make sure the device is in D0 */
2390 if (vdev->pm_cap) {
2391 uint16_t pmcsr;
2392 uint8_t state;
2393
2394 pmcsr = vfio_pci_read_config(pdev, vdev->pm_cap + PCI_PM_CTRL, 2);
2395 state = pmcsr & PCI_PM_CTRL_STATE_MASK;
2396 if (state) {
2397 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
2398 vfio_pci_write_config(pdev, vdev->pm_cap + PCI_PM_CTRL, pmcsr, 2);
2399 /* vfio handles the necessary delay here */
2400 pmcsr = vfio_pci_read_config(pdev, vdev->pm_cap + PCI_PM_CTRL, 2);
2401 state = pmcsr & PCI_PM_CTRL_STATE_MASK;
2402 if (state) {
2403 error_report("vfio: Unable to power on device, stuck in D%d",
2404 state);
2405 }
2406 }
2407 }
2408
2409 /*
2410 * Stop any ongoing DMA by disconnecting I/O, MMIO, and bus master.
2411 * Also put INTx Disable in known state.
2412 */
2413 cmd = vfio_pci_read_config(pdev, PCI_COMMAND, 2);
2414 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
2415 PCI_COMMAND_INTX_DISABLE);
2416 vfio_pci_write_config(pdev, PCI_COMMAND, cmd, 2);
2417 }
2418
vfio_pci_post_reset(VFIOPCIDevice * vdev)2419 void vfio_pci_post_reset(VFIOPCIDevice *vdev)
2420 {
2421 Error *err = NULL;
2422 int nr;
2423
2424 vfio_intx_enable(vdev, &err);
2425 if (err) {
2426 error_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name);
2427 }
2428
2429 for (nr = 0; nr < PCI_NUM_REGIONS - 1; ++nr) {
2430 off_t addr = vdev->config_offset + PCI_BASE_ADDRESS_0 + (4 * nr);
2431 uint32_t val = 0;
2432 uint32_t len = sizeof(val);
2433
2434 if (pwrite(vdev->vbasedev.fd, &val, len, addr) != len) {
2435 error_report("%s(%s) reset bar %d failed: %m", __func__,
2436 vdev->vbasedev.name, nr);
2437 }
2438 }
2439
2440 vfio_quirk_reset(vdev);
2441 }
2442
vfio_pci_host_match(PCIHostDeviceAddress * addr,const char * name)2443 bool vfio_pci_host_match(PCIHostDeviceAddress *addr, const char *name)
2444 {
2445 char tmp[13];
2446
2447 sprintf(tmp, "%04x:%02x:%02x.%1x", addr->domain,
2448 addr->bus, addr->slot, addr->function);
2449
2450 return (strcmp(tmp, name) == 0);
2451 }
2452
vfio_pci_get_pci_hot_reset_info(VFIOPCIDevice * vdev,struct vfio_pci_hot_reset_info ** info_p)2453 int vfio_pci_get_pci_hot_reset_info(VFIOPCIDevice *vdev,
2454 struct vfio_pci_hot_reset_info **info_p)
2455 {
2456 struct vfio_pci_hot_reset_info *info;
2457 int ret, count;
2458
2459 assert(info_p && !*info_p);
2460
2461 info = g_malloc0(sizeof(*info));
2462 info->argsz = sizeof(*info);
2463
2464 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_PCI_HOT_RESET_INFO, info);
2465 if (ret && errno != ENOSPC) {
2466 ret = -errno;
2467 g_free(info);
2468 if (!vdev->has_pm_reset) {
2469 error_report("vfio: Cannot reset device %s, "
2470 "no available reset mechanism.", vdev->vbasedev.name);
2471 }
2472 return ret;
2473 }
2474
2475 count = info->count;
2476 info = g_realloc(info, sizeof(*info) + (count * sizeof(info->devices[0])));
2477 info->argsz = sizeof(*info) + (count * sizeof(info->devices[0]));
2478
2479 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_PCI_HOT_RESET_INFO, info);
2480 if (ret) {
2481 ret = -errno;
2482 g_free(info);
2483 error_report("vfio: hot reset info failed: %m");
2484 return ret;
2485 }
2486
2487 *info_p = info;
2488 return 0;
2489 }
2490
vfio_pci_hot_reset(VFIOPCIDevice * vdev,bool single)2491 static int vfio_pci_hot_reset(VFIOPCIDevice *vdev, bool single)
2492 {
2493 VFIODevice *vbasedev = &vdev->vbasedev;
2494 const VFIOIOMMUClass *ops = vbasedev->bcontainer->ops;
2495
2496 return ops->pci_hot_reset(vbasedev, single);
2497 }
2498
2499 /*
2500 * We want to differentiate hot reset of multiple in-use devices vs hot reset
2501 * of a single in-use device. VFIO_DEVICE_RESET will already handle the case
2502 * of doing hot resets when there is only a single device per bus. The in-use
2503 * here refers to how many VFIODevices are affected. A hot reset that affects
2504 * multiple devices, but only a single in-use device, means that we can call
2505 * it from our bus ->reset() callback since the extent is effectively a single
2506 * device. This allows us to make use of it in the hotplug path. When there
2507 * are multiple in-use devices, we can only trigger the hot reset during a
2508 * system reset and thus from our reset handler. We separate _one vs _multi
2509 * here so that we don't overlap and do a double reset on the system reset
2510 * path where both our reset handler and ->reset() callback are used. Calling
2511 * _one() will only do a hot reset for the one in-use devices case, calling
2512 * _multi() will do nothing if a _one() would have been sufficient.
2513 */
vfio_pci_hot_reset_one(VFIOPCIDevice * vdev)2514 static int vfio_pci_hot_reset_one(VFIOPCIDevice *vdev)
2515 {
2516 return vfio_pci_hot_reset(vdev, true);
2517 }
2518
vfio_pci_hot_reset_multi(VFIODevice * vbasedev)2519 static int vfio_pci_hot_reset_multi(VFIODevice *vbasedev)
2520 {
2521 VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev);
2522 return vfio_pci_hot_reset(vdev, false);
2523 }
2524
vfio_pci_compute_needs_reset(VFIODevice * vbasedev)2525 static void vfio_pci_compute_needs_reset(VFIODevice *vbasedev)
2526 {
2527 VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev);
2528 if (!vbasedev->reset_works || (!vdev->has_flr && vdev->has_pm_reset)) {
2529 vbasedev->needs_reset = true;
2530 }
2531 }
2532
vfio_pci_get_object(VFIODevice * vbasedev)2533 static Object *vfio_pci_get_object(VFIODevice *vbasedev)
2534 {
2535 VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev);
2536
2537 return OBJECT(vdev);
2538 }
2539
vfio_msix_present(void * opaque,int version_id)2540 static bool vfio_msix_present(void *opaque, int version_id)
2541 {
2542 PCIDevice *pdev = opaque;
2543
2544 return msix_present(pdev);
2545 }
2546
vfio_display_migration_needed(void * opaque)2547 static bool vfio_display_migration_needed(void *opaque)
2548 {
2549 VFIOPCIDevice *vdev = opaque;
2550
2551 /*
2552 * We need to migrate the VFIODisplay object if ramfb *migration* was
2553 * explicitly requested (in which case we enforced both ramfb=on and
2554 * display=on), or ramfb migration was left at the default "auto"
2555 * setting, and *ramfb* was explicitly requested (in which case we
2556 * enforced display=on).
2557 */
2558 return vdev->ramfb_migrate == ON_OFF_AUTO_ON ||
2559 (vdev->ramfb_migrate == ON_OFF_AUTO_AUTO && vdev->enable_ramfb);
2560 }
2561
2562 static const VMStateDescription vmstate_vfio_display = {
2563 .name = "VFIOPCIDevice/VFIODisplay",
2564 .version_id = 1,
2565 .minimum_version_id = 1,
2566 .needed = vfio_display_migration_needed,
2567 .fields = (const VMStateField[]){
2568 VMSTATE_STRUCT_POINTER(dpy, VFIOPCIDevice, vfio_display_vmstate,
2569 VFIODisplay),
2570 VMSTATE_END_OF_LIST()
2571 }
2572 };
2573
2574 static const VMStateDescription vmstate_vfio_pci_config = {
2575 .name = "VFIOPCIDevice",
2576 .version_id = 1,
2577 .minimum_version_id = 1,
2578 .fields = (const VMStateField[]) {
2579 VMSTATE_PCI_DEVICE(pdev, VFIOPCIDevice),
2580 VMSTATE_MSIX_TEST(pdev, VFIOPCIDevice, vfio_msix_present),
2581 VMSTATE_END_OF_LIST()
2582 },
2583 .subsections = (const VMStateDescription * const []) {
2584 &vmstate_vfio_display,
2585 NULL
2586 }
2587 };
2588
vfio_pci_save_config(VFIODevice * vbasedev,QEMUFile * f)2589 static void vfio_pci_save_config(VFIODevice *vbasedev, QEMUFile *f)
2590 {
2591 VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev);
2592
2593 vmstate_save_state(f, &vmstate_vfio_pci_config, vdev, NULL);
2594 }
2595
vfio_pci_load_config(VFIODevice * vbasedev,QEMUFile * f)2596 static int vfio_pci_load_config(VFIODevice *vbasedev, QEMUFile *f)
2597 {
2598 VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev);
2599 PCIDevice *pdev = &vdev->pdev;
2600 pcibus_t old_addr[PCI_NUM_REGIONS - 1];
2601 int bar, ret;
2602
2603 for (bar = 0; bar < PCI_ROM_SLOT; bar++) {
2604 old_addr[bar] = pdev->io_regions[bar].addr;
2605 }
2606
2607 ret = vmstate_load_state(f, &vmstate_vfio_pci_config, vdev, 1);
2608 if (ret) {
2609 return ret;
2610 }
2611
2612 vfio_pci_write_config(pdev, PCI_COMMAND,
2613 pci_get_word(pdev->config + PCI_COMMAND), 2);
2614
2615 for (bar = 0; bar < PCI_ROM_SLOT; bar++) {
2616 /*
2617 * The address may not be changed in some scenarios
2618 * (e.g. the VF driver isn't loaded in VM).
2619 */
2620 if (old_addr[bar] != pdev->io_regions[bar].addr &&
2621 vdev->bars[bar].region.size > 0 &&
2622 vdev->bars[bar].region.size < qemu_real_host_page_size()) {
2623 vfio_sub_page_bar_update_mapping(pdev, bar);
2624 }
2625 }
2626
2627 if (msi_enabled(pdev)) {
2628 vfio_msi_enable(vdev);
2629 } else if (msix_enabled(pdev)) {
2630 vfio_msix_enable(vdev);
2631 }
2632
2633 return ret;
2634 }
2635
2636 static VFIODeviceOps vfio_pci_ops = {
2637 .vfio_compute_needs_reset = vfio_pci_compute_needs_reset,
2638 .vfio_hot_reset_multi = vfio_pci_hot_reset_multi,
2639 .vfio_eoi = vfio_intx_eoi,
2640 .vfio_get_object = vfio_pci_get_object,
2641 .vfio_save_config = vfio_pci_save_config,
2642 .vfio_load_config = vfio_pci_load_config,
2643 };
2644
vfio_populate_vga(VFIOPCIDevice * vdev,Error ** errp)2645 int vfio_populate_vga(VFIOPCIDevice *vdev, Error **errp)
2646 {
2647 VFIODevice *vbasedev = &vdev->vbasedev;
2648 struct vfio_region_info *reg_info;
2649 int ret;
2650
2651 ret = vfio_get_region_info(vbasedev, VFIO_PCI_VGA_REGION_INDEX, ®_info);
2652 if (ret) {
2653 error_setg_errno(errp, -ret,
2654 "failed getting region info for VGA region index %d",
2655 VFIO_PCI_VGA_REGION_INDEX);
2656 return ret;
2657 }
2658
2659 if (!(reg_info->flags & VFIO_REGION_INFO_FLAG_READ) ||
2660 !(reg_info->flags & VFIO_REGION_INFO_FLAG_WRITE) ||
2661 reg_info->size < 0xbffff + 1) {
2662 error_setg(errp, "unexpected VGA info, flags 0x%lx, size 0x%lx",
2663 (unsigned long)reg_info->flags,
2664 (unsigned long)reg_info->size);
2665 g_free(reg_info);
2666 return -EINVAL;
2667 }
2668
2669 vdev->vga = g_new0(VFIOVGA, 1);
2670
2671 vdev->vga->fd_offset = reg_info->offset;
2672 vdev->vga->fd = vdev->vbasedev.fd;
2673
2674 g_free(reg_info);
2675
2676 vdev->vga->region[QEMU_PCI_VGA_MEM].offset = QEMU_PCI_VGA_MEM_BASE;
2677 vdev->vga->region[QEMU_PCI_VGA_MEM].nr = QEMU_PCI_VGA_MEM;
2678 QLIST_INIT(&vdev->vga->region[QEMU_PCI_VGA_MEM].quirks);
2679
2680 memory_region_init_io(&vdev->vga->region[QEMU_PCI_VGA_MEM].mem,
2681 OBJECT(vdev), &vfio_vga_ops,
2682 &vdev->vga->region[QEMU_PCI_VGA_MEM],
2683 "vfio-vga-mmio@0xa0000",
2684 QEMU_PCI_VGA_MEM_SIZE);
2685
2686 vdev->vga->region[QEMU_PCI_VGA_IO_LO].offset = QEMU_PCI_VGA_IO_LO_BASE;
2687 vdev->vga->region[QEMU_PCI_VGA_IO_LO].nr = QEMU_PCI_VGA_IO_LO;
2688 QLIST_INIT(&vdev->vga->region[QEMU_PCI_VGA_IO_LO].quirks);
2689
2690 memory_region_init_io(&vdev->vga->region[QEMU_PCI_VGA_IO_LO].mem,
2691 OBJECT(vdev), &vfio_vga_ops,
2692 &vdev->vga->region[QEMU_PCI_VGA_IO_LO],
2693 "vfio-vga-io@0x3b0",
2694 QEMU_PCI_VGA_IO_LO_SIZE);
2695
2696 vdev->vga->region[QEMU_PCI_VGA_IO_HI].offset = QEMU_PCI_VGA_IO_HI_BASE;
2697 vdev->vga->region[QEMU_PCI_VGA_IO_HI].nr = QEMU_PCI_VGA_IO_HI;
2698 QLIST_INIT(&vdev->vga->region[QEMU_PCI_VGA_IO_HI].quirks);
2699
2700 memory_region_init_io(&vdev->vga->region[QEMU_PCI_VGA_IO_HI].mem,
2701 OBJECT(vdev), &vfio_vga_ops,
2702 &vdev->vga->region[QEMU_PCI_VGA_IO_HI],
2703 "vfio-vga-io@0x3c0",
2704 QEMU_PCI_VGA_IO_HI_SIZE);
2705
2706 pci_register_vga(&vdev->pdev, &vdev->vga->region[QEMU_PCI_VGA_MEM].mem,
2707 &vdev->vga->region[QEMU_PCI_VGA_IO_LO].mem,
2708 &vdev->vga->region[QEMU_PCI_VGA_IO_HI].mem);
2709
2710 return 0;
2711 }
2712
vfio_populate_device(VFIOPCIDevice * vdev,Error ** errp)2713 static void vfio_populate_device(VFIOPCIDevice *vdev, Error **errp)
2714 {
2715 VFIODevice *vbasedev = &vdev->vbasedev;
2716 struct vfio_region_info *reg_info;
2717 struct vfio_irq_info irq_info = { .argsz = sizeof(irq_info) };
2718 int i, ret = -1;
2719
2720 /* Sanity check device */
2721 if (!(vbasedev->flags & VFIO_DEVICE_FLAGS_PCI)) {
2722 error_setg(errp, "this isn't a PCI device");
2723 return;
2724 }
2725
2726 if (vbasedev->num_regions < VFIO_PCI_CONFIG_REGION_INDEX + 1) {
2727 error_setg(errp, "unexpected number of io regions %u",
2728 vbasedev->num_regions);
2729 return;
2730 }
2731
2732 if (vbasedev->num_irqs < VFIO_PCI_MSIX_IRQ_INDEX + 1) {
2733 error_setg(errp, "unexpected number of irqs %u", vbasedev->num_irqs);
2734 return;
2735 }
2736
2737 for (i = VFIO_PCI_BAR0_REGION_INDEX; i < VFIO_PCI_ROM_REGION_INDEX; i++) {
2738 char *name = g_strdup_printf("%s BAR %d", vbasedev->name, i);
2739
2740 ret = vfio_region_setup(OBJECT(vdev), vbasedev,
2741 &vdev->bars[i].region, i, name);
2742 g_free(name);
2743
2744 if (ret) {
2745 error_setg_errno(errp, -ret, "failed to get region %d info", i);
2746 return;
2747 }
2748
2749 QLIST_INIT(&vdev->bars[i].quirks);
2750 }
2751
2752 ret = vfio_get_region_info(vbasedev,
2753 VFIO_PCI_CONFIG_REGION_INDEX, ®_info);
2754 if (ret) {
2755 error_setg_errno(errp, -ret, "failed to get config info");
2756 return;
2757 }
2758
2759 trace_vfio_populate_device_config(vdev->vbasedev.name,
2760 (unsigned long)reg_info->size,
2761 (unsigned long)reg_info->offset,
2762 (unsigned long)reg_info->flags);
2763
2764 vdev->config_size = reg_info->size;
2765 if (vdev->config_size == PCI_CONFIG_SPACE_SIZE) {
2766 vdev->pdev.cap_present &= ~QEMU_PCI_CAP_EXPRESS;
2767 }
2768 vdev->config_offset = reg_info->offset;
2769
2770 g_free(reg_info);
2771
2772 if (vdev->features & VFIO_FEATURE_ENABLE_VGA) {
2773 ret = vfio_populate_vga(vdev, errp);
2774 if (ret) {
2775 error_append_hint(errp, "device does not support "
2776 "requested feature x-vga\n");
2777 return;
2778 }
2779 }
2780
2781 irq_info.index = VFIO_PCI_ERR_IRQ_INDEX;
2782
2783 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_IRQ_INFO, &irq_info);
2784 if (ret) {
2785 /* This can fail for an old kernel or legacy PCI dev */
2786 trace_vfio_populate_device_get_irq_info_failure(strerror(errno));
2787 } else if (irq_info.count == 1) {
2788 vdev->pci_aer = true;
2789 } else {
2790 warn_report(VFIO_MSG_PREFIX
2791 "Could not enable error recovery for the device",
2792 vbasedev->name);
2793 }
2794 }
2795
vfio_pci_put_device(VFIOPCIDevice * vdev)2796 static void vfio_pci_put_device(VFIOPCIDevice *vdev)
2797 {
2798 vfio_detach_device(&vdev->vbasedev);
2799
2800 g_free(vdev->vbasedev.name);
2801 g_free(vdev->msix);
2802 }
2803
vfio_err_notifier_handler(void * opaque)2804 static void vfio_err_notifier_handler(void *opaque)
2805 {
2806 VFIOPCIDevice *vdev = opaque;
2807
2808 if (!event_notifier_test_and_clear(&vdev->err_notifier)) {
2809 return;
2810 }
2811
2812 /*
2813 * TBD. Retrieve the error details and decide what action
2814 * needs to be taken. One of the actions could be to pass
2815 * the error to the guest and have the guest driver recover
2816 * from the error. This requires that PCIe capabilities be
2817 * exposed to the guest. For now, we just terminate the
2818 * guest to contain the error.
2819 */
2820
2821 error_report("%s(%s) Unrecoverable error detected. Please collect any data possible and then kill the guest", __func__, vdev->vbasedev.name);
2822
2823 vm_stop(RUN_STATE_INTERNAL_ERROR);
2824 }
2825
2826 /*
2827 * Registers error notifier for devices supporting error recovery.
2828 * If we encounter a failure in this function, we report an error
2829 * and continue after disabling error recovery support for the
2830 * device.
2831 */
vfio_register_err_notifier(VFIOPCIDevice * vdev)2832 static void vfio_register_err_notifier(VFIOPCIDevice *vdev)
2833 {
2834 Error *err = NULL;
2835 int32_t fd;
2836
2837 if (!vdev->pci_aer) {
2838 return;
2839 }
2840
2841 if (event_notifier_init(&vdev->err_notifier, 0)) {
2842 error_report("vfio: Unable to init event notifier for error detection");
2843 vdev->pci_aer = false;
2844 return;
2845 }
2846
2847 fd = event_notifier_get_fd(&vdev->err_notifier);
2848 qemu_set_fd_handler(fd, vfio_err_notifier_handler, NULL, vdev);
2849
2850 if (vfio_set_irq_signaling(&vdev->vbasedev, VFIO_PCI_ERR_IRQ_INDEX, 0,
2851 VFIO_IRQ_SET_ACTION_TRIGGER, fd, &err)) {
2852 error_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name);
2853 qemu_set_fd_handler(fd, NULL, NULL, vdev);
2854 event_notifier_cleanup(&vdev->err_notifier);
2855 vdev->pci_aer = false;
2856 }
2857 }
2858
vfio_unregister_err_notifier(VFIOPCIDevice * vdev)2859 static void vfio_unregister_err_notifier(VFIOPCIDevice *vdev)
2860 {
2861 Error *err = NULL;
2862
2863 if (!vdev->pci_aer) {
2864 return;
2865 }
2866
2867 if (vfio_set_irq_signaling(&vdev->vbasedev, VFIO_PCI_ERR_IRQ_INDEX, 0,
2868 VFIO_IRQ_SET_ACTION_TRIGGER, -1, &err)) {
2869 error_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name);
2870 }
2871 qemu_set_fd_handler(event_notifier_get_fd(&vdev->err_notifier),
2872 NULL, NULL, vdev);
2873 event_notifier_cleanup(&vdev->err_notifier);
2874 }
2875
vfio_req_notifier_handler(void * opaque)2876 static void vfio_req_notifier_handler(void *opaque)
2877 {
2878 VFIOPCIDevice *vdev = opaque;
2879 Error *err = NULL;
2880
2881 if (!event_notifier_test_and_clear(&vdev->req_notifier)) {
2882 return;
2883 }
2884
2885 qdev_unplug(DEVICE(vdev), &err);
2886 if (err) {
2887 warn_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name);
2888 }
2889 }
2890
vfio_register_req_notifier(VFIOPCIDevice * vdev)2891 static void vfio_register_req_notifier(VFIOPCIDevice *vdev)
2892 {
2893 struct vfio_irq_info irq_info = { .argsz = sizeof(irq_info),
2894 .index = VFIO_PCI_REQ_IRQ_INDEX };
2895 Error *err = NULL;
2896 int32_t fd;
2897
2898 if (!(vdev->features & VFIO_FEATURE_ENABLE_REQ)) {
2899 return;
2900 }
2901
2902 if (ioctl(vdev->vbasedev.fd,
2903 VFIO_DEVICE_GET_IRQ_INFO, &irq_info) < 0 || irq_info.count < 1) {
2904 return;
2905 }
2906
2907 if (event_notifier_init(&vdev->req_notifier, 0)) {
2908 error_report("vfio: Unable to init event notifier for device request");
2909 return;
2910 }
2911
2912 fd = event_notifier_get_fd(&vdev->req_notifier);
2913 qemu_set_fd_handler(fd, vfio_req_notifier_handler, NULL, vdev);
2914
2915 if (vfio_set_irq_signaling(&vdev->vbasedev, VFIO_PCI_REQ_IRQ_INDEX, 0,
2916 VFIO_IRQ_SET_ACTION_TRIGGER, fd, &err)) {
2917 error_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name);
2918 qemu_set_fd_handler(fd, NULL, NULL, vdev);
2919 event_notifier_cleanup(&vdev->req_notifier);
2920 } else {
2921 vdev->req_enabled = true;
2922 }
2923 }
2924
vfio_unregister_req_notifier(VFIOPCIDevice * vdev)2925 static void vfio_unregister_req_notifier(VFIOPCIDevice *vdev)
2926 {
2927 Error *err = NULL;
2928
2929 if (!vdev->req_enabled) {
2930 return;
2931 }
2932
2933 if (vfio_set_irq_signaling(&vdev->vbasedev, VFIO_PCI_REQ_IRQ_INDEX, 0,
2934 VFIO_IRQ_SET_ACTION_TRIGGER, -1, &err)) {
2935 error_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name);
2936 }
2937 qemu_set_fd_handler(event_notifier_get_fd(&vdev->req_notifier),
2938 NULL, NULL, vdev);
2939 event_notifier_cleanup(&vdev->req_notifier);
2940
2941 vdev->req_enabled = false;
2942 }
2943
vfio_realize(PCIDevice * pdev,Error ** errp)2944 static void vfio_realize(PCIDevice *pdev, Error **errp)
2945 {
2946 ERRP_GUARD();
2947 VFIOPCIDevice *vdev = VFIO_PCI(pdev);
2948 VFIODevice *vbasedev = &vdev->vbasedev;
2949 char *tmp, *subsys;
2950 Error *err = NULL;
2951 int i, ret;
2952 bool is_mdev;
2953 char uuid[UUID_STR_LEN];
2954 char *name;
2955
2956 if (vbasedev->fd < 0 && !vbasedev->sysfsdev) {
2957 if (!(~vdev->host.domain || ~vdev->host.bus ||
2958 ~vdev->host.slot || ~vdev->host.function)) {
2959 error_setg(errp, "No provided host device");
2960 error_append_hint(errp, "Use -device vfio-pci,host=DDDD:BB:DD.F "
2961 #ifdef CONFIG_IOMMUFD
2962 "or -device vfio-pci,fd=DEVICE_FD "
2963 #endif
2964 "or -device vfio-pci,sysfsdev=PATH_TO_DEVICE\n");
2965 return;
2966 }
2967 vbasedev->sysfsdev =
2968 g_strdup_printf("/sys/bus/pci/devices/%04x:%02x:%02x.%01x",
2969 vdev->host.domain, vdev->host.bus,
2970 vdev->host.slot, vdev->host.function);
2971 }
2972
2973 if (vfio_device_get_name(vbasedev, errp) < 0) {
2974 return;
2975 }
2976
2977 /*
2978 * Mediated devices *might* operate compatibly with discarding of RAM, but
2979 * we cannot know for certain, it depends on whether the mdev vendor driver
2980 * stays in sync with the active working set of the guest driver. Prevent
2981 * the x-balloon-allowed option unless this is minimally an mdev device.
2982 */
2983 tmp = g_strdup_printf("%s/subsystem", vbasedev->sysfsdev);
2984 subsys = realpath(tmp, NULL);
2985 g_free(tmp);
2986 is_mdev = subsys && (strcmp(subsys, "/sys/bus/mdev") == 0);
2987 free(subsys);
2988
2989 trace_vfio_mdev(vbasedev->name, is_mdev);
2990
2991 if (vbasedev->ram_block_discard_allowed && !is_mdev) {
2992 error_setg(errp, "x-balloon-allowed only potentially compatible "
2993 "with mdev devices");
2994 goto error;
2995 }
2996
2997 if (!qemu_uuid_is_null(&vdev->vf_token)) {
2998 qemu_uuid_unparse(&vdev->vf_token, uuid);
2999 name = g_strdup_printf("%s vf_token=%s", vbasedev->name, uuid);
3000 } else {
3001 name = g_strdup(vbasedev->name);
3002 }
3003
3004 ret = vfio_attach_device(name, vbasedev,
3005 pci_device_iommu_address_space(pdev), errp);
3006 g_free(name);
3007 if (ret) {
3008 goto error;
3009 }
3010
3011 vfio_populate_device(vdev, &err);
3012 if (err) {
3013 error_propagate(errp, err);
3014 goto error;
3015 }
3016
3017 /* Get a copy of config space */
3018 ret = pread(vbasedev->fd, vdev->pdev.config,
3019 MIN(pci_config_size(&vdev->pdev), vdev->config_size),
3020 vdev->config_offset);
3021 if (ret < (int)MIN(pci_config_size(&vdev->pdev), vdev->config_size)) {
3022 ret = ret < 0 ? -errno : -EFAULT;
3023 error_setg_errno(errp, -ret, "failed to read device config space");
3024 goto error;
3025 }
3026
3027 /* vfio emulates a lot for us, but some bits need extra love */
3028 vdev->emulated_config_bits = g_malloc0(vdev->config_size);
3029
3030 /* QEMU can choose to expose the ROM or not */
3031 memset(vdev->emulated_config_bits + PCI_ROM_ADDRESS, 0xff, 4);
3032 /* QEMU can also add or extend BARs */
3033 memset(vdev->emulated_config_bits + PCI_BASE_ADDRESS_0, 0xff, 6 * 4);
3034
3035 /*
3036 * The PCI spec reserves vendor ID 0xffff as an invalid value. The
3037 * device ID is managed by the vendor and need only be a 16-bit value.
3038 * Allow any 16-bit value for subsystem so they can be hidden or changed.
3039 */
3040 if (vdev->vendor_id != PCI_ANY_ID) {
3041 if (vdev->vendor_id >= 0xffff) {
3042 error_setg(errp, "invalid PCI vendor ID provided");
3043 goto error;
3044 }
3045 vfio_add_emulated_word(vdev, PCI_VENDOR_ID, vdev->vendor_id, ~0);
3046 trace_vfio_pci_emulated_vendor_id(vbasedev->name, vdev->vendor_id);
3047 } else {
3048 vdev->vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
3049 }
3050
3051 if (vdev->device_id != PCI_ANY_ID) {
3052 if (vdev->device_id > 0xffff) {
3053 error_setg(errp, "invalid PCI device ID provided");
3054 goto error;
3055 }
3056 vfio_add_emulated_word(vdev, PCI_DEVICE_ID, vdev->device_id, ~0);
3057 trace_vfio_pci_emulated_device_id(vbasedev->name, vdev->device_id);
3058 } else {
3059 vdev->device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
3060 }
3061
3062 if (vdev->sub_vendor_id != PCI_ANY_ID) {
3063 if (vdev->sub_vendor_id > 0xffff) {
3064 error_setg(errp, "invalid PCI subsystem vendor ID provided");
3065 goto error;
3066 }
3067 vfio_add_emulated_word(vdev, PCI_SUBSYSTEM_VENDOR_ID,
3068 vdev->sub_vendor_id, ~0);
3069 trace_vfio_pci_emulated_sub_vendor_id(vbasedev->name,
3070 vdev->sub_vendor_id);
3071 }
3072
3073 if (vdev->sub_device_id != PCI_ANY_ID) {
3074 if (vdev->sub_device_id > 0xffff) {
3075 error_setg(errp, "invalid PCI subsystem device ID provided");
3076 goto error;
3077 }
3078 vfio_add_emulated_word(vdev, PCI_SUBSYSTEM_ID, vdev->sub_device_id, ~0);
3079 trace_vfio_pci_emulated_sub_device_id(vbasedev->name,
3080 vdev->sub_device_id);
3081 }
3082
3083 /* QEMU can change multi-function devices to single function, or reverse */
3084 vdev->emulated_config_bits[PCI_HEADER_TYPE] =
3085 PCI_HEADER_TYPE_MULTI_FUNCTION;
3086
3087 /* Restore or clear multifunction, this is always controlled by QEMU */
3088 if (vdev->pdev.cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
3089 vdev->pdev.config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
3090 } else {
3091 vdev->pdev.config[PCI_HEADER_TYPE] &= ~PCI_HEADER_TYPE_MULTI_FUNCTION;
3092 }
3093
3094 /*
3095 * Clear host resource mapping info. If we choose not to register a
3096 * BAR, such as might be the case with the option ROM, we can get
3097 * confusing, unwritable, residual addresses from the host here.
3098 */
3099 memset(&vdev->pdev.config[PCI_BASE_ADDRESS_0], 0, 24);
3100 memset(&vdev->pdev.config[PCI_ROM_ADDRESS], 0, 4);
3101
3102 vfio_pci_size_rom(vdev);
3103
3104 vfio_bars_prepare(vdev);
3105
3106 vfio_msix_early_setup(vdev, &err);
3107 if (err) {
3108 error_propagate(errp, err);
3109 goto error;
3110 }
3111
3112 vfio_bars_register(vdev);
3113
3114 ret = vfio_add_capabilities(vdev, errp);
3115 if (ret) {
3116 goto out_teardown;
3117 }
3118
3119 if (vdev->vga) {
3120 vfio_vga_quirk_setup(vdev);
3121 }
3122
3123 for (i = 0; i < PCI_ROM_SLOT; i++) {
3124 vfio_bar_quirk_setup(vdev, i);
3125 }
3126
3127 if (!vdev->igd_opregion &&
3128 vdev->features & VFIO_FEATURE_ENABLE_IGD_OPREGION) {
3129 struct vfio_region_info *opregion;
3130
3131 if (vdev->pdev.qdev.hotplugged) {
3132 error_setg(errp,
3133 "cannot support IGD OpRegion feature on hotplugged "
3134 "device");
3135 goto out_teardown;
3136 }
3137
3138 ret = vfio_get_dev_region_info(vbasedev,
3139 VFIO_REGION_TYPE_PCI_VENDOR_TYPE | PCI_VENDOR_ID_INTEL,
3140 VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION, &opregion);
3141 if (ret) {
3142 error_setg_errno(errp, -ret,
3143 "does not support requested IGD OpRegion feature");
3144 goto out_teardown;
3145 }
3146
3147 ret = vfio_pci_igd_opregion_init(vdev, opregion, errp);
3148 g_free(opregion);
3149 if (ret) {
3150 goto out_teardown;
3151 }
3152 }
3153
3154 /* QEMU emulates all of MSI & MSIX */
3155 if (pdev->cap_present & QEMU_PCI_CAP_MSIX) {
3156 memset(vdev->emulated_config_bits + pdev->msix_cap, 0xff,
3157 MSIX_CAP_LENGTH);
3158 }
3159
3160 if (pdev->cap_present & QEMU_PCI_CAP_MSI) {
3161 memset(vdev->emulated_config_bits + pdev->msi_cap, 0xff,
3162 vdev->msi_cap_size);
3163 }
3164
3165 if (vfio_pci_read_config(&vdev->pdev, PCI_INTERRUPT_PIN, 1)) {
3166 vdev->intx.mmap_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL,
3167 vfio_intx_mmap_enable, vdev);
3168 pci_device_set_intx_routing_notifier(&vdev->pdev,
3169 vfio_intx_routing_notifier);
3170 vdev->irqchip_change_notifier.notify = vfio_irqchip_change;
3171 kvm_irqchip_add_change_notifier(&vdev->irqchip_change_notifier);
3172 ret = vfio_intx_enable(vdev, errp);
3173 if (ret) {
3174 goto out_deregister;
3175 }
3176 }
3177
3178 if (vdev->display != ON_OFF_AUTO_OFF) {
3179 ret = vfio_display_probe(vdev, errp);
3180 if (ret) {
3181 goto out_deregister;
3182 }
3183 }
3184 if (vdev->enable_ramfb && vdev->dpy == NULL) {
3185 error_setg(errp, "ramfb=on requires display=on");
3186 goto out_deregister;
3187 }
3188 if (vdev->display_xres || vdev->display_yres) {
3189 if (vdev->dpy == NULL) {
3190 error_setg(errp, "xres and yres properties require display=on");
3191 goto out_deregister;
3192 }
3193 if (vdev->dpy->edid_regs == NULL) {
3194 error_setg(errp, "xres and yres properties need edid support");
3195 goto out_deregister;
3196 }
3197 }
3198
3199 if (vdev->ramfb_migrate == ON_OFF_AUTO_ON && !vdev->enable_ramfb) {
3200 warn_report("x-ramfb-migrate=on but ramfb=off. "
3201 "Forcing x-ramfb-migrate to off.");
3202 vdev->ramfb_migrate = ON_OFF_AUTO_OFF;
3203 }
3204 if (vbasedev->enable_migration == ON_OFF_AUTO_OFF) {
3205 if (vdev->ramfb_migrate == ON_OFF_AUTO_AUTO) {
3206 vdev->ramfb_migrate = ON_OFF_AUTO_OFF;
3207 } else if (vdev->ramfb_migrate == ON_OFF_AUTO_ON) {
3208 error_setg(errp, "x-ramfb-migrate requires enable-migration");
3209 goto out_deregister;
3210 }
3211 }
3212
3213 if (!pdev->failover_pair_id) {
3214 if (!vfio_migration_realize(vbasedev, errp)) {
3215 goto out_deregister;
3216 }
3217 }
3218
3219 vfio_register_err_notifier(vdev);
3220 vfio_register_req_notifier(vdev);
3221 vfio_setup_resetfn_quirk(vdev);
3222
3223 return;
3224
3225 out_deregister:
3226 if (vdev->interrupt == VFIO_INT_INTx) {
3227 vfio_intx_disable(vdev);
3228 }
3229 pci_device_set_intx_routing_notifier(&vdev->pdev, NULL);
3230 if (vdev->irqchip_change_notifier.notify) {
3231 kvm_irqchip_remove_change_notifier(&vdev->irqchip_change_notifier);
3232 }
3233 if (vdev->intx.mmap_timer) {
3234 timer_free(vdev->intx.mmap_timer);
3235 }
3236 out_teardown:
3237 vfio_teardown_msi(vdev);
3238 vfio_bars_exit(vdev);
3239 error:
3240 error_prepend(errp, VFIO_MSG_PREFIX, vbasedev->name);
3241 }
3242
vfio_instance_finalize(Object * obj)3243 static void vfio_instance_finalize(Object *obj)
3244 {
3245 VFIOPCIDevice *vdev = VFIO_PCI(obj);
3246
3247 vfio_display_finalize(vdev);
3248 vfio_bars_finalize(vdev);
3249 g_free(vdev->emulated_config_bits);
3250 g_free(vdev->rom);
3251 /*
3252 * XXX Leaking igd_opregion is not an oversight, we can't remove the
3253 * fw_cfg entry therefore leaking this allocation seems like the safest
3254 * option.
3255 *
3256 * g_free(vdev->igd_opregion);
3257 */
3258 vfio_pci_put_device(vdev);
3259 }
3260
vfio_exitfn(PCIDevice * pdev)3261 static void vfio_exitfn(PCIDevice *pdev)
3262 {
3263 VFIOPCIDevice *vdev = VFIO_PCI(pdev);
3264
3265 vfio_unregister_req_notifier(vdev);
3266 vfio_unregister_err_notifier(vdev);
3267 pci_device_set_intx_routing_notifier(&vdev->pdev, NULL);
3268 if (vdev->irqchip_change_notifier.notify) {
3269 kvm_irqchip_remove_change_notifier(&vdev->irqchip_change_notifier);
3270 }
3271 vfio_disable_interrupts(vdev);
3272 if (vdev->intx.mmap_timer) {
3273 timer_free(vdev->intx.mmap_timer);
3274 }
3275 vfio_teardown_msi(vdev);
3276 vfio_pci_disable_rp_atomics(vdev);
3277 vfio_bars_exit(vdev);
3278 vfio_migration_exit(&vdev->vbasedev);
3279 }
3280
vfio_pci_reset(DeviceState * dev)3281 static void vfio_pci_reset(DeviceState *dev)
3282 {
3283 VFIOPCIDevice *vdev = VFIO_PCI(dev);
3284
3285 trace_vfio_pci_reset(vdev->vbasedev.name);
3286
3287 vfio_pci_pre_reset(vdev);
3288
3289 if (vdev->display != ON_OFF_AUTO_OFF) {
3290 vfio_display_reset(vdev);
3291 }
3292
3293 if (vdev->resetfn && !vdev->resetfn(vdev)) {
3294 goto post_reset;
3295 }
3296
3297 if (vdev->vbasedev.reset_works &&
3298 (vdev->has_flr || !vdev->has_pm_reset) &&
3299 !ioctl(vdev->vbasedev.fd, VFIO_DEVICE_RESET)) {
3300 trace_vfio_pci_reset_flr(vdev->vbasedev.name);
3301 goto post_reset;
3302 }
3303
3304 /* See if we can do our own bus reset */
3305 if (!vfio_pci_hot_reset_one(vdev)) {
3306 goto post_reset;
3307 }
3308
3309 /* If nothing else works and the device supports PM reset, use it */
3310 if (vdev->vbasedev.reset_works && vdev->has_pm_reset &&
3311 !ioctl(vdev->vbasedev.fd, VFIO_DEVICE_RESET)) {
3312 trace_vfio_pci_reset_pm(vdev->vbasedev.name);
3313 goto post_reset;
3314 }
3315
3316 post_reset:
3317 vfio_pci_post_reset(vdev);
3318 }
3319
vfio_instance_init(Object * obj)3320 static void vfio_instance_init(Object *obj)
3321 {
3322 PCIDevice *pci_dev = PCI_DEVICE(obj);
3323 VFIOPCIDevice *vdev = VFIO_PCI(obj);
3324 VFIODevice *vbasedev = &vdev->vbasedev;
3325
3326 device_add_bootindex_property(obj, &vdev->bootindex,
3327 "bootindex", NULL,
3328 &pci_dev->qdev);
3329 vdev->host.domain = ~0U;
3330 vdev->host.bus = ~0U;
3331 vdev->host.slot = ~0U;
3332 vdev->host.function = ~0U;
3333
3334 vfio_device_init(vbasedev, VFIO_DEVICE_TYPE_PCI, &vfio_pci_ops,
3335 DEVICE(vdev), false);
3336
3337 vdev->nv_gpudirect_clique = 0xFF;
3338
3339 /* QEMU_PCI_CAP_EXPRESS initialization does not depend on QEMU command
3340 * line, therefore, no need to wait to realize like other devices */
3341 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
3342 }
3343
3344 static Property vfio_pci_dev_properties[] = {
3345 DEFINE_PROP_PCI_HOST_DEVADDR("host", VFIOPCIDevice, host),
3346 DEFINE_PROP_UUID_NODEFAULT("vf-token", VFIOPCIDevice, vf_token),
3347 DEFINE_PROP_STRING("sysfsdev", VFIOPCIDevice, vbasedev.sysfsdev),
3348 DEFINE_PROP_ON_OFF_AUTO("x-pre-copy-dirty-page-tracking", VFIOPCIDevice,
3349 vbasedev.pre_copy_dirty_page_tracking,
3350 ON_OFF_AUTO_ON),
3351 DEFINE_PROP_ON_OFF_AUTO("display", VFIOPCIDevice,
3352 display, ON_OFF_AUTO_OFF),
3353 DEFINE_PROP_UINT32("xres", VFIOPCIDevice, display_xres, 0),
3354 DEFINE_PROP_UINT32("yres", VFIOPCIDevice, display_yres, 0),
3355 DEFINE_PROP_UINT32("x-intx-mmap-timeout-ms", VFIOPCIDevice,
3356 intx.mmap_timeout, 1100),
3357 DEFINE_PROP_BIT("x-vga", VFIOPCIDevice, features,
3358 VFIO_FEATURE_ENABLE_VGA_BIT, false),
3359 DEFINE_PROP_BIT("x-req", VFIOPCIDevice, features,
3360 VFIO_FEATURE_ENABLE_REQ_BIT, true),
3361 DEFINE_PROP_BIT("x-igd-opregion", VFIOPCIDevice, features,
3362 VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT, false),
3363 DEFINE_PROP_ON_OFF_AUTO("enable-migration", VFIOPCIDevice,
3364 vbasedev.enable_migration, ON_OFF_AUTO_AUTO),
3365 DEFINE_PROP_BOOL("x-no-mmap", VFIOPCIDevice, vbasedev.no_mmap, false),
3366 DEFINE_PROP_BOOL("x-balloon-allowed", VFIOPCIDevice,
3367 vbasedev.ram_block_discard_allowed, false),
3368 DEFINE_PROP_BOOL("x-no-kvm-intx", VFIOPCIDevice, no_kvm_intx, false),
3369 DEFINE_PROP_BOOL("x-no-kvm-msi", VFIOPCIDevice, no_kvm_msi, false),
3370 DEFINE_PROP_BOOL("x-no-kvm-msix", VFIOPCIDevice, no_kvm_msix, false),
3371 DEFINE_PROP_BOOL("x-no-geforce-quirks", VFIOPCIDevice,
3372 no_geforce_quirks, false),
3373 DEFINE_PROP_BOOL("x-no-kvm-ioeventfd", VFIOPCIDevice, no_kvm_ioeventfd,
3374 false),
3375 DEFINE_PROP_BOOL("x-no-vfio-ioeventfd", VFIOPCIDevice, no_vfio_ioeventfd,
3376 false),
3377 DEFINE_PROP_UINT32("x-pci-vendor-id", VFIOPCIDevice, vendor_id, PCI_ANY_ID),
3378 DEFINE_PROP_UINT32("x-pci-device-id", VFIOPCIDevice, device_id, PCI_ANY_ID),
3379 DEFINE_PROP_UINT32("x-pci-sub-vendor-id", VFIOPCIDevice,
3380 sub_vendor_id, PCI_ANY_ID),
3381 DEFINE_PROP_UINT32("x-pci-sub-device-id", VFIOPCIDevice,
3382 sub_device_id, PCI_ANY_ID),
3383 DEFINE_PROP_UINT32("x-igd-gms", VFIOPCIDevice, igd_gms, 0),
3384 DEFINE_PROP_UNSIGNED_NODEFAULT("x-nv-gpudirect-clique", VFIOPCIDevice,
3385 nv_gpudirect_clique,
3386 qdev_prop_nv_gpudirect_clique, uint8_t),
3387 DEFINE_PROP_OFF_AUTO_PCIBAR("x-msix-relocation", VFIOPCIDevice, msix_relo,
3388 OFF_AUTOPCIBAR_OFF),
3389 #ifdef CONFIG_IOMMUFD
3390 DEFINE_PROP_LINK("iommufd", VFIOPCIDevice, vbasedev.iommufd,
3391 TYPE_IOMMUFD_BACKEND, IOMMUFDBackend *),
3392 #endif
3393 DEFINE_PROP_END_OF_LIST(),
3394 };
3395
3396 #ifdef CONFIG_IOMMUFD
vfio_pci_set_fd(Object * obj,const char * str,Error ** errp)3397 static void vfio_pci_set_fd(Object *obj, const char *str, Error **errp)
3398 {
3399 vfio_device_set_fd(&VFIO_PCI(obj)->vbasedev, str, errp);
3400 }
3401 #endif
3402
vfio_pci_dev_class_init(ObjectClass * klass,void * data)3403 static void vfio_pci_dev_class_init(ObjectClass *klass, void *data)
3404 {
3405 DeviceClass *dc = DEVICE_CLASS(klass);
3406 PCIDeviceClass *pdc = PCI_DEVICE_CLASS(klass);
3407
3408 dc->reset = vfio_pci_reset;
3409 device_class_set_props(dc, vfio_pci_dev_properties);
3410 #ifdef CONFIG_IOMMUFD
3411 object_class_property_add_str(klass, "fd", NULL, vfio_pci_set_fd);
3412 #endif
3413 dc->desc = "VFIO-based PCI device assignment";
3414 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
3415 pdc->realize = vfio_realize;
3416 pdc->exit = vfio_exitfn;
3417 pdc->config_read = vfio_pci_read_config;
3418 pdc->config_write = vfio_pci_write_config;
3419 }
3420
3421 static const TypeInfo vfio_pci_dev_info = {
3422 .name = TYPE_VFIO_PCI,
3423 .parent = TYPE_PCI_DEVICE,
3424 .instance_size = sizeof(VFIOPCIDevice),
3425 .class_init = vfio_pci_dev_class_init,
3426 .instance_init = vfio_instance_init,
3427 .instance_finalize = vfio_instance_finalize,
3428 .interfaces = (InterfaceInfo[]) {
3429 { INTERFACE_PCIE_DEVICE },
3430 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
3431 { }
3432 },
3433 };
3434
3435 static Property vfio_pci_dev_nohotplug_properties[] = {
3436 DEFINE_PROP_BOOL("ramfb", VFIOPCIDevice, enable_ramfb, false),
3437 DEFINE_PROP_ON_OFF_AUTO("x-ramfb-migrate", VFIOPCIDevice, ramfb_migrate,
3438 ON_OFF_AUTO_AUTO),
3439 DEFINE_PROP_END_OF_LIST(),
3440 };
3441
vfio_pci_nohotplug_dev_class_init(ObjectClass * klass,void * data)3442 static void vfio_pci_nohotplug_dev_class_init(ObjectClass *klass, void *data)
3443 {
3444 DeviceClass *dc = DEVICE_CLASS(klass);
3445
3446 device_class_set_props(dc, vfio_pci_dev_nohotplug_properties);
3447 dc->hotpluggable = false;
3448 }
3449
3450 static const TypeInfo vfio_pci_nohotplug_dev_info = {
3451 .name = TYPE_VFIO_PCI_NOHOTPLUG,
3452 .parent = TYPE_VFIO_PCI,
3453 .instance_size = sizeof(VFIOPCIDevice),
3454 .class_init = vfio_pci_nohotplug_dev_class_init,
3455 };
3456
register_vfio_pci_dev_type(void)3457 static void register_vfio_pci_dev_type(void)
3458 {
3459 type_register_static(&vfio_pci_dev_info);
3460 type_register_static(&vfio_pci_nohotplug_dev_info);
3461 }
3462
3463 type_init(register_vfio_pci_dev_type)
3464