1 /**************************************************************************** 2 Copyright (C) 1987-2015 by Jeffery P. Hansen 3 4 This program is free software; you can redistribute it and/or modify 5 it under the terms of the GNU General Public License as published by 6 the Free Software Foundation; either version 2 of the License, or 7 (at your option) any later version. 8 9 This program is distributed in the hope that it will be useful, 10 but WITHOUT ANY WARRANTY; without even the implied warranty of 11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 GNU General Public License for more details. 13 14 You should have received a copy of the GNU General Public License along 15 with this program; if not, write to the Free Software Foundation, Inc., 16 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 17 18 Last edit by hansen on Fri Feb 13 20:24:16 2009 19 ****************************************************************************/ 20 #ifndef __thyme_h 21 #define __thyme_h 22 #include <stdlib.h> 23 #include <stdio.h> 24 #include <sys/types.h> 25 #include <sys/time.h> 26 #include <unistd.h> 27 #include <stdarg.h> 28 #include <string.h> 29 #include "config.h" /* Tkgate global configuration parameters */ 30 #include "thyme_config.h" /* thyme-specific configuration parameters */ 31 #include "misc.h" /* libcommon miscelaneous functions/macros */ 32 #include "hash.h" /* libcommon hash table functions/macros */ 33 #include "list.h" /* libcommon list functions/macros */ 34 #include "ycmalloc.h" /* libcommon ycmalloc package */ 35 #include "io.h" /* Communication functions */ 36 #include "error.h" /* Error and Place handling */ 37 #include "multint.h" /* Multi-word integer operations */ 38 #include "value.h" /* Verilog value class */ 39 #include "operators.h" /* Operator functions */ 40 #include "systask.h" /* System tasks */ 41 #include "memory.h" /* Memory */ 42 #include "expr.h" /* Expressions */ 43 #include "statement.h" /* Statements */ 44 #include "mitem.h" /* Module Items */ 45 #include "specify.h" /* Handling for specify blocks */ 46 #include "directive.h" /* Compiler directive handling */ 47 #include "module.h" /* Modules */ 48 #include "task.h" /* User-defined tasks */ 49 #include "net.h" /* Nets */ 50 #include "circuit.h" /* Circuit */ 51 #include "evqueue.h" /* Event processing */ 52 #include "channel.h" /* Data channel handling */ 53 #include "trigger.h" /* Event triggers */ 54 #include "bytecode.h" /* Simulation byte code */ 55 #include "verilog.h" /* Parser functions */ 56 #include "yybasic.h" /* Basic parser functions */ 57 #include "vgrammar.h" /* Symbols definitions for tokens */ 58 59 typedef enum delay_type_en { 60 DT_MIN = 0, 61 #define DT_MIN DT_MIN /* Use minimum delays */ 62 DT_TYP = 1, 63 #define DT_TYP DT_TYP /* Use typical delays */ 64 DT_MAX = 2 65 #define DT_MAX DT_MAX /* Use maximum delays */ 66 } DelayType; 67 68 typedef enum verilog_std_en { 69 VSTD_UNDEFINED = 0, 70 VSTD_1995 = 1995, 71 VSTD_2001 = 2001 72 } VerilogStd; 73 74 /***************************************************************************** 75 * 76 * GVSecurity - Security settings. 77 * 78 *****************************************************************************/ 79 typedef struct { 80 int vgs_send; /* Enable $tkg$send() */ 81 int vgs_fopen; /* Enable $fopen() */ 82 int vgs_writemem; /* Enable $writememb() and $writememh() */ 83 int vgs_queue; /* Enable $tkg$read() and $tkg$write() */ 84 int vgs_exec; /* 0=disabled, 1=registered, 2=enabled */ 85 int vgs_handling; /* 0=ignore, 1=warn, 2=stop */ 86 } VGSecurity; 87 88 /***************************************************************************** 89 * 90 * GVSim - Top level structure for simulator data. 91 * 92 *****************************************************************************/ 93 typedef struct vgsim_str { 94 char *vg_baseDirectory; /* Base directory for input files */ 95 char *vg_topModuleName; /* Name of top-level module */ 96 char *vg_defaultTopModuleName; /* Default name of top-level module */ 97 SHash vg_modules; /* Table of modules */ 98 Circuit vg_circuit; /* Instantiated circuit to be simulated */ 99 int vg_interactive; /* Non-zero if we are in interactive mode */ 100 101 VGSecurity vg_sec; /* Security options */ 102 103 Timescale vg_timescale; /* Lowest timescale of any loaded module */ 104 int vg_haveTScount; /* Number of modules with timescale */ 105 106 int vg_noTimeViolations; /* Supress all timing violations? */ 107 simtime_t vg_initTime; /* Time need for user circuit to initialize. */ 108 109 DelayType vg_delayType; /* Type of delays to use */ 110 VerilogStd vg_std; 111 } VGSim; 112 113 void VGSim_init(VGSim *); 114 void VGSim_addModule(VGSim *, ModuleDecl * m); 115 ModuleDecl *VGSim_findModule(VGSim *, const char *name); 116 117 void VGSecurity_init(VGSecurity *, int trusted); 118 void VGSecurity_handleException(VGSecurity *, VGThread * t, const char *name); 119 120 int VerilogLoad(const char *name); 121 int VerilogLoadScript(const char *name, DynamicModule * dm); 122 FILE *openInPath(const char *name); 123 124 extern VGSim vgsim; /* Global state for gvsim */ 125 126 void *ob_malloc(int s,char *x); 127 void *ob_calloc(int n,int s,char *x); 128 void ob_free(void *p); 129 char *ob_strdup(char const *s); 130 void ob_set_type(void *o,char *n); 131 void ob_touch(void *o); 132 133 #endif 134