| /dports/cad/yosys/yosys-yosys-0.12/tests/memfile/ |
| H A D | memory.v | 5 input we_i, port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/generic/ |
| H A D | generic_sync_fifo.vhd | 56 we_i : in std_logic; port
89 we_i : in std_logic; port in generic_sync_fifo.syn.inferred_sync_fifo
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| H A D | generic_async_fifo.vhd | 62 we_i : in std_logic; port
108 we_i : in std_logic; port in generic_async_fifo.syn.inferred_async_fifo
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/control_lib/ |
| H A D | wb_ram_dist.v | 24 input we_i, port
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| H A D | wb_ram_block.v | 27 input we_i, port
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| H A D | v5icap_wb.v | 22 input cyc_i, input stb_i, input we_i, output ack_o, port
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| H A D | atr_controller.v | 26 input we_i, input stb_i, input cyc_i, output reg ack_o, port
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| H A D | s3a_icap_wb.v | 22 input cyc_i, input stb_i, input we_i, output ack_o, port
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| H A D | atr_controller16.v | 26 input we_i, input stb_i, input cyc_i, output reg ack_o, port
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| H A D | nsgpio.v | 40 input cyc_i, input stb_i, input [4:0] adr_i, input we_i, input [31:0] dat_i, port
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| H A D | nsgpio16LE.v | 40 input cyc_i, input stb_i, input [3:0] adr_i, input we_i, input [15:0] dat_i, port
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| H A D | pic.v | 97 input we_i, port
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| H A D | simple_uart.v | 24 input we_i, input stb_i, input cyc_i, output reg ack_o, port
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| /dports/cad/ghdl/ghdl-1.0.0/testsuite/synth/issue1190/hdl/ |
| H A D | ram.vhdl | 11 we_i : in std_logic; port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/ |
| H A D | lm32_dp_ram.vhd | 17 we_i : in std_logic; port
|
| /dports/devel/urjtag/urjtag-2021.03/extra/fjmem/ |
| H A D | generic_ram_ena.vhd | 58 we_i : in std_logic; port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/ |
| H A D | genram_pkg.vhd | 67 we_i : in std_logic; port in genram_pkg.generic_spram
162 we_i : in std_logic; port in genram_pkg.generic_async_fifo
195 we_i : in std_logic; port in genram_pkg.generic_sync_fifo
213 we_i : in std_logic; port in genram_pkg.generic_shiftreg_fifo
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/timing/ |
| H A D | timer.v | 23 input we_i, input [31:0] dat_i, output [31:0] dat_o, output ack_o, port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/opencores/simple_gpio/rtl/ |
| H A D | simple_gpio.v | 112 input we_i; // write enable port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/control/ |
| H A D | s7_icap_wb.v | 31 input we_i, port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/sim/wishbone/simple_uart/ |
| H A D | simple_uart_tb.v | 17 reg we_i; register
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/wishbone/ |
| H A D | simple_uart_tb.v | 17 reg we_i; register
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| H A D | simple_uart.v | 13 input we_i, input stb_i, input cyc_i, output reg ack_o, port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/genrams/common/ |
| H A D | generic_shiftreg_fifo.vhd | 62 we_i : in std_logic; port
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/opencores/simple_pic/rtl/ |
| H A D | simple_pic.v | 109 input we_i; // write enable port
|