1 /* $NetBSD: dm_services_types.h,v 1.2 2021/12/18 23:45:00 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012-15 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #ifndef __DM_SERVICES_TYPES_H__ 29 #define __DM_SERVICES_TYPES_H__ 30 31 #include "os_types.h" 32 #include "dc_types.h" 33 34 struct pp_smu_funcs; 35 36 struct dm_pp_clock_range { 37 int min_khz; 38 int max_khz; 39 }; 40 41 enum dm_pp_clocks_state { 42 DM_PP_CLOCKS_STATE_INVALID, 43 DM_PP_CLOCKS_STATE_ULTRA_LOW, 44 DM_PP_CLOCKS_STATE_LOW, 45 DM_PP_CLOCKS_STATE_NOMINAL, 46 DM_PP_CLOCKS_STATE_PERFORMANCE, 47 48 /* Starting from DCE11, Max 8 levels of DPM state supported. */ 49 DM_PP_CLOCKS_DPM_STATE_LEVEL_INVALID = DM_PP_CLOCKS_STATE_INVALID, 50 DM_PP_CLOCKS_DPM_STATE_LEVEL_0, 51 DM_PP_CLOCKS_DPM_STATE_LEVEL_1, 52 DM_PP_CLOCKS_DPM_STATE_LEVEL_2, 53 /* to be backward compatible */ 54 DM_PP_CLOCKS_DPM_STATE_LEVEL_3, 55 DM_PP_CLOCKS_DPM_STATE_LEVEL_4, 56 DM_PP_CLOCKS_DPM_STATE_LEVEL_5, 57 DM_PP_CLOCKS_DPM_STATE_LEVEL_6, 58 DM_PP_CLOCKS_DPM_STATE_LEVEL_7, 59 60 DM_PP_CLOCKS_MAX_STATES 61 }; 62 63 struct dm_pp_gpu_clock_range { 64 enum dm_pp_clocks_state clock_state; 65 struct dm_pp_clock_range sclk; 66 struct dm_pp_clock_range mclk; 67 struct dm_pp_clock_range eclk; 68 struct dm_pp_clock_range dclk; 69 }; 70 71 enum dm_pp_clock_type { 72 DM_PP_CLOCK_TYPE_DISPLAY_CLK = 1, 73 DM_PP_CLOCK_TYPE_ENGINE_CLK, /* System clock */ 74 DM_PP_CLOCK_TYPE_MEMORY_CLK, 75 DM_PP_CLOCK_TYPE_DCFCLK, 76 DM_PP_CLOCK_TYPE_DCEFCLK, 77 DM_PP_CLOCK_TYPE_SOCCLK, 78 DM_PP_CLOCK_TYPE_PIXELCLK, 79 DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, 80 DM_PP_CLOCK_TYPE_DPPCLK, 81 DM_PP_CLOCK_TYPE_FCLK, 82 }; 83 84 #define DC_DECODE_PP_CLOCK_TYPE(clk_type) \ 85 (clk_type) == DM_PP_CLOCK_TYPE_DISPLAY_CLK ? "Display" : \ 86 (clk_type) == DM_PP_CLOCK_TYPE_ENGINE_CLK ? "Engine" : \ 87 (clk_type) == DM_PP_CLOCK_TYPE_MEMORY_CLK ? "Memory" : \ 88 (clk_type) == DM_PP_CLOCK_TYPE_DCFCLK ? "DCF" : \ 89 (clk_type) == DM_PP_CLOCK_TYPE_DCEFCLK ? "DCEF" : \ 90 (clk_type) == DM_PP_CLOCK_TYPE_SOCCLK ? "SoC" : \ 91 (clk_type) == DM_PP_CLOCK_TYPE_PIXELCLK ? "Pixel" : \ 92 (clk_type) == DM_PP_CLOCK_TYPE_DISPLAYPHYCLK ? "Display PHY" : \ 93 (clk_type) == DM_PP_CLOCK_TYPE_DPPCLK ? "DPP" : \ 94 (clk_type) == DM_PP_CLOCK_TYPE_FCLK ? "F" : \ 95 "Invalid" 96 97 #define DM_PP_MAX_CLOCK_LEVELS 16 98 99 struct dm_pp_clock_levels { 100 uint32_t num_levels; 101 uint32_t clocks_in_khz[DM_PP_MAX_CLOCK_LEVELS]; 102 }; 103 104 struct dm_pp_clock_with_latency { 105 uint32_t clocks_in_khz; 106 uint32_t latency_in_us; 107 }; 108 109 struct dm_pp_clock_levels_with_latency { 110 uint32_t num_levels; 111 struct dm_pp_clock_with_latency data[DM_PP_MAX_CLOCK_LEVELS]; 112 }; 113 114 struct dm_pp_clock_with_voltage { 115 uint32_t clocks_in_khz; 116 uint32_t voltage_in_mv; 117 }; 118 119 struct dm_pp_clock_levels_with_voltage { 120 uint32_t num_levels; 121 struct dm_pp_clock_with_voltage data[DM_PP_MAX_CLOCK_LEVELS]; 122 }; 123 124 struct dm_pp_single_disp_config { 125 enum signal_type signal; 126 uint8_t transmitter; 127 uint8_t ddi_channel_mapping; 128 uint8_t pipe_idx; 129 uint32_t src_height; 130 uint32_t src_width; 131 uint32_t v_refresh; 132 uint32_t sym_clock; /* HDMI only */ 133 struct dc_link_settings link_settings; /* DP only */ 134 }; 135 136 #define MAX_WM_SETS 4 137 138 enum dm_pp_wm_set_id { 139 WM_SET_A = 0, 140 WM_SET_B, 141 WM_SET_C, 142 WM_SET_D, 143 WM_SET_INVALID = 0xffff, 144 }; 145 146 struct dm_pp_clock_range_for_wm_set { 147 enum dm_pp_wm_set_id wm_set_id; 148 uint32_t wm_min_eng_clk_in_khz; 149 uint32_t wm_max_eng_clk_in_khz; 150 uint32_t wm_min_mem_clk_in_khz; 151 uint32_t wm_max_mem_clk_in_khz; 152 }; 153 154 struct dm_pp_wm_sets_with_clock_ranges { 155 uint32_t num_wm_sets; 156 struct dm_pp_clock_range_for_wm_set wm_clk_ranges[MAX_WM_SETS]; 157 }; 158 159 struct dm_pp_clock_range_for_dmif_wm_set_soc15 { 160 enum dm_pp_wm_set_id wm_set_id; 161 uint32_t wm_min_dcfclk_clk_in_khz; 162 uint32_t wm_max_dcfclk_clk_in_khz; 163 uint32_t wm_min_mem_clk_in_khz; 164 uint32_t wm_max_mem_clk_in_khz; 165 }; 166 167 struct dm_pp_clock_range_for_mcif_wm_set_soc15 { 168 enum dm_pp_wm_set_id wm_set_id; 169 uint32_t wm_min_socclk_clk_in_khz; 170 uint32_t wm_max_socclk_clk_in_khz; 171 uint32_t wm_min_mem_clk_in_khz; 172 uint32_t wm_max_mem_clk_in_khz; 173 }; 174 175 struct dm_pp_wm_sets_with_clock_ranges_soc15 { 176 uint32_t num_wm_dmif_sets; 177 uint32_t num_wm_mcif_sets; 178 struct dm_pp_clock_range_for_dmif_wm_set_soc15 179 wm_dmif_clocks_ranges[MAX_WM_SETS]; 180 struct dm_pp_clock_range_for_mcif_wm_set_soc15 181 wm_mcif_clocks_ranges[MAX_WM_SETS]; 182 }; 183 184 #define MAX_DISPLAY_CONFIGS 6 185 186 struct dm_pp_display_configuration { 187 bool nb_pstate_switch_disable;/* controls NB PState switch */ 188 bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */ 189 bool cpu_pstate_disable; 190 uint32_t cpu_pstate_separation_time; 191 192 uint32_t min_memory_clock_khz; 193 uint32_t min_engine_clock_khz; 194 uint32_t min_engine_clock_deep_sleep_khz; 195 196 uint32_t avail_mclk_switch_time_us; 197 uint32_t avail_mclk_switch_time_in_disp_active_us; 198 uint32_t min_dcfclock_khz; 199 uint32_t min_dcfc_deep_sleep_clock_khz; 200 201 uint32_t disp_clk_khz; 202 203 bool all_displays_in_sync; 204 205 uint8_t display_count; 206 struct dm_pp_single_disp_config disp_configs[MAX_DISPLAY_CONFIGS]; 207 208 /*Controller Index of primary display - used in MCLK SMC switching hang 209 * SW Workaround*/ 210 uint8_t crtc_index; 211 /*htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/ 212 uint32_t line_time_in_us; 213 }; 214 215 struct dm_bl_data_point { 216 /* Brightness level in percentage */ 217 uint8_t luminance; 218 /* Brightness level as effective value in range 0-255, 219 * corresponding to above percentage 220 */ 221 uint8_t signal_level; 222 }; 223 224 /* Total size of the structure should not exceed 256 bytes */ 225 #define BL_DATA_POINTS 99 226 struct dm_acpi_atif_backlight_caps { 227 uint16_t size; /* Bytes 0-1 (2 bytes) */ 228 uint16_t flags; /* Byted 2-3 (2 bytes) */ 229 uint8_t error_code; /* Byte 4 */ 230 uint8_t ac_level_percentage; /* Byte 5 */ 231 uint8_t dc_level_percentage; /* Byte 6 */ 232 uint8_t min_input_signal; /* Byte 7 */ 233 uint8_t max_input_signal; /* Byte 8 */ 234 uint8_t num_data_points; /* Byte 9 */ 235 struct dm_bl_data_point data_points[BL_DATA_POINTS]; /* Bytes 10-207 (198 bytes)*/ 236 }; 237 238 enum dm_acpi_display_type { 239 AcpiDisplayType_LCD1 = 0, 240 AcpiDisplayType_CRT1 = 1, 241 AcpiDisplayType_DFP1 = 3, 242 AcpiDisplayType_CRT2 = 4, 243 AcpiDisplayType_LCD2 = 5, 244 AcpiDisplayType_DFP2 = 7, 245 AcpiDisplayType_DFP3 = 9, 246 AcpiDisplayType_DFP4 = 10, 247 AcpiDisplayType_DFP5 = 11, 248 AcpiDisplayType_DFP6 = 12 249 }; 250 251 struct dm_pp_power_level_change_request { 252 enum dm_pp_clocks_state power_level; 253 }; 254 255 struct dm_pp_clock_for_voltage_req { 256 enum dm_pp_clock_type clk_type; 257 uint32_t clocks_in_khz; 258 }; 259 260 struct dm_pp_static_clock_info { 261 uint32_t max_sclk_khz; 262 uint32_t max_mclk_khz; 263 264 /* max possible display block clocks state */ 265 enum dm_pp_clocks_state max_clocks_state; 266 }; 267 268 struct dtn_min_clk_info { 269 uint32_t disp_clk_khz; 270 uint32_t min_engine_clock_khz; 271 uint32_t min_memory_clock_khz; 272 }; 273 274 #endif 275