1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2011 NetApp, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/param.h>
30 #include <sys/pcpu.h>
31 #include <sys/systm.h>
32 #include <sys/sysctl.h>
33
34 #include <machine/clock.h>
35 #include <machine/cpufunc.h>
36 #include <machine/md_var.h>
37 #include <machine/segments.h>
38 #include <machine/specialreg.h>
39
40 #include <machine/vmm.h>
41
42 #include "vmm_host.h"
43 #include "vmm_ktr.h"
44 #include "vmm_util.h"
45 #include "x86.h"
46
47 SYSCTL_DECL(_hw_vmm);
48 static SYSCTL_NODE(_hw_vmm, OID_AUTO, topology, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
49 NULL);
50
51 #define CPUID_VM_HIGH 0x40000000
52
53 static const char bhyve_id[12] = "bhyve bhyve ";
54
55 static uint64_t bhyve_xcpuids;
56 SYSCTL_ULONG(_hw_vmm, OID_AUTO, bhyve_xcpuids, CTLFLAG_RW, &bhyve_xcpuids, 0,
57 "Number of times an unknown cpuid leaf was accessed");
58
59 static int cpuid_leaf_b = 1;
60 SYSCTL_INT(_hw_vmm_topology, OID_AUTO, cpuid_leaf_b, CTLFLAG_RDTUN,
61 &cpuid_leaf_b, 0, NULL);
62
63 /*
64 * Compute ceil(log2(x)). Returns -1 if x is zero.
65 */
66 static __inline int
log2(u_int x)67 log2(u_int x)
68 {
69
70 return (x == 0 ? -1 : fls(x - 1));
71 }
72
73 int
x86_emulate_cpuid(struct vcpu * vcpu,uint64_t * rax,uint64_t * rbx,uint64_t * rcx,uint64_t * rdx)74 x86_emulate_cpuid(struct vcpu *vcpu, uint64_t *rax, uint64_t *rbx,
75 uint64_t *rcx, uint64_t *rdx)
76 {
77 struct vm *vm = vcpu_vm(vcpu);
78 int vcpu_id = vcpu_vcpuid(vcpu);
79 const struct xsave_limits *limits;
80 uint64_t cr4;
81 int error, enable_invpcid, enable_rdpid, enable_rdtscp, level,
82 width, x2apic_id;
83 unsigned int func, regs[4], logical_cpus, param;
84 enum x2apic_state x2apic_state;
85 uint16_t cores, maxcpus, sockets, threads;
86
87 /*
88 * The function of CPUID is controlled through the provided value of
89 * %eax (and secondarily %ecx, for certain leaf data).
90 */
91 func = (uint32_t)*rax;
92 param = (uint32_t)*rcx;
93
94 VCPU_CTR2(vm, vcpu_id, "cpuid %#x,%#x", func, param);
95
96 /*
97 * Requests for invalid CPUID levels should map to the highest
98 * available level instead.
99 */
100 if (cpu_exthigh != 0 && func >= 0x80000000) {
101 if (func > cpu_exthigh)
102 func = cpu_exthigh;
103 } else if (func >= 0x40000000) {
104 if (func > CPUID_VM_HIGH)
105 func = CPUID_VM_HIGH;
106 } else if (func > cpu_high) {
107 func = cpu_high;
108 }
109
110 /*
111 * In general the approach used for CPU topology is to
112 * advertise a flat topology where all CPUs are packages with
113 * no multi-core or SMT.
114 */
115 switch (func) {
116 /*
117 * Pass these through to the guest
118 */
119 case CPUID_0000_0000:
120 case CPUID_0000_0002:
121 case CPUID_0000_0003:
122 case CPUID_8000_0000:
123 case CPUID_8000_0002:
124 case CPUID_8000_0003:
125 case CPUID_8000_0004:
126 case CPUID_8000_0006:
127 cpuid_count(func, param, regs);
128 break;
129 case CPUID_8000_0008:
130 cpuid_count(func, param, regs);
131 if (vmm_is_svm()) {
132 /*
133 * As on Intel (0000_0007:0, EDX), mask out
134 * unsupported or unsafe AMD extended features
135 * (8000_0008 EBX).
136 */
137 regs[1] &= (AMDFEID_CLZERO | AMDFEID_IRPERF |
138 AMDFEID_XSAVEERPTR);
139
140 vm_get_topology(vm, &sockets, &cores, &threads,
141 &maxcpus);
142 /*
143 * Here, width is ApicIdCoreIdSize, present on
144 * at least Family 15h and newer. It
145 * represents the "number of bits in the
146 * initial apicid that indicate thread id
147 * within a package."
148 *
149 * Our topo_probe_amd() uses it for
150 * pkg_id_shift and other OSes may rely on it.
151 */
152 width = MIN(0xF, log2(threads * cores));
153 if (width < 0x4)
154 width = 0;
155 logical_cpus = MIN(0xFF, threads * cores - 1);
156 regs[2] = (width << AMDID_COREID_SIZE_SHIFT) | logical_cpus;
157 }
158 break;
159
160 case CPUID_8000_0001:
161 cpuid_count(func, param, regs);
162
163 /*
164 * Hide SVM from guest.
165 */
166 regs[2] &= ~AMDID2_SVM;
167
168 /*
169 * Don't advertise extended performance counter MSRs
170 * to the guest.
171 */
172 regs[2] &= ~AMDID2_PCXC;
173 regs[2] &= ~AMDID2_PNXC;
174 regs[2] &= ~AMDID2_PTSCEL2I;
175
176 /*
177 * Don't advertise Instruction Based Sampling feature.
178 */
179 regs[2] &= ~AMDID2_IBS;
180
181 /* NodeID MSR not available */
182 regs[2] &= ~AMDID2_NODE_ID;
183
184 /* Don't advertise the OS visible workaround feature */
185 regs[2] &= ~AMDID2_OSVW;
186
187 /* Hide mwaitx/monitorx capability from the guest */
188 regs[2] &= ~AMDID2_MWAITX;
189
190 /* Advertise RDTSCP if it is enabled. */
191 error = vm_get_capability(vcpu,
192 VM_CAP_RDTSCP, &enable_rdtscp);
193 if (error == 0 && enable_rdtscp)
194 regs[3] |= AMDID_RDTSCP;
195 else
196 regs[3] &= ~AMDID_RDTSCP;
197 break;
198
199 case CPUID_8000_0007:
200 /*
201 * AMD uses this leaf to advertise the processor's
202 * power monitoring and RAS capabilities. These
203 * features are hardware-specific and exposing
204 * them to a guest doesn't make a lot of sense.
205 *
206 * Intel uses this leaf only to advertise the
207 * "Invariant TSC" feature with all other bits
208 * being reserved (set to zero).
209 */
210 regs[0] = 0;
211 regs[1] = 0;
212 regs[2] = 0;
213 regs[3] = 0;
214
215 /*
216 * "Invariant TSC" can be advertised to the guest if:
217 * - host TSC frequency is invariant
218 * - host TSCs are synchronized across physical cpus
219 *
220 * XXX This still falls short because the vcpu
221 * can observe the TSC moving backwards as it
222 * migrates across physical cpus. But at least
223 * it should discourage the guest from using the
224 * TSC to keep track of time.
225 */
226 if (tsc_is_invariant && smp_tsc)
227 regs[3] |= AMDPM_TSC_INVARIANT;
228 break;
229
230 case CPUID_8000_001D:
231 /* AMD Cache topology, like 0000_0004 for Intel. */
232 if (!vmm_is_svm())
233 goto default_leaf;
234
235 /*
236 * Similar to Intel, generate a fictitious cache
237 * topology for the guest with L3 shared by the
238 * package, and L1 and L2 local to a core.
239 */
240 vm_get_topology(vm, &sockets, &cores, &threads,
241 &maxcpus);
242 switch (param) {
243 case 0:
244 logical_cpus = threads;
245 level = 1;
246 func = 1; /* data cache */
247 break;
248 case 1:
249 logical_cpus = threads;
250 level = 2;
251 func = 3; /* unified cache */
252 break;
253 case 2:
254 logical_cpus = threads * cores;
255 level = 3;
256 func = 3; /* unified cache */
257 break;
258 default:
259 logical_cpus = 0;
260 level = 0;
261 func = 0;
262 break;
263 }
264
265 logical_cpus = MIN(0xfff, logical_cpus - 1);
266 regs[0] = (logical_cpus << 14) | (1 << 8) |
267 (level << 5) | func;
268 regs[1] = (func > 0) ? (CACHE_LINE_SIZE - 1) : 0;
269 regs[2] = 0;
270 regs[3] = 0;
271 break;
272
273 case CPUID_8000_001E:
274 /*
275 * AMD Family 16h+ and Hygon Family 18h additional
276 * identifiers.
277 */
278 if (!vmm_is_svm() || CPUID_TO_FAMILY(cpu_id) < 0x16)
279 goto default_leaf;
280
281 vm_get_topology(vm, &sockets, &cores, &threads,
282 &maxcpus);
283 regs[0] = vcpu_id;
284 threads = MIN(0xFF, threads - 1);
285 regs[1] = (threads << 8) |
286 (vcpu_id >> log2(threads + 1));
287 /*
288 * XXX Bhyve topology cannot yet represent >1 node per
289 * processor.
290 */
291 regs[2] = 0;
292 regs[3] = 0;
293 break;
294
295 case CPUID_0000_0001:
296 do_cpuid(1, regs);
297
298 error = vm_get_x2apic_state(vcpu, &x2apic_state);
299 if (error) {
300 panic("x86_emulate_cpuid: error %d "
301 "fetching x2apic state", error);
302 }
303
304 /*
305 * Override the APIC ID only in ebx
306 */
307 regs[1] &= ~(CPUID_LOCAL_APIC_ID);
308 regs[1] |= (vcpu_id << CPUID_0000_0001_APICID_SHIFT);
309
310 /*
311 * Don't expose VMX, SpeedStep, TME or SMX capability.
312 * Advertise x2APIC capability and Hypervisor guest.
313 */
314 regs[2] &= ~(CPUID2_VMX | CPUID2_EST | CPUID2_TM2);
315 regs[2] &= ~(CPUID2_SMX);
316
317 regs[2] |= CPUID2_HV;
318
319 if (x2apic_state != X2APIC_DISABLED)
320 regs[2] |= CPUID2_X2APIC;
321 else
322 regs[2] &= ~CPUID2_X2APIC;
323
324 /*
325 * Only advertise CPUID2_XSAVE in the guest if
326 * the host is using XSAVE.
327 */
328 if (!(regs[2] & CPUID2_OSXSAVE))
329 regs[2] &= ~CPUID2_XSAVE;
330
331 /*
332 * If CPUID2_XSAVE is being advertised and the
333 * guest has set CR4_XSAVE, set
334 * CPUID2_OSXSAVE.
335 */
336 regs[2] &= ~CPUID2_OSXSAVE;
337 if (regs[2] & CPUID2_XSAVE) {
338 error = vm_get_register(vcpu,
339 VM_REG_GUEST_CR4, &cr4);
340 if (error)
341 panic("x86_emulate_cpuid: error %d "
342 "fetching %%cr4", error);
343 if (cr4 & CR4_XSAVE)
344 regs[2] |= CPUID2_OSXSAVE;
345 }
346
347 /*
348 * Hide monitor/mwait until we know how to deal with
349 * these instructions.
350 */
351 regs[2] &= ~CPUID2_MON;
352
353 /*
354 * Hide the performance and debug features.
355 */
356 regs[2] &= ~CPUID2_PDCM;
357
358 /*
359 * No TSC deadline support in the APIC yet
360 */
361 regs[2] &= ~CPUID2_TSCDLT;
362
363 /*
364 * Hide thermal monitoring
365 */
366 regs[3] &= ~(CPUID_ACPI | CPUID_TM);
367
368 /*
369 * Hide the debug store capability.
370 */
371 regs[3] &= ~CPUID_DS;
372
373 /*
374 * Advertise the Machine Check and MTRR capability.
375 *
376 * Some guest OSes (e.g. Windows) will not boot if
377 * these features are absent.
378 */
379 regs[3] |= (CPUID_MCA | CPUID_MCE | CPUID_MTRR);
380
381 vm_get_topology(vm, &sockets, &cores, &threads,
382 &maxcpus);
383 logical_cpus = threads * cores;
384 regs[1] &= ~CPUID_HTT_CORES;
385 regs[1] |= (logical_cpus & 0xff) << 16;
386 regs[3] |= CPUID_HTT;
387 break;
388
389 case CPUID_0000_0004:
390 cpuid_count(func, param, regs);
391
392 if (regs[0] || regs[1] || regs[2] || regs[3]) {
393 vm_get_topology(vm, &sockets, &cores, &threads,
394 &maxcpus);
395 regs[0] &= 0x3ff;
396 regs[0] |= (cores - 1) << 26;
397 /*
398 * Cache topology:
399 * - L1 and L2 are shared only by the logical
400 * processors in a single core.
401 * - L3 and above are shared by all logical
402 * processors in the package.
403 */
404 logical_cpus = threads;
405 level = (regs[0] >> 5) & 0x7;
406 if (level >= 3)
407 logical_cpus *= cores;
408 regs[0] |= (logical_cpus - 1) << 14;
409 }
410 break;
411
412 case CPUID_0000_0007:
413 regs[0] = 0;
414 regs[1] = 0;
415 regs[2] = 0;
416 regs[3] = 0;
417
418 /* leaf 0 */
419 if (param == 0) {
420 cpuid_count(func, param, regs);
421
422 /* Only leaf 0 is supported */
423 regs[0] = 0;
424
425 /*
426 * Expose known-safe features.
427 */
428 regs[1] &= CPUID_STDEXT_FSGSBASE |
429 CPUID_STDEXT_BMI1 | CPUID_STDEXT_HLE |
430 CPUID_STDEXT_AVX2 | CPUID_STDEXT_SMEP |
431 CPUID_STDEXT_BMI2 |
432 CPUID_STDEXT_ERMS | CPUID_STDEXT_RTM |
433 CPUID_STDEXT_AVX512F |
434 CPUID_STDEXT_AVX512DQ |
435 CPUID_STDEXT_RDSEED |
436 CPUID_STDEXT_SMAP |
437 CPUID_STDEXT_AVX512PF |
438 CPUID_STDEXT_AVX512ER |
439 CPUID_STDEXT_AVX512CD | CPUID_STDEXT_SHA |
440 CPUID_STDEXT_AVX512BW |
441 CPUID_STDEXT_AVX512VL;
442 regs[2] &= CPUID_STDEXT2_VAES |
443 CPUID_STDEXT2_VPCLMULQDQ;
444 regs[3] &= CPUID_STDEXT3_MD_CLEAR;
445
446 /* Advertise RDPID if it is enabled. */
447 error = vm_get_capability(vcpu, VM_CAP_RDPID,
448 &enable_rdpid);
449 if (error == 0 && enable_rdpid)
450 regs[2] |= CPUID_STDEXT2_RDPID;
451
452 /* Advertise INVPCID if it is enabled. */
453 error = vm_get_capability(vcpu,
454 VM_CAP_ENABLE_INVPCID, &enable_invpcid);
455 if (error == 0 && enable_invpcid)
456 regs[1] |= CPUID_STDEXT_INVPCID;
457 }
458 break;
459
460 case CPUID_0000_0006:
461 regs[0] = CPUTPM1_ARAT;
462 regs[1] = 0;
463 regs[2] = 0;
464 regs[3] = 0;
465 break;
466
467 case CPUID_0000_000A:
468 /*
469 * Handle the access, but report 0 for
470 * all options
471 */
472 regs[0] = 0;
473 regs[1] = 0;
474 regs[2] = 0;
475 regs[3] = 0;
476 break;
477
478 case CPUID_0000_000B:
479 /*
480 * Intel processor topology enumeration
481 */
482 if (vmm_is_intel()) {
483 vm_get_topology(vm, &sockets, &cores, &threads,
484 &maxcpus);
485 if (param == 0) {
486 logical_cpus = threads;
487 width = log2(logical_cpus);
488 level = CPUID_TYPE_SMT;
489 x2apic_id = vcpu_id;
490 }
491
492 if (param == 1) {
493 logical_cpus = threads * cores;
494 width = log2(logical_cpus);
495 level = CPUID_TYPE_CORE;
496 x2apic_id = vcpu_id;
497 }
498
499 if (!cpuid_leaf_b || param >= 2) {
500 width = 0;
501 logical_cpus = 0;
502 level = 0;
503 x2apic_id = 0;
504 }
505
506 regs[0] = width & 0x1f;
507 regs[1] = logical_cpus & 0xffff;
508 regs[2] = (level << 8) | (param & 0xff);
509 regs[3] = x2apic_id;
510 } else {
511 regs[0] = 0;
512 regs[1] = 0;
513 regs[2] = 0;
514 regs[3] = 0;
515 }
516 break;
517
518 case CPUID_0000_000D:
519 limits = vmm_get_xsave_limits();
520 if (!limits->xsave_enabled) {
521 regs[0] = 0;
522 regs[1] = 0;
523 regs[2] = 0;
524 regs[3] = 0;
525 break;
526 }
527
528 cpuid_count(func, param, regs);
529 switch (param) {
530 case 0:
531 /*
532 * Only permit the guest to use bits
533 * that are active in the host in
534 * %xcr0. Also, claim that the
535 * maximum save area size is
536 * equivalent to the host's current
537 * save area size. Since this runs
538 * "inside" of vmrun(), it runs with
539 * the guest's xcr0, so the current
540 * save area size is correct as-is.
541 */
542 regs[0] &= limits->xcr0_allowed;
543 regs[2] = limits->xsave_max_size;
544 regs[3] &= (limits->xcr0_allowed >> 32);
545 break;
546 case 1:
547 /* Only permit XSAVEOPT. */
548 regs[0] &= CPUID_EXTSTATE_XSAVEOPT;
549 regs[1] = 0;
550 regs[2] = 0;
551 regs[3] = 0;
552 break;
553 default:
554 /*
555 * If the leaf is for a permitted feature,
556 * pass through as-is, otherwise return
557 * all zeroes.
558 */
559 if (!(limits->xcr0_allowed & (1ul << param))) {
560 regs[0] = 0;
561 regs[1] = 0;
562 regs[2] = 0;
563 regs[3] = 0;
564 }
565 break;
566 }
567 break;
568
569 case CPUID_0000_000F:
570 case CPUID_0000_0010:
571 /*
572 * Do not report any Resource Director Technology
573 * capabilities. Exposing control of cache or memory
574 * controller resource partitioning to the guest is not
575 * at all sensible.
576 *
577 * This is already hidden at a high level by masking of
578 * leaf 0x7. Even still, a guest may look here for
579 * detailed capability information.
580 */
581 regs[0] = 0;
582 regs[1] = 0;
583 regs[2] = 0;
584 regs[3] = 0;
585 break;
586
587 case CPUID_0000_0015:
588 /*
589 * Don't report CPU TSC/Crystal ratio and clock
590 * values since guests may use these to derive the
591 * local APIC frequency..
592 */
593 regs[0] = 0;
594 regs[1] = 0;
595 regs[2] = 0;
596 regs[3] = 0;
597 break;
598
599 case 0x40000000:
600 regs[0] = CPUID_VM_HIGH;
601 bcopy(bhyve_id, ®s[1], 4);
602 bcopy(bhyve_id + 4, ®s[2], 4);
603 bcopy(bhyve_id + 8, ®s[3], 4);
604 break;
605
606 default:
607 default_leaf:
608 /*
609 * The leaf value has already been clamped so
610 * simply pass this through, keeping count of
611 * how many unhandled leaf values have been seen.
612 */
613 atomic_add_long(&bhyve_xcpuids, 1);
614 cpuid_count(func, param, regs);
615 break;
616 }
617
618 /*
619 * CPUID clears the upper 32-bits of the long-mode registers.
620 */
621 *rax = regs[0];
622 *rbx = regs[1];
623 *rcx = regs[2];
624 *rdx = regs[3];
625
626 return (1);
627 }
628
629 bool
vm_cpuid_capability(struct vcpu * vcpu,enum vm_cpuid_capability cap)630 vm_cpuid_capability(struct vcpu *vcpu, enum vm_cpuid_capability cap)
631 {
632 bool rv;
633
634 KASSERT(cap > 0 && cap < VCC_LAST, ("%s: invalid vm_cpu_capability %d",
635 __func__, cap));
636
637 /*
638 * Simply passthrough the capabilities of the host cpu for now.
639 */
640 rv = false;
641 switch (cap) {
642 case VCC_NO_EXECUTE:
643 if (amd_feature & AMDID_NX)
644 rv = true;
645 break;
646 case VCC_FFXSR:
647 if (amd_feature & AMDID_FFXSR)
648 rv = true;
649 break;
650 case VCC_TCE:
651 if (amd_feature2 & AMDID2_TCE)
652 rv = true;
653 break;
654 default:
655 panic("%s: unknown vm_cpu_capability %d", __func__, cap);
656 }
657 return (rv);
658 }
659
660 int
vm_rdmtrr(struct vm_mtrr * mtrr,u_int num,uint64_t * val)661 vm_rdmtrr(struct vm_mtrr *mtrr, u_int num, uint64_t *val)
662 {
663 switch (num) {
664 case MSR_MTRRcap:
665 *val = MTRR_CAP_WC | MTRR_CAP_FIXED | VMM_MTRR_VAR_MAX;
666 break;
667 case MSR_MTRRdefType:
668 *val = mtrr->def_type;
669 break;
670 case MSR_MTRR4kBase ... MSR_MTRR4kBase + 7:
671 *val = mtrr->fixed4k[num - MSR_MTRR4kBase];
672 break;
673 case MSR_MTRR16kBase ... MSR_MTRR16kBase + 1:
674 *val = mtrr->fixed16k[num - MSR_MTRR16kBase];
675 break;
676 case MSR_MTRR64kBase:
677 *val = mtrr->fixed64k;
678 break;
679 case MSR_MTRRVarBase ... MSR_MTRRVarBase + (VMM_MTRR_VAR_MAX * 2) - 1: {
680 u_int offset = num - MSR_MTRRVarBase;
681 if (offset % 2 == 0) {
682 *val = mtrr->var[offset / 2].base;
683 } else {
684 *val = mtrr->var[offset / 2].mask;
685 }
686 break;
687 }
688 default:
689 return (-1);
690 }
691
692 return (0);
693 }
694
695 int
vm_wrmtrr(struct vm_mtrr * mtrr,u_int num,uint64_t val)696 vm_wrmtrr(struct vm_mtrr *mtrr, u_int num, uint64_t val)
697 {
698 switch (num) {
699 case MSR_MTRRcap:
700 /* MTRRCAP is read only */
701 return (-1);
702 case MSR_MTRRdefType:
703 if (val & ~VMM_MTRR_DEF_MASK) {
704 /* generate #GP on writes to reserved fields */
705 return (-1);
706 }
707 mtrr->def_type = val;
708 break;
709 case MSR_MTRR4kBase ... MSR_MTRR4kBase + 7:
710 mtrr->fixed4k[num - MSR_MTRR4kBase] = val;
711 break;
712 case MSR_MTRR16kBase ... MSR_MTRR16kBase + 1:
713 mtrr->fixed16k[num - MSR_MTRR16kBase] = val;
714 break;
715 case MSR_MTRR64kBase:
716 mtrr->fixed64k = val;
717 break;
718 case MSR_MTRRVarBase ... MSR_MTRRVarBase + (VMM_MTRR_VAR_MAX * 2) - 1: {
719 u_int offset = num - MSR_MTRRVarBase;
720 if (offset % 2 == 0) {
721 if (val & ~VMM_MTRR_PHYSBASE_MASK) {
722 /* generate #GP on writes to reserved fields */
723 return (-1);
724 }
725 mtrr->var[offset / 2].base = val;
726 } else {
727 if (val & ~VMM_MTRR_PHYSMASK_MASK) {
728 /* generate #GP on writes to reserved fields */
729 return (-1);
730 }
731 mtrr->var[offset / 2].mask = val;
732 }
733 break;
734 }
735 default:
736 return (-1);
737 }
738
739 return (0);
740 }
741