1 /* $OpenBSD: if_xe.c,v 1.64 2024/05/26 08:46:28 jsg Exp $ */
2
3 /*
4 * Copyright (c) 1999 Niklas Hallqvist, Brandon Creighton, Job de Haas
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Niklas Hallqvist,
18 * C Stone and Job de Haas.
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 /*
35 * A driver for Xircom ethernet PC-cards.
36 *
37 * The driver has been inspired by the xirc2ps_cs.c driver found in Linux'
38 * PCMCIA package written by Werner Koch <werner.koch@guug.de>:
39 * [xirc2ps_cs.c wk 14.04.97] (1.31 1998/12/09 19:32:55)
40 * I will note that no code was used verbatim from that driver as it is under
41 * the much too strong GNU General Public License, it was only used as a
42 * "specification" of sorts.
43 * Other inspirations have been if_fxp.c, if_ep_pcmcia.c and elink3.c as
44 * they were found in OpenBSD 2.4.
45 */
46
47 #include "bpfilter.h"
48
49 #include <sys/param.h>
50 #include <sys/systm.h>
51 #include <sys/device.h>
52 #include <sys/ioctl.h>
53 #include <sys/mbuf.h>
54 #include <sys/malloc.h>
55 #include <sys/syslog.h>
56
57 #include <net/if.h>
58 #include <net/if_media.h>
59
60 #include <netinet/in.h>
61 #include <netinet/if_ether.h>
62
63 #if NBPFILTER > 0
64 #include <net/bpf.h>
65 #endif
66
67 /*
68 * Maximum number of bytes to read per interrupt. Linux recommends
69 * somewhere between 2000-22000.
70 * XXX This is currently a hard maximum.
71 */
72 #define MAX_BYTES_INTR 12000
73
74 #include <dev/mii/miivar.h>
75
76 #include <dev/pcmcia/pcmciareg.h>
77 #include <dev/pcmcia/pcmciavar.h>
78 #include <dev/pcmcia/pcmciadevs.h>
79 #include <dev/pcmcia/if_xereg.h>
80
81 #ifdef __GNUC__
82 #define INLINE __inline
83 #else
84 #define INLINE
85 #endif /* __GNUC__ */
86
87 #ifdef XEDEBUG
88
89 #define XED_CONFIG 0x1
90 #define XED_MII 0x2
91 #define XED_INTR 0x4
92 #define XED_FIFO 0x8
93
94 #ifndef XEDEBUG_DEF
95 #define XEDEBUG_DEF (XED_CONFIG|XED_INTR)
96 #endif /* XEDEBUG_DEF */
97
98 int xedebug = XEDEBUG_DEF;
99
100 #define DPRINTF(cat, x) if (xedebug & (cat)) printf x
101
102 #else /* XEDEBUG */
103 #define DPRINTF(cat, x) (void)0
104 #endif /* XEDEBUG */
105
106 int xe_pcmcia_match(struct device *, void *, void *);
107 void xe_pcmcia_attach(struct device *, struct device *, void *);
108 int xe_pcmcia_detach(struct device *, int);
109 int xe_pcmcia_activate(struct device *, int);
110
111 /*
112 * In case this chipset ever turns up out of pcmcia attachments (very
113 * unlikely) do the driver splitup.
114 */
115 struct xe_softc {
116 struct device sc_dev; /* Generic device info */
117 u_int32_t sc_flags; /* Misc. flags */
118 void *sc_ih; /* Interrupt handler */
119 struct arpcom sc_arpcom; /* Ethernet common part */
120 struct ifmedia sc_media; /* Media control */
121 struct mii_data sc_mii; /* MII media information */
122 int sc_all_mcasts; /* Receive all multicasts */
123 bus_space_tag_t sc_bst; /* Bus cookie */
124 bus_space_handle_t sc_bsh; /* Bus I/O handle */
125 bus_size_t sc_offset; /* Offset of registers */
126 u_int8_t sc_rev; /* Chip revision */
127 };
128
129 #define XEF_MOHAWK 0x001
130 #define XEF_DINGO 0x002
131 #define XEF_MODEM 0x004
132 #define XEF_UNSUPPORTED 0x008
133 #define XEF_CE 0x010
134 #define XEF_CE2 0x020
135 #define XEF_CE3 0x040
136 #define XEF_CE33 0x080
137 #define XEF_CE56 0x100
138
139 struct xe_pcmcia_softc {
140 struct xe_softc sc_xe; /* Generic device info */
141 struct pcmcia_mem_handle sc_pcmh; /* PCMCIA memspace info */
142 int sc_mem_window; /* mem window */
143 struct pcmcia_io_handle sc_pcioh; /* iospace info */
144 int sc_io_window; /* io window info */
145 struct pcmcia_function *sc_pf; /* PCMCIA function */
146 };
147
148 /* Autoconfig definition of driver back-end */
149 struct cfdriver xe_cd = {
150 NULL, "xe", DV_IFNET
151 };
152
153 const struct cfattach xe_pcmcia_ca = {
154 sizeof (struct xe_pcmcia_softc), xe_pcmcia_match, xe_pcmcia_attach,
155 xe_pcmcia_detach, xe_pcmcia_activate
156 };
157
158 void xe_cycle_power(struct xe_softc *);
159 void xe_full_reset(struct xe_softc *);
160 void xe_init(struct xe_softc *);
161 int xe_intr(void *);
162 int xe_ioctl(struct ifnet *, u_long, caddr_t);
163 int xe_mdi_read(struct device *, int, int);
164 void xe_mdi_write(struct device *, int, int, int);
165 int xe_mediachange(struct ifnet *);
166 void xe_mediastatus(struct ifnet *, struct ifmediareq *);
167 int xe_pcmcia_funce_enaddr(struct device *, u_int8_t *);
168 u_int32_t xe_pcmcia_interpret_manfid(struct device *);
169 int xe_pcmcia_lan_nid_ciscallback(struct pcmcia_tuple *, void *);
170 int xe_pcmcia_manfid_ciscallback(struct pcmcia_tuple *, void *);
171 u_int16_t xe_get(struct xe_softc *);
172 void xe_reset(struct xe_softc *);
173 void xe_set_address(struct xe_softc *);
174 void xe_start(struct ifnet *);
175 void xe_statchg(struct device *);
176 void xe_stop(struct xe_softc *);
177 void xe_watchdog(struct ifnet *);
178 #ifdef XEDEBUG
179 void xe_reg_dump(struct xe_softc *);
180 #endif /* XEDEBUG */
181
182 int
xe_pcmcia_match(struct device * parent,void * match,void * aux)183 xe_pcmcia_match(struct device *parent, void *match, void *aux)
184 {
185 struct pcmcia_attach_args *pa = aux;
186
187 if (pa->pf->function != PCMCIA_FUNCTION_NETWORK)
188 return (0);
189
190 switch (pa->manufacturer) {
191 case PCMCIA_VENDOR_COMPAQ:
192 case PCMCIA_VENDOR_COMPAQ2:
193 return (0);
194
195 case PCMCIA_VENDOR_INTEL:
196 case PCMCIA_VENDOR_XIRCOM:
197 /* XXX Per-productid checking here. */
198 return (1);
199
200 default:
201 return (0);
202 }
203 }
204
205 void
xe_pcmcia_attach(struct device * parent,struct device * self,void * aux)206 xe_pcmcia_attach(struct device *parent, struct device *self, void *aux)
207 {
208 struct xe_pcmcia_softc *psc = (struct xe_pcmcia_softc *)self;
209 struct xe_softc *sc = &psc->sc_xe;
210 struct pcmcia_attach_args *pa = aux;
211 struct pcmcia_function *pf = pa->pf;
212 struct pcmcia_config_entry *cfe = NULL;
213 struct ifnet *ifp;
214 u_int8_t myla[ETHER_ADDR_LEN], *enaddr = NULL;
215 int state = 0;
216 struct pcmcia_mem_handle pcmh;
217 int ccr_window;
218 bus_size_t ccr_offset;
219 const char *intrstr;
220
221 psc->sc_pf = pf;
222
223 #if 0
224 /* Figure out what card we are. */
225 sc->sc_flags = xe_pcmcia_interpret_manfid(parent);
226 #endif
227 if (sc->sc_flags & XEF_UNSUPPORTED) {
228 printf(": card unsupported\n");
229 goto bad;
230 }
231
232 /* Tell the pcmcia framework where the CCR is. */
233 pf->ccr_base = 0x800;
234 pf->ccr_mask = 0x67;
235
236 /* Fake a cfe. */
237 SIMPLEQ_FIRST(&pa->pf->cfe_head) = cfe = (struct pcmcia_config_entry *)
238 malloc(sizeof *cfe, M_DEVBUF, M_NOWAIT | M_ZERO);
239 if (!cfe) {
240 printf(": function enable failed\n");
241 return;
242 }
243
244 /*
245 * XXX Use preprocessor symbols instead.
246 * Enable ethernet & its interrupts, wiring them to -INT
247 * No I/O base.
248 */
249 cfe->number = 0x5;
250 cfe->flags = 0; /* XXX Check! */
251 cfe->iftype = PCMCIA_IFTYPE_IO;
252 cfe->num_iospace = 0;
253 cfe->num_memspace = 0;
254 cfe->irqmask = 0x8eb0;
255
256 /* Enable the card. */
257 pcmcia_function_init(pa->pf, cfe);
258 if (pcmcia_function_enable(pa->pf)) {
259 printf(": function enable failed\n");
260 goto bad;
261 }
262
263 state++;
264
265 if (pcmcia_io_alloc(pa->pf, 0, 16, 16, &psc->sc_pcioh)) {
266 printf(": io allocation failed\n");
267 goto bad;
268 }
269
270 state++;
271
272 if (pcmcia_io_map(pa->pf, PCMCIA_WIDTH_IO16, 0, 16, &psc->sc_pcioh,
273 &psc->sc_io_window)) {
274 printf(": can't map io space\n");
275 goto bad;
276 }
277 sc->sc_bst = psc->sc_pcioh.iot;
278 sc->sc_bsh = psc->sc_pcioh.ioh;
279 sc->sc_offset = 0;
280
281 printf(" port 0x%lx/%d", psc->sc_pcioh.addr, 16);
282
283 #if 0
284 if (pcmcia_mem_alloc(pf, 16, &psc->sc_pcmh)) {
285 printf(": pcmcia memory allocation failed\n");
286 goto bad;
287 }
288 state++;
289
290 if (pcmcia_mem_map(pf, PCMCIA_MEM_ATTR, 0x300, 16, &psc->sc_pcmh,
291 &sc->sc_offset, &psc->sc_mem_window)) {
292 printf(": pcmcia memory mapping failed\n");
293 goto bad;
294 }
295
296 sc->sc_bst = psc->sc_pcmh.memt;
297 sc->sc_bsh = psc->sc_pcmh.memh;
298 #endif
299
300 /* Figure out what card we are. */
301 sc->sc_flags = xe_pcmcia_interpret_manfid(parent);
302
303 /*
304 * Configuration as advised by DINGO documentation.
305 * We only know about this flag after the manfid interpretation.
306 * Dingo has some extra configuration registers in the CCR space.
307 */
308 if (sc->sc_flags & XEF_DINGO) {
309 if (pcmcia_mem_alloc(pf, PCMCIA_CCR_SIZE_DINGO, &pcmh)) {
310 DPRINTF(XED_CONFIG, ("bad mem alloc\n"));
311 goto bad;
312 }
313
314 if (pcmcia_mem_map(pf, PCMCIA_MEM_ATTR, pf->ccr_base,
315 PCMCIA_CCR_SIZE_DINGO, &pcmh, &ccr_offset,
316 &ccr_window)) {
317 DPRINTF(XED_CONFIG, ("bad mem map\n"));
318 pcmcia_mem_free(pf, &pcmh);
319 goto bad;
320 }
321
322 bus_space_write_1(pcmh.memt, pcmh.memh,
323 ccr_offset + PCMCIA_CCR_DCOR0, PCMCIA_CCR_DCOR0_SFINT);
324 bus_space_write_1(pcmh.memt, pcmh.memh,
325 ccr_offset + PCMCIA_CCR_DCOR1,
326 PCMCIA_CCR_DCOR1_FORCE_LEVIREQ | PCMCIA_CCR_DCOR1_D6);
327 bus_space_write_1(pcmh.memt, pcmh.memh,
328 ccr_offset + PCMCIA_CCR_DCOR2, 0);
329 bus_space_write_1(pcmh.memt, pcmh.memh,
330 ccr_offset + PCMCIA_CCR_DCOR3, 0);
331 bus_space_write_1(pcmh.memt, pcmh.memh,
332 ccr_offset + PCMCIA_CCR_DCOR4, 0);
333
334 /* We don't need them anymore and can free them (I think). */
335 pcmcia_mem_unmap(pf, ccr_window);
336 pcmcia_mem_free(pf, &pcmh);
337 }
338
339 /*
340 * Try to get the ethernet address from FUNCE/LAN_NID tuple.
341 */
342 if (xe_pcmcia_funce_enaddr(parent, myla))
343 enaddr = myla;
344 ifp = &sc->sc_arpcom.ac_if;
345 if (enaddr)
346 bcopy(enaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN);
347 else {
348 printf(", unable to get ethernet address\n");
349 goto bad;
350 }
351
352 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
353 ifp->if_softc = sc;
354 ifp->if_flags =
355 IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
356 ifp->if_ioctl = xe_ioctl;
357 ifp->if_start = xe_start;
358 ifp->if_watchdog = xe_watchdog;
359
360 /* Establish the interrupt. */
361 sc->sc_ih = pcmcia_intr_establish(pa->pf, IPL_NET, xe_intr, sc,
362 sc->sc_dev.dv_xname);
363 if (sc->sc_ih == NULL) {
364 printf(", couldn't establish interrupt\n");
365 goto bad;
366 }
367 intrstr = pcmcia_intr_string(psc->sc_pf, sc->sc_ih);
368 printf("%s%s: address %s\n", *intrstr ? ", " : "", intrstr,
369 ether_sprintf(sc->sc_arpcom.ac_enaddr));
370
371 /* Reset and initialize the card. */
372 xe_full_reset(sc);
373
374 /* Initialize our media structures and probe the phy. */
375 sc->sc_mii.mii_ifp = ifp;
376 sc->sc_mii.mii_readreg = xe_mdi_read;
377 sc->sc_mii.mii_writereg = xe_mdi_write;
378 sc->sc_mii.mii_statchg = xe_statchg;
379 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, xe_mediachange,
380 xe_mediastatus);
381 DPRINTF(XED_MII | XED_CONFIG,
382 ("bmsr %x\n", xe_mdi_read(&sc->sc_dev, 0, 1)));
383 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY,
384 0);
385 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL)
386 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO, 0,
387 NULL);
388 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO);
389
390 /*
391 * Attach the interface.
392 */
393 if_attach(ifp);
394 ether_ifattach(ifp);
395
396 /*
397 * Reset and initialize the card again for DINGO (as found in Linux
398 * driver). Without this Dingo will get a watchdog timeout the first
399 * time. The ugly media tickling seems to be necessary for getting
400 * autonegotiation to work too.
401 */
402 if (sc->sc_flags & XEF_DINGO) {
403 xe_full_reset(sc);
404 xe_init(sc);
405 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO);
406 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_NONE);
407 xe_stop(sc);
408 }
409 return;
410
411 bad:
412 if (state > 2)
413 pcmcia_io_unmap(pf, psc->sc_io_window);
414 if (state > 1)
415 pcmcia_io_free(pf, &psc->sc_pcioh);
416 if (state > 0)
417 pcmcia_function_disable(pa->pf);
418 free(cfe, M_DEVBUF, 0);
419 }
420
421 int
xe_pcmcia_detach(struct device * dev,int flags)422 xe_pcmcia_detach(struct device *dev, int flags)
423 {
424 struct xe_pcmcia_softc *psc = (struct xe_pcmcia_softc *)dev;
425 struct xe_softc *sc = &psc->sc_xe;
426 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
427 int rv = 0;
428
429 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY);
430 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY);
431
432 pcmcia_io_unmap(psc->sc_pf, psc->sc_io_window);
433 pcmcia_io_free(psc->sc_pf, &psc->sc_pcioh);
434
435 ether_ifdetach(ifp);
436 if_detach(ifp);
437
438 return (rv);
439 }
440
441 int
xe_pcmcia_activate(struct device * dev,int act)442 xe_pcmcia_activate(struct device *dev, int act)
443 {
444 struct xe_pcmcia_softc *sc = (struct xe_pcmcia_softc *)dev;
445 struct ifnet *ifp = &sc->sc_xe.sc_arpcom.ac_if;
446
447 switch (act) {
448 case DVACT_SUSPEND:
449 if (ifp->if_flags & IFF_RUNNING)
450 xe_stop(&sc->sc_xe);
451 ifp->if_flags &= ~IFF_RUNNING;
452 if (sc->sc_xe.sc_ih)
453 pcmcia_intr_disestablish(sc->sc_pf, sc->sc_xe.sc_ih);
454 sc->sc_xe.sc_ih = NULL;
455 pcmcia_function_disable(sc->sc_pf);
456 break;
457 case DVACT_RESUME:
458 pcmcia_function_enable(sc->sc_pf);
459 sc->sc_xe.sc_ih = pcmcia_intr_establish(sc->sc_pf, IPL_NET,
460 xe_intr, sc, sc->sc_xe.sc_dev.dv_xname);
461 /* XXX this is a ridiculous */
462 xe_reset(&sc->sc_xe);
463 if ((ifp->if_flags & IFF_UP) == 0)
464 xe_stop(&sc->sc_xe);
465 break;
466 case DVACT_DEACTIVATE:
467 ifp->if_timer = 0;
468 ifp->if_flags &= ~IFF_RUNNING;
469 if (sc->sc_xe.sc_ih)
470 pcmcia_intr_disestablish(sc->sc_pf, sc->sc_xe.sc_ih);
471 sc->sc_xe.sc_ih = NULL;
472 pcmcia_function_disable(sc->sc_pf);
473 break;
474 }
475 return (0);
476 }
477
478 /*
479 * XXX These two functions might be OK to factor out into pcmcia.c since
480 * if_sm_pcmcia.c uses similar ones.
481 */
482 int
xe_pcmcia_funce_enaddr(struct device * parent,u_int8_t * myla)483 xe_pcmcia_funce_enaddr(struct device *parent, u_int8_t *myla)
484 {
485 /* XXX The Linux driver has more ways to do this in case of failure. */
486 return (pcmcia_scan_cis(parent, xe_pcmcia_lan_nid_ciscallback, myla));
487 }
488
489 int
xe_pcmcia_lan_nid_ciscallback(struct pcmcia_tuple * tuple,void * arg)490 xe_pcmcia_lan_nid_ciscallback(struct pcmcia_tuple *tuple, void *arg)
491 {
492 u_int8_t *myla = arg;
493 int i;
494
495 if (tuple->code == PCMCIA_CISTPL_FUNCE) {
496 if (tuple->length < 2)
497 return (0);
498
499 switch (pcmcia_tuple_read_1(tuple, 0)) {
500 case PCMCIA_TPLFE_TYPE_LAN_NID:
501 if (pcmcia_tuple_read_1(tuple, 1) != ETHER_ADDR_LEN)
502 return (0);
503 break;
504
505 case 0x02:
506 /*
507 * Not sure about this, I don't have a CE2
508 * that puts the ethernet addr here.
509 */
510 if (pcmcia_tuple_read_1(tuple, 1) != 13)
511 return (0);
512 break;
513
514 default:
515 return (0);
516 }
517
518 for (i = 0; i < ETHER_ADDR_LEN; i++)
519 myla[i] = pcmcia_tuple_read_1(tuple, i + 2);
520 return (1);
521 }
522
523 /* Yet another spot where this might be. */
524 if (tuple->code == 0x89) {
525 pcmcia_tuple_read_1(tuple, 1);
526 for (i = 0; i < ETHER_ADDR_LEN; i++)
527 myla[i] = pcmcia_tuple_read_1(tuple, i + 2);
528 return (1);
529 }
530 return (0);
531 }
532
533 u_int32_t
xe_pcmcia_interpret_manfid(struct device * parent)534 xe_pcmcia_interpret_manfid(struct device *parent)
535 {
536 u_int32_t flags = 0;
537 struct pcmcia_softc *psc = (struct pcmcia_softc *)parent;
538 char *tptr;
539
540 if (!pcmcia_scan_cis(parent, xe_pcmcia_manfid_ciscallback, &flags))
541 return (XEF_UNSUPPORTED);
542
543 if (flags & XEF_CE) {
544 tptr = memchr(psc->card.cis1_info[2], 'C',
545 strlen(psc->card.cis1_info[2]));
546 /* XXX not sure if other CE2s hide "CE2" in different places */
547 if (tptr && *(tptr + 1) == 'E' && *(tptr + 2) == '2') {
548 flags ^= (XEF_CE | XEF_UNSUPPORTED);
549 flags |= XEF_CE2;
550 }
551 }
552 return (flags);
553 }
554
555 int
xe_pcmcia_manfid_ciscallback(struct pcmcia_tuple * tuple,void * arg)556 xe_pcmcia_manfid_ciscallback(struct pcmcia_tuple *tuple, void *arg)
557 {
558 u_int32_t *flagsp = arg;
559 u_int8_t media, product;
560
561 if (tuple->code == PCMCIA_CISTPL_MANFID) {
562 if (tuple->length < 2)
563 return (0);
564
565 media = pcmcia_tuple_read_1(tuple, 3);
566 product = pcmcia_tuple_read_1(tuple, 4);
567
568 if (!(product & XEPROD_CREDITCARD) ||
569 !(media & XEMEDIA_ETHER)) {
570 *flagsp |= XEF_UNSUPPORTED;
571 return (1);
572 }
573
574 if (media & XEMEDIA_MODEM)
575 *flagsp |= XEF_MODEM;
576
577 switch (product & XEPROD_IDMASK) {
578 case 1:
579 /* XXX Can be CE2 too (we double-check later). */
580 *flagsp |= XEF_CE | XEF_UNSUPPORTED;
581 break;
582 case 2:
583 *flagsp |= XEF_CE2;
584 break;
585 case 3:
586 if (!(*flagsp & XEF_MODEM))
587 *flagsp |= XEF_MOHAWK;
588 *flagsp |= XEF_CE3;
589 break;
590 case 4:
591 *flagsp |= XEF_CE33;
592 break;
593 case 5:
594 *flagsp |= XEF_CE56 | XEF_MOHAWK;
595 break;
596 case 6:
597 case 7:
598 *flagsp |= XEF_CE56 | XEF_MOHAWK | XEF_DINGO;
599 break;
600 default:
601 *flagsp |= XEF_UNSUPPORTED;
602 break;
603 }
604
605 return (1);
606 }
607 return (0);
608 }
609
610 int
xe_intr(void * arg)611 xe_intr(void *arg)
612 {
613 struct xe_softc *sc = arg;
614 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
615 u_int8_t esr, rsr, isr, rx_status, savedpage;
616 u_int16_t tx_status, recvcount = 0, tempint;
617
618 ifp->if_timer = 0; /* turn watchdog timer off */
619
620 if (sc->sc_flags & XEF_MOHAWK) {
621 /* Disable interrupt (Linux does it). */
622 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR,
623 0);
624 }
625
626 savedpage =
627 bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + PR);
628
629 PAGE(sc, 0);
630 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + ESR);
631 isr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + ISR0);
632 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RSR);
633
634 /* Check to see if card has been ejected. */
635 if (isr == 0xff) {
636 printf("%s: interrupt for dead card\n", sc->sc_dev.dv_xname);
637 goto end;
638 }
639
640 PAGE(sc, 40);
641 rx_status =
642 bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RXST0);
643 tx_status =
644 bus_space_read_2(sc->sc_bst, sc->sc_bsh, sc->sc_offset + TXST0);
645
646 /*
647 * XXX Linux writes to RXST0 and TXST* here. My CE2 works just fine
648 * without it, and I can't see an obvious reason for it.
649 */
650
651 PAGE(sc, 0);
652 while (esr & FULL_PKT_RCV) {
653 if (!(rsr & RSR_RX_OK))
654 break;
655
656 /* Compare bytes read this interrupt to hard maximum. */
657 if (recvcount > MAX_BYTES_INTR) {
658 DPRINTF(XED_INTR,
659 ("%s: too many bytes this interrupt\n",
660 sc->sc_dev.dv_xname));
661 ifp->if_iqdrops++;
662 /* Drop packet. */
663 bus_space_write_2(sc->sc_bst, sc->sc_bsh,
664 sc->sc_offset + DO0, DO_SKIP_RX_PKT);
665 }
666 tempint = xe_get(sc);
667 recvcount += tempint;
668 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh,
669 sc->sc_offset + ESR);
670 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh,
671 sc->sc_offset + RSR);
672 }
673
674 /* Packet too long? */
675 if (rsr & RSR_TOO_LONG) {
676 ifp->if_ierrors++;
677 DPRINTF(XED_INTR,
678 ("%s: packet too long\n", sc->sc_dev.dv_xname));
679 }
680
681 /* CRC error? */
682 if (rsr & RSR_CRCERR) {
683 ifp->if_ierrors++;
684 DPRINTF(XED_INTR,
685 ("%s: CRC error detected\n", sc->sc_dev.dv_xname));
686 }
687
688 /* Alignment error? */
689 if (rsr & RSR_ALIGNERR) {
690 ifp->if_ierrors++;
691 DPRINTF(XED_INTR,
692 ("%s: alignment error detected\n", sc->sc_dev.dv_xname));
693 }
694
695 /* Check for rx overrun. */
696 if (rx_status & RX_OVERRUN) {
697 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR,
698 CLR_RX_OVERRUN);
699 DPRINTF(XED_INTR, ("overrun cleared\n"));
700 }
701
702 /* Try to start more packets transmitting. */
703 if (ifq_empty(&ifp->if_snd) == 0)
704 xe_start(ifp);
705
706 /* Detected excessive collisions? */
707 if (tx_status & EXCESSIVE_COLL) {
708 DPRINTF(XED_INTR,
709 ("%s: excessive collisions\n", sc->sc_dev.dv_xname));
710 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR,
711 RESTART_TX);
712 ifp->if_oerrors++;
713 }
714
715 if (tx_status & TX_ABORT)
716 ifp->if_oerrors++;
717
718 end:
719 /* Reenable interrupts. */
720 PAGE(sc, savedpage);
721 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR,
722 ENABLE_INT);
723
724 return (1);
725 }
726
727 u_int16_t
xe_get(struct xe_softc * sc)728 xe_get(struct xe_softc *sc)
729 {
730 u_int8_t rsr;
731 struct mbuf *top, **mp, *m;
732 struct mbuf_list ml = MBUF_LIST_INITIALIZER();
733 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
734 u_int16_t pktlen, len, recvcount = 0;
735 u_int8_t *data;
736
737 PAGE(sc, 0);
738 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RSR);
739
740 pktlen =
741 bus_space_read_2(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RBC0) &
742 RBC_COUNT_MASK;
743 if (pktlen == 0) {
744 /*
745 * XXX At least one CE2 sets RBC0 == 0 occasionally, and only
746 * when MPE is set. It is not known why.
747 */
748 return (0);
749 }
750 recvcount += pktlen;
751
752 MGETHDR(m, M_DONTWAIT, MT_DATA);
753 if (m == NULL)
754 return (recvcount);
755 m->m_pkthdr.len = pktlen;
756 len = MHLEN;
757 top = 0;
758 mp = ⊤
759
760 while (pktlen > 0) {
761 if (top) {
762 MGET(m, M_DONTWAIT, MT_DATA);
763 if (m == NULL) {
764 m_freem(top);
765 return (recvcount);
766 }
767 len = MLEN;
768 }
769 if (pktlen >= MINCLSIZE) {
770 MCLGET(m, M_DONTWAIT);
771 if (!(m->m_flags & M_EXT)) {
772 m_freem(m);
773 m_freem(top);
774 return (recvcount);
775 }
776 len = MCLBYTES;
777 }
778 if (!top) {
779 caddr_t newdata = (caddr_t)ALIGN(m->m_data +
780 sizeof (struct ether_header)) -
781 sizeof (struct ether_header);
782 len -= newdata - m->m_data;
783 m->m_data = newdata;
784 }
785 len = min(pktlen, len);
786
787 data = mtod(m, u_int8_t *);
788 if (len > 1) {
789 len &= ~1;
790 bus_space_read_raw_multi_2(sc->sc_bst, sc->sc_bsh,
791 sc->sc_offset + EDP, data, len);
792 } else
793 *data = bus_space_read_1(sc->sc_bst, sc->sc_bsh,
794 sc->sc_offset + EDP);
795 m->m_len = len;
796 pktlen -= len;
797 *mp = m;
798 mp = &m->m_next;
799 }
800
801 /* Skip Rx packet. */
802 bus_space_write_2(sc->sc_bst, sc->sc_bsh, sc->sc_offset + DO0,
803 DO_SKIP_RX_PKT);
804
805 ml_enqueue(&ml, top);
806 if_input(ifp, &ml);
807
808 return (recvcount);
809 }
810
811
812 /*
813 * Serial management for the MII.
814 * The DELAY's below stem from the fact that the maximum frequency
815 * acceptable on the MDC pin is 2.5 MHz and fast processors can easily
816 * go much faster than that.
817 */
818
819 /* Let the MII serial management be idle for one period. */
820 static INLINE void xe_mdi_idle(struct xe_softc *);
821 static INLINE void
xe_mdi_idle(struct xe_softc * sc)822 xe_mdi_idle(struct xe_softc *sc)
823 {
824 bus_space_tag_t bst = sc->sc_bst;
825 bus_space_handle_t bsh = sc->sc_bsh;
826 bus_size_t offset = sc->sc_offset;
827
828 /* Drive MDC low... */
829 bus_space_write_1(bst, bsh, offset + GP2, MDC_LOW);
830 DELAY(1);
831
832 /* and high again. */
833 bus_space_write_1(bst, bsh, offset + GP2, MDC_HIGH);
834 DELAY(1);
835 }
836
837 /* Pulse out one bit of data. */
838 static INLINE void xe_mdi_pulse(struct xe_softc *, int);
839 static INLINE void
xe_mdi_pulse(struct xe_softc * sc,int data)840 xe_mdi_pulse(struct xe_softc *sc, int data)
841 {
842 bus_space_tag_t bst = sc->sc_bst;
843 bus_space_handle_t bsh = sc->sc_bsh;
844 bus_size_t offset = sc->sc_offset;
845 u_int8_t bit = data ? MDIO_HIGH : MDIO_LOW;
846
847 /* First latch the data bit MDIO with clock bit MDC low...*/
848 bus_space_write_1(bst, bsh, offset + GP2, bit | MDC_LOW);
849 DELAY(1);
850
851 /* then raise the clock again, preserving the data bit. */
852 bus_space_write_1(bst, bsh, offset + GP2, bit | MDC_HIGH);
853 DELAY(1);
854 }
855
856 /* Probe one bit of data. */
857 static INLINE int xe_mdi_probe(struct xe_softc *sc);
858 static INLINE int
xe_mdi_probe(struct xe_softc * sc)859 xe_mdi_probe(struct xe_softc *sc)
860 {
861 bus_space_tag_t bst = sc->sc_bst;
862 bus_space_handle_t bsh = sc->sc_bsh;
863 bus_size_t offset = sc->sc_offset;
864 u_int8_t x;
865
866 /* Pull clock bit MDCK low... */
867 bus_space_write_1(bst, bsh, offset + GP2, MDC_LOW);
868 DELAY(1);
869
870 /* Read data and drive clock high again. */
871 x = bus_space_read_1(bst, bsh, offset + GP2) & MDIO;
872 bus_space_write_1(bst, bsh, offset + GP2, MDC_HIGH);
873 DELAY(1);
874
875 return (x);
876 }
877
878 /* Pulse out a sequence of data bits. */
879 static INLINE void xe_mdi_pulse_bits(struct xe_softc *, u_int32_t, int);
880 static INLINE void
xe_mdi_pulse_bits(struct xe_softc * sc,u_int32_t data,int len)881 xe_mdi_pulse_bits(struct xe_softc *sc, u_int32_t data, int len)
882 {
883 u_int32_t mask;
884
885 for (mask = 1 << (len - 1); mask; mask >>= 1)
886 xe_mdi_pulse(sc, data & mask);
887 }
888
889 /* Read a PHY register. */
890 int
xe_mdi_read(struct device * self,int phy,int reg)891 xe_mdi_read(struct device *self, int phy, int reg)
892 {
893 struct xe_softc *sc = (struct xe_softc *)self;
894 int i;
895 u_int32_t mask;
896 u_int32_t data = 0;
897
898 PAGE(sc, 2);
899 for (i = 0; i < 32; i++) /* Synchronize. */
900 xe_mdi_pulse(sc, 1);
901 xe_mdi_pulse_bits(sc, 0x06, 4); /* Start + Read opcode */
902 xe_mdi_pulse_bits(sc, phy, 5); /* PHY address */
903 xe_mdi_pulse_bits(sc, reg, 5); /* PHY register */
904 xe_mdi_idle(sc); /* Turn around. */
905 xe_mdi_probe(sc); /* Drop initial zero bit. */
906
907 for (mask = 1 << 15; mask; mask >>= 1)
908 if (xe_mdi_probe(sc))
909 data |= mask;
910 xe_mdi_idle(sc);
911
912 DPRINTF(XED_MII,
913 ("xe_mdi_read: phy %d reg %d -> %x\n", phy, reg, data));
914 return (data);
915 }
916
917 /* Write a PHY register. */
918 void
xe_mdi_write(struct device * self,int phy,int reg,int value)919 xe_mdi_write(struct device *self, int phy, int reg, int value)
920 {
921 struct xe_softc *sc = (struct xe_softc *)self;
922 int i;
923
924 PAGE(sc, 2);
925 for (i = 0; i < 32; i++) /* Synchronize. */
926 xe_mdi_pulse(sc, 1);
927 xe_mdi_pulse_bits(sc, 0x05, 4); /* Start + Write opcode */
928 xe_mdi_pulse_bits(sc, phy, 5); /* PHY address */
929 xe_mdi_pulse_bits(sc, reg, 5); /* PHY register */
930 xe_mdi_pulse_bits(sc, 0x02, 2); /* Turn around. */
931 xe_mdi_pulse_bits(sc, value, 16); /* Write the data */
932 xe_mdi_idle(sc); /* Idle away. */
933
934 DPRINTF(XED_MII,
935 ("xe_mdi_write: phy %d reg %d val %x\n", phy, reg, value));
936 }
937
938 void
xe_statchg(struct device * self)939 xe_statchg(struct device *self)
940 {
941 }
942
943 /*
944 * Change media according to request.
945 */
946 int
xe_mediachange(struct ifnet * ifp)947 xe_mediachange(struct ifnet *ifp)
948 {
949 if (ifp->if_flags & IFF_UP)
950 xe_init(ifp->if_softc);
951 return (0);
952 }
953
954 /*
955 * Notify the world which media we're using.
956 */
957 void
xe_mediastatus(struct ifnet * ifp,struct ifmediareq * ifmr)958 xe_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
959 {
960 struct xe_softc *sc = ifp->if_softc;
961
962 mii_pollstat(&sc->sc_mii);
963 ifmr->ifm_status = sc->sc_mii.mii_media_status;
964 ifmr->ifm_active = sc->sc_mii.mii_media_active;
965 }
966
967 void
xe_reset(struct xe_softc * sc)968 xe_reset(struct xe_softc *sc)
969 {
970 int s;
971
972 s = splnet();
973 xe_stop(sc);
974 xe_full_reset(sc);
975 xe_init(sc);
976 splx(s);
977 }
978
979 void
xe_watchdog(struct ifnet * ifp)980 xe_watchdog(struct ifnet *ifp)
981 {
982 struct xe_softc *sc = ifp->if_softc;
983
984 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname);
985 ++sc->sc_arpcom.ac_if.if_oerrors;
986
987 xe_reset(sc);
988 }
989
990 void
xe_stop(struct xe_softc * sc)991 xe_stop(struct xe_softc *sc)
992 {
993 /* Disable interrupts. */
994 PAGE(sc, 0);
995 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 0);
996
997 PAGE(sc, 1);
998 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + IMR0, 0);
999
1000 /* Power down, wait. */
1001 PAGE(sc, 4);
1002 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + GP1, 0);
1003 DELAY(40000);
1004
1005 /* Cancel watchdog timer. */
1006 sc->sc_arpcom.ac_if.if_timer = 0;
1007 }
1008
1009 void
xe_init(struct xe_softc * sc)1010 xe_init(struct xe_softc *sc)
1011 {
1012 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1013 int s;
1014
1015 DPRINTF(XED_CONFIG, ("xe_init\n"));
1016
1017 s = splnet();
1018
1019 xe_set_address(sc);
1020
1021 /* Set current media. */
1022 mii_mediachg(&sc->sc_mii);
1023
1024 ifp->if_flags |= IFF_RUNNING;
1025 ifq_clr_oactive(&ifp->if_snd);
1026 splx(s);
1027 }
1028
1029 /*
1030 * Start outputting on the interface.
1031 * Always called as splnet().
1032 */
1033 void
xe_start(struct ifnet * ifp)1034 xe_start(struct ifnet *ifp)
1035 {
1036 struct xe_softc *sc = ifp->if_softc;
1037 bus_space_tag_t bst = sc->sc_bst;
1038 bus_space_handle_t bsh = sc->sc_bsh;
1039 bus_size_t offset = sc->sc_offset;
1040 unsigned int s, len, pad = 0;
1041 struct mbuf *m0, *m;
1042 u_int16_t space;
1043
1044 /* Don't transmit if interface is busy or not running. */
1045 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd))
1046 return;
1047
1048 /* Peek at the next packet. */
1049 m0 = ifq_deq_begin(&ifp->if_snd);
1050 if (m0 == NULL)
1051 return;
1052
1053 /* We need to use m->m_pkthdr.len, so require the header. */
1054 if (!(m0->m_flags & M_PKTHDR))
1055 panic("xe_start: no header mbuf");
1056
1057 len = m0->m_pkthdr.len;
1058
1059 /* Pad to ETHER_MIN_LEN - ETHER_CRC_LEN. */
1060 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
1061 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
1062
1063 PAGE(sc, 0);
1064 space = bus_space_read_2(bst, bsh, offset + TSO0) & 0x7fff;
1065 if (len + pad + 2 > space) {
1066 ifq_deq_rollback(&ifp->if_snd, m0);
1067 DPRINTF(XED_FIFO,
1068 ("%s: not enough space in output FIFO (%d > %d)\n",
1069 sc->sc_dev.dv_xname, len + pad + 2, space));
1070 return;
1071 }
1072
1073 ifq_deq_commit(&ifp->if_snd, m0);
1074
1075 #if NBPFILTER > 0
1076 if (ifp->if_bpf)
1077 bpf_mtap(ifp->if_bpf, m0, BPF_DIRECTION_OUT);
1078 #endif
1079
1080 /*
1081 * Do the output at splhigh() so that an interrupt from another device
1082 * won't cause a FIFO underrun.
1083 */
1084 s = splhigh();
1085
1086 bus_space_write_2(bst, bsh, offset + TSO2, (u_int16_t)len + pad + 2);
1087 bus_space_write_2(bst, bsh, offset + EDP, (u_int16_t)len + pad);
1088 for (m = m0; m; ) {
1089 if (m->m_len > 1)
1090 bus_space_write_raw_multi_2(bst, bsh, offset + EDP,
1091 mtod(m, u_int8_t *), m->m_len & ~1);
1092 if (m->m_len & 1)
1093 bus_space_write_1(bst, bsh, offset + EDP,
1094 *(mtod(m, u_int8_t *) + m->m_len - 1));
1095 m0 = m_free(m);
1096 m = m0;
1097 }
1098 if (sc->sc_flags & XEF_MOHAWK)
1099 bus_space_write_1(bst, bsh, offset + CR, TX_PKT | ENABLE_INT);
1100 else {
1101 for (; pad > 1; pad -= 2)
1102 bus_space_write_2(bst, bsh, offset + EDP, 0);
1103 if (pad == 1)
1104 bus_space_write_1(bst, bsh, offset + EDP, 0);
1105 }
1106
1107 splx(s);
1108
1109 ifp->if_timer = 5;
1110 }
1111
1112 int
xe_ioctl(struct ifnet * ifp,u_long command,caddr_t data)1113 xe_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1114 {
1115 struct xe_softc *sc = ifp->if_softc;
1116 struct ifreq *ifr = (struct ifreq *)data;
1117 int s, error = 0;
1118
1119 s = splnet();
1120
1121 switch (command) {
1122 case SIOCSIFADDR:
1123 ifp->if_flags |= IFF_UP;
1124 xe_init(sc);
1125 break;
1126
1127 case SIOCSIFFLAGS:
1128 sc->sc_all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0;
1129
1130 PAGE(sc, 0x42);
1131 if ((ifp->if_flags & IFF_PROMISC) ||
1132 (ifp->if_flags & IFF_ALLMULTI))
1133 bus_space_write_1(sc->sc_bst, sc->sc_bsh,
1134 sc->sc_offset + SWC1,
1135 SWC1_PROMISC | SWC1_MCAST_PROM);
1136 else
1137 bus_space_write_1(sc->sc_bst, sc->sc_bsh,
1138 sc->sc_offset + SWC1, 0);
1139
1140 /*
1141 * If interface is marked up and not running, then start it.
1142 * If it is marked down and running, stop it.
1143 * XXX If it's up then re-initialize it. This is so flags
1144 * such as IFF_PROMISC are handled.
1145 */
1146 if (ifp->if_flags & IFF_UP) {
1147 xe_init(sc);
1148 } else {
1149 if (ifp->if_flags & IFF_RUNNING)
1150 xe_stop(sc);
1151 }
1152 break;
1153
1154 case SIOCADDMULTI:
1155 case SIOCDELMULTI:
1156 sc->sc_all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0;
1157 error = (command == SIOCADDMULTI) ?
1158 ether_addmulti(ifr, &sc->sc_arpcom) :
1159 ether_delmulti(ifr, &sc->sc_arpcom);
1160
1161 if (error == ENETRESET) {
1162 /*
1163 * Multicast list has changed; set the hardware
1164 * filter accordingly.
1165 */
1166 if (!sc->sc_all_mcasts &&
1167 !(ifp->if_flags & IFF_PROMISC))
1168 xe_set_address(sc);
1169
1170 /*
1171 * xe_set_address() can turn on all_mcasts if we run
1172 * out of space, so check it again rather than else {}.
1173 */
1174 if (sc->sc_all_mcasts)
1175 xe_init(sc);
1176 error = 0;
1177 }
1178 break;
1179
1180 case SIOCSIFMEDIA:
1181 case SIOCGIFMEDIA:
1182 error =
1183 ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command);
1184 break;
1185
1186 default:
1187 error = ENOTTY;
1188 }
1189
1190 splx(s);
1191 return (error);
1192 }
1193
1194 void
xe_set_address(struct xe_softc * sc)1195 xe_set_address(struct xe_softc *sc)
1196 {
1197 bus_space_tag_t bst = sc->sc_bst;
1198 bus_space_handle_t bsh = sc->sc_bsh;
1199 bus_size_t offset = sc->sc_offset;
1200 struct arpcom *arp = &sc->sc_arpcom;
1201 struct ether_multi *enm;
1202 struct ether_multistep step;
1203 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1204 int i, page, pos, num;
1205
1206 PAGE(sc, 0x50);
1207 for (i = 0; i < 6; i++) {
1208 bus_space_write_1(bst, bsh, offset + IA + i,
1209 sc->sc_arpcom.ac_enaddr[(sc->sc_flags & XEF_MOHAWK) ?
1210 5 - i : i]);
1211 }
1212
1213 if (arp->ac_multirangecnt > 0) {
1214 ifp->if_flags |= IFF_ALLMULTI;
1215 sc->sc_all_mcasts=1;
1216 } else if (arp->ac_multicnt > 0) {
1217 if (arp->ac_multicnt > 9) {
1218 PAGE(sc, 0x42);
1219 bus_space_write_1(sc->sc_bst, sc->sc_bsh,
1220 sc->sc_offset + SWC1,
1221 SWC1_PROMISC | SWC1_MCAST_PROM);
1222 return;
1223 }
1224
1225 ETHER_FIRST_MULTI(step, arp, enm);
1226
1227 pos = IA + 6;
1228 for (page = 0x50, num = arp->ac_multicnt; num > 0 && enm;
1229 num--) {
1230 for (i = 0; i < 6; i++) {
1231 bus_space_write_1(bst, bsh, offset + pos,
1232 enm->enm_addrlo[
1233 (sc->sc_flags & XEF_MOHAWK) ? 5 - i : i]);
1234
1235 if (++pos > 15) {
1236 pos = IA;
1237 page++;
1238 PAGE(sc, page);
1239 }
1240 }
1241 }
1242 }
1243 }
1244
1245 void
xe_cycle_power(struct xe_softc * sc)1246 xe_cycle_power(struct xe_softc *sc)
1247 {
1248 bus_space_tag_t bst = sc->sc_bst;
1249 bus_space_handle_t bsh = sc->sc_bsh;
1250 bus_size_t offset = sc->sc_offset;
1251
1252 PAGE(sc, 4);
1253 DELAY(1);
1254 bus_space_write_1(bst, bsh, offset + GP1, 0);
1255 DELAY(40000);
1256 if (sc->sc_flags & XEF_MOHAWK)
1257 bus_space_write_1(bst, bsh, offset + GP1, POWER_UP);
1258 else
1259 /* XXX What is bit 2 (aka AIC)? */
1260 bus_space_write_1(bst, bsh, offset + GP1, POWER_UP | 4);
1261 DELAY(20000);
1262 }
1263
1264 void
xe_full_reset(struct xe_softc * sc)1265 xe_full_reset(struct xe_softc *sc)
1266 {
1267 bus_space_tag_t bst = sc->sc_bst;
1268 bus_space_handle_t bsh = sc->sc_bsh;
1269 bus_size_t offset = sc->sc_offset;
1270
1271 /* Do an as extensive reset as possible on all functions. */
1272 xe_cycle_power(sc);
1273 bus_space_write_1(bst, bsh, offset + CR, SOFT_RESET);
1274 DELAY(20000);
1275 bus_space_write_1(bst, bsh, offset + CR, 0);
1276 DELAY(20000);
1277 if (sc->sc_flags & XEF_MOHAWK) {
1278 PAGE(sc, 4);
1279 /*
1280 * Drive GP1 low to power up ML6692 and GP2 high to power up
1281 * the 10MHz chip. XXX What chip is that? The phy?
1282 */
1283 bus_space_write_1(bst, bsh, offset + GP0,
1284 GP1_OUT | GP2_OUT | GP2_WR);
1285 }
1286 DELAY(500000);
1287
1288 /* Get revision information. XXX Symbolic constants. */
1289 sc->sc_rev = bus_space_read_1(bst, bsh, offset + BV) &
1290 ((sc->sc_flags & XEF_MOHAWK) ? 0x70 : 0x30) >> 4;
1291
1292 /* Media selection. XXX Maybe manual overriding too? */
1293 if (!(sc->sc_flags & XEF_MOHAWK)) {
1294 PAGE(sc, 4);
1295 /*
1296 * XXX I have no idea what this really does, it is from the
1297 * Linux driver.
1298 */
1299 bus_space_write_1(bst, bsh, offset + GP0, GP1_OUT);
1300 }
1301 DELAY(40000);
1302
1303 /* Setup the ethernet interrupt mask. */
1304 PAGE(sc, 1);
1305 bus_space_write_1(bst, bsh, offset + IMR0,
1306 ISR_TX_OFLOW | ISR_PKT_TX | ISR_MAC_INT | /* ISR_RX_EARLY | */
1307 ISR_RX_FULL | ISR_RX_PKT_REJ | ISR_FORCED_INT);
1308 #if 0
1309 bus_space_write_1(bst, bsh, offset + IMR0, 0xff);
1310 #endif
1311 if (!(sc->sc_flags & XEF_DINGO))
1312 /* XXX What is this? Not for Dingo at least. */
1313 bus_space_write_1(bst, bsh, offset + IMR1, 1);
1314
1315 /*
1316 * Disable source insertion.
1317 * XXX Dingo does not have this bit, but Linux does it unconditionally.
1318 */
1319 if (!(sc->sc_flags & XEF_DINGO)) {
1320 PAGE(sc, 0x42);
1321 bus_space_write_1(bst, bsh, offset + SWC0, 0x20);
1322 }
1323
1324 /* Set the local memory dividing line. */
1325 if (sc->sc_rev != 1) {
1326 PAGE(sc, 2);
1327 /* XXX Symbolic constant preferable. */
1328 bus_space_write_2(bst, bsh, offset + RBS0, 0x2000);
1329 }
1330
1331 xe_set_address(sc);
1332
1333 /*
1334 * Apparently the receive byte pointer can be bad after a reset, so
1335 * we hardwire it correctly.
1336 */
1337 PAGE(sc, 0);
1338 bus_space_write_2(bst, bsh, offset + DO0, DO_CHG_OFFSET);
1339
1340 /* Setup ethernet MAC registers. XXX Symbolic constants. */
1341 PAGE(sc, 0x40);
1342 bus_space_write_1(bst, bsh, offset + RX0MSK,
1343 PKT_TOO_LONG | CRC_ERR | RX_OVERRUN | RX_ABORT | RX_OK);
1344 bus_space_write_1(bst, bsh, offset + TX0MSK,
1345 CARRIER_LOST | EXCESSIVE_COLL | TX_UNDERRUN | LATE_COLLISION |
1346 SQE | TX_ABORT | TX_OK);
1347 if (!(sc->sc_flags & XEF_DINGO))
1348 /* XXX From Linux, dunno what 0xb0 means. */
1349 bus_space_write_1(bst, bsh, offset + TX1MSK, 0xb0);
1350 bus_space_write_1(bst, bsh, offset + RXST0, 0);
1351 bus_space_write_1(bst, bsh, offset + TXST0, 0);
1352 bus_space_write_1(bst, bsh, offset + TXST1, 0);
1353
1354 /* Enable MII function if available. */
1355 if (LIST_FIRST(&sc->sc_mii.mii_phys)) {
1356 PAGE(sc, 2);
1357 bus_space_write_1(bst, bsh, offset + MSR,
1358 bus_space_read_1(bst, bsh, offset + MSR) | SELECT_MII);
1359 DELAY(20000);
1360 } else {
1361 PAGE(sc, 0);
1362
1363 /* XXX Do we need to do this? */
1364 PAGE(sc, 0x42);
1365 bus_space_write_1(bst, bsh, offset + SWC1, SWC1_AUTO_MEDIA);
1366 DELAY(50000);
1367
1368 /* XXX Linux probes the media here. */
1369 }
1370
1371 /* Configure the LED registers. */
1372 PAGE(sc, 2);
1373
1374 /* XXX This is not good for 10base2. */
1375 bus_space_write_1(bst, bsh, offset + LED,
1376 LED_TX_ACT << LED1_SHIFT | LED_10MB_LINK << LED0_SHIFT);
1377 if (sc->sc_flags & XEF_DINGO)
1378 bus_space_write_1(bst, bsh, offset + LED3,
1379 LED_100MB_LINK << LED3_SHIFT);
1380
1381 /* Enable receiver and go online. */
1382 PAGE(sc, 0x40);
1383 bus_space_write_1(bst, bsh, offset + CMD0, ENABLE_RX | ONLINE);
1384
1385 #if 0
1386 /* XXX Linux does this here - is it necessary? */
1387 PAGE(sc, 1);
1388 bus_space_write_1(bst, bsh, offset + IMR0, 0xff);
1389 if (!(sc->sc_flags & XEF_DINGO))
1390 /* XXX What is this? Not for Dingo at least. */
1391 bus_space_write_1(bst, bsh, offset + IMR1, 1);
1392 #endif
1393
1394 /* Enable interrupts. */
1395 PAGE(sc, 0);
1396 bus_space_write_1(bst, bsh, offset + CR, ENABLE_INT);
1397
1398 /* XXX This is pure magic for me, found in the Linux driver. */
1399 if ((sc->sc_flags & (XEF_DINGO | XEF_MODEM)) == XEF_MODEM) {
1400 if ((bus_space_read_1(bst, bsh, offset + 0x10) & 0x01) == 0)
1401 /* Unmask the master interrupt bit. */
1402 bus_space_write_1(bst, bsh, offset + 0x10, 0x11);
1403 }
1404
1405 /*
1406 * The Linux driver says this:
1407 * We should switch back to page 0 to avoid a bug in revision 0
1408 * where regs with offset below 8 can't be read after an access
1409 * to the MAC registers.
1410 */
1411 PAGE(sc, 0);
1412 }
1413
1414 #ifdef XEDEBUG
1415 void
xe_reg_dump(struct xe_softc * sc)1416 xe_reg_dump(struct xe_softc *sc)
1417 {
1418 int page, i;
1419 bus_space_tag_t bst = sc->sc_bst;
1420 bus_space_handle_t bsh = sc->sc_bsh;
1421 bus_size_t offset = sc->sc_offset;
1422
1423 printf("%x: Common registers: ", sc->sc_dev.dv_xname);
1424 for (i = 0; i < 8; i++) {
1425 printf(" %2.2x", bus_space_read_1(bst, bsh, offset + i));
1426 }
1427 printf("\n");
1428
1429 for (page = 0; page < 8; page++) {
1430 printf("%s: Register page %2.2x: ", sc->sc_dev.dv_xname, page);
1431 PAGE(sc, page);
1432 for (i = 8; i < 16; i++) {
1433 printf(" %2.2x",
1434 bus_space_read_1(bst, bsh, offset + i));
1435 }
1436 printf("\n");
1437 }
1438
1439 for (page = 0x40; page < 0x5f; page++) {
1440 if (page == 0x43 || (page >= 0x46 && page <= 0x4f) ||
1441 (page >= 0x51 && page <= 0x5e))
1442 continue;
1443 printf("%s: Register page %2.2x: ", sc->sc_dev.dv_xname, page);
1444 PAGE(sc, page);
1445 for (i = 8; i < 16; i++) {
1446 printf(" %2.2x",
1447 bus_space_read_1(bst, bsh, offset + i));
1448 }
1449 printf("\n");
1450 }
1451 }
1452 #endif /* XEDEBUG */
1453