1 /*
2 * AMD 10Gb Ethernet driver
3 *
4 * Copyright (c) 2020 Advanced Micro Devices, Inc.
5 *
6 * This file is available to you under your choice of the following two
7 * licenses:
8 *
9 * License 1: GPLv2
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
59 * Redistribution and use in source and binary forms, with or without
60 * modification, are permitted provided that the following conditions are met:
61 * * Redistributions of source code must retain the above copyright
62 * notice, this list of conditions and the following disclaimer.
63 * * Redistributions in binary form must reproduce the above copyright
64 * notice, this list of conditions and the following disclaimer in the
65 * documentation and/or other materials provided with the distribution.
66 * * Neither the name of Advanced Micro Devices, Inc. nor the
67 * names of its contributors may be used to endorse or promote products
68 * derived from this software without specific prior written permission.
69 *
70 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
71 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
72 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
73 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
74 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
75 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
76 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
77 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
78 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
79 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
80 *
81 * This file incorporates work covered by the following copyright and
82 * permission notice:
83 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
84 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
85 * Inc. unless otherwise expressly agreed to in writing between Synopsys
86 * and you.
87 *
88 * The Software IS NOT an item of Licensed Software or Licensed Product
89 * under any End User Software License Agreement or Agreement for Licensed
90 * Product with Synopsys or any supplement thereto. Permission is hereby
91 * granted, free of charge, to any person obtaining a copy of this software
92 * annotated with this license and the Software, to deal in the Software
93 * without restriction, including without limitation the rights to use,
94 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
95 * of the Software, and to permit persons to whom the Software is furnished
96 * to do so, subject to the following conditions:
97 *
98 * The above copyright notice and this permission notice shall be included
99 * in all copies or substantial portions of the Software.
100 *
101 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
102 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
103 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
104 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
105 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
106 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
107 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
108 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
109 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
110 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
111 * THE POSSIBILITY OF SUCH DAMAGE.
112 */
113
114 #include <sys/cdefs.h>
115 #include "xgbe.h"
116 #include "xgbe-common.h"
117
118 #define XGBE_ABORT_COUNT 500
119 #define XGBE_DISABLE_COUNT 1000
120
121 #define XGBE_STD_SPEED 1
122
123 #define XGBE_INTR_RX_FULL BIT(IC_RAW_INTR_STAT_RX_FULL_INDEX)
124 #define XGBE_INTR_TX_EMPTY BIT(IC_RAW_INTR_STAT_TX_EMPTY_INDEX)
125 #define XGBE_INTR_TX_ABRT BIT(IC_RAW_INTR_STAT_TX_ABRT_INDEX)
126 #define XGBE_INTR_STOP_DET BIT(IC_RAW_INTR_STAT_STOP_DET_INDEX)
127 #define XGBE_DEFAULT_INT_MASK (XGBE_INTR_RX_FULL | \
128 XGBE_INTR_TX_EMPTY | \
129 XGBE_INTR_TX_ABRT | \
130 XGBE_INTR_STOP_DET)
131
132 #define XGBE_I2C_READ BIT(8)
133 #define XGBE_I2C_STOP BIT(9)
134
135 static int
xgbe_i2c_abort(struct xgbe_prv_data * pdata)136 xgbe_i2c_abort(struct xgbe_prv_data *pdata)
137 {
138 unsigned int wait = XGBE_ABORT_COUNT;
139
140 /* Must be enabled to recognize the abort request */
141 XI2C_IOWRITE_BITS(pdata, IC_ENABLE, EN, 1);
142
143 /* Issue the abort */
144 XI2C_IOWRITE_BITS(pdata, IC_ENABLE, ABORT, 1);
145
146 while (wait--) {
147 if (!XI2C_IOREAD_BITS(pdata, IC_ENABLE, ABORT))
148 return (0);
149
150 DELAY(500);
151 }
152
153 return (-EBUSY);
154 }
155
156 static int
xgbe_i2c_set_enable(struct xgbe_prv_data * pdata,bool enable)157 xgbe_i2c_set_enable(struct xgbe_prv_data *pdata, bool enable)
158 {
159 unsigned int wait = XGBE_DISABLE_COUNT;
160 unsigned int mode = enable ? 1 : 0;
161
162 while (wait--) {
163 XI2C_IOWRITE_BITS(pdata, IC_ENABLE, EN, mode);
164 if (XI2C_IOREAD_BITS(pdata, IC_ENABLE_STATUS, EN) == mode)
165 return (0);
166
167 DELAY(100);
168 }
169
170 return (-EBUSY);
171 }
172
173 static int
xgbe_i2c_disable(struct xgbe_prv_data * pdata)174 xgbe_i2c_disable(struct xgbe_prv_data *pdata)
175 {
176 unsigned int ret;
177
178 ret = xgbe_i2c_set_enable(pdata, false);
179 if (ret) {
180 /* Disable failed, try an abort */
181 ret = xgbe_i2c_abort(pdata);
182 if (ret) {
183 axgbe_error("%s: i2c_abort %d\n", __func__, ret);
184 return (ret);
185 }
186
187 /* Abort succeeded, try to disable again */
188 ret = xgbe_i2c_set_enable(pdata, false);
189 }
190
191 axgbe_printf(3, "%s: final i2c_disable %d\n", __func__, ret);
192 return (ret);
193 }
194
195 static int
xgbe_i2c_enable(struct xgbe_prv_data * pdata)196 xgbe_i2c_enable(struct xgbe_prv_data *pdata)
197 {
198 return (xgbe_i2c_set_enable(pdata, true));
199 }
200
201 static void
xgbe_i2c_clear_all_interrupts(struct xgbe_prv_data * pdata)202 xgbe_i2c_clear_all_interrupts(struct xgbe_prv_data *pdata)
203 {
204 XI2C_IOREAD(pdata, IC_CLR_INTR);
205 }
206
207 static void
xgbe_i2c_disable_interrupts(struct xgbe_prv_data * pdata)208 xgbe_i2c_disable_interrupts(struct xgbe_prv_data *pdata)
209 {
210 XI2C_IOWRITE(pdata, IC_INTR_MASK, 0);
211 }
212
213 static void
xgbe_i2c_enable_interrupts(struct xgbe_prv_data * pdata)214 xgbe_i2c_enable_interrupts(struct xgbe_prv_data *pdata)
215 {
216 XI2C_IOWRITE(pdata, IC_INTR_MASK, XGBE_DEFAULT_INT_MASK);
217 }
218
219 static void
xgbe_i2c_write(struct xgbe_prv_data * pdata)220 xgbe_i2c_write(struct xgbe_prv_data *pdata)
221 {
222 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
223 unsigned int tx_slots, cmd;
224
225 /* Configured to never receive Rx overflows, so fill up Tx fifo */
226 tx_slots = pdata->i2c.tx_fifo_size - XI2C_IOREAD(pdata, IC_TXFLR);
227 axgbe_printf(3, "%s: tx_slots %d tx_len %d\n", __func__, tx_slots,
228 state->tx_len);
229
230 while (tx_slots && state->tx_len) {
231 if (state->op->cmd == XGBE_I2C_CMD_READ)
232 cmd = XGBE_I2C_READ;
233 else
234 cmd = *state->tx_buf++;
235
236 axgbe_printf(3, "%s: cmd %d tx_len %d\n", __func__, cmd,
237 state->tx_len);
238
239 if (state->tx_len == 1)
240 XI2C_SET_BITS(cmd, IC_DATA_CMD, STOP, 1);
241
242 XI2C_IOWRITE(pdata, IC_DATA_CMD, cmd);
243
244 tx_slots--;
245 state->tx_len--;
246 }
247
248 /* No more Tx operations, so ignore TX_EMPTY and return */
249 if (!state->tx_len)
250 XI2C_IOWRITE_BITS(pdata, IC_INTR_MASK, TX_EMPTY, 0);
251 }
252
253 static void
xgbe_i2c_read(struct xgbe_prv_data * pdata)254 xgbe_i2c_read(struct xgbe_prv_data *pdata)
255 {
256 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
257 unsigned int rx_slots;
258
259 /* Anything to be read? */
260 axgbe_printf(3, "%s: op cmd %d\n", __func__, state->op->cmd);
261 if (state->op->cmd != XGBE_I2C_CMD_READ)
262 return;
263
264 rx_slots = XI2C_IOREAD(pdata, IC_RXFLR);
265 axgbe_printf(3, "%s: rx_slots %d rx_len %d\n", __func__, rx_slots,
266 state->rx_len);
267
268 while (rx_slots && state->rx_len) {
269 *state->rx_buf++ = XI2C_IOREAD(pdata, IC_DATA_CMD);
270 state->rx_len--;
271 rx_slots--;
272 }
273 }
274
275 static void
xgbe_i2c_clear_isr_interrupts(struct xgbe_prv_data * pdata,unsigned int isr)276 xgbe_i2c_clear_isr_interrupts(struct xgbe_prv_data *pdata, unsigned int isr)
277 {
278 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
279
280 if (isr & XGBE_INTR_TX_ABRT) {
281 state->tx_abort_source = XI2C_IOREAD(pdata, IC_TX_ABRT_SOURCE);
282 XI2C_IOREAD(pdata, IC_CLR_TX_ABRT);
283 }
284
285 if (isr & XGBE_INTR_STOP_DET)
286 XI2C_IOREAD(pdata, IC_CLR_STOP_DET);
287 }
288
289 static void
xgbe_i2c_isr(void * data)290 xgbe_i2c_isr(void *data)
291 {
292 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
293 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
294 unsigned int isr;
295
296 isr = XI2C_IOREAD(pdata, IC_RAW_INTR_STAT);
297 axgbe_printf(3, "%s: isr 0x%x\n", __func__, isr);
298 if (!isr)
299 goto reissue_check;
300
301 axgbe_printf(3, "%s: I2C interrupt status=%#010x\n", __func__, isr);
302
303 xgbe_i2c_clear_isr_interrupts(pdata, isr);
304
305 if (isr & XGBE_INTR_TX_ABRT) {
306 axgbe_printf(1, "%s: I2C TX_ABRT received (%#010x) for target "
307 "%#04x\n", __func__, state->tx_abort_source,
308 state->op->target);
309
310 xgbe_i2c_disable_interrupts(pdata);
311
312 state->ret = -EIO;
313 goto out;
314 }
315
316 /* Check for data in the Rx fifo */
317 xgbe_i2c_read(pdata);
318
319 /* Fill up the Tx fifo next */
320 xgbe_i2c_write(pdata);
321
322 out:
323 /* Complete on an error or STOP condition */
324 axgbe_printf(3, "%s: ret %d stop %d\n", __func__, state->ret,
325 XI2C_GET_BITS(isr, IC_RAW_INTR_STAT, STOP_DET));
326
327 if (state->ret || XI2C_GET_BITS(isr, IC_RAW_INTR_STAT, STOP_DET))
328 pdata->i2c_complete = true;
329
330 reissue_check:
331 /* Reissue interrupt if status is not clear */
332 if (pdata->vdata->irq_reissue_support)
333 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 2);
334 }
335
336 static void
xgbe_i2c_set_mode(struct xgbe_prv_data * pdata)337 xgbe_i2c_set_mode(struct xgbe_prv_data *pdata)
338 {
339 unsigned int reg;
340
341 reg = XI2C_IOREAD(pdata, IC_CON);
342 XI2C_SET_BITS(reg, IC_CON, MASTER_MODE, 1);
343 XI2C_SET_BITS(reg, IC_CON, SLAVE_DISABLE, 1);
344 XI2C_SET_BITS(reg, IC_CON, RESTART_EN, 1);
345 XI2C_SET_BITS(reg, IC_CON, SPEED, XGBE_STD_SPEED);
346 XI2C_SET_BITS(reg, IC_CON, RX_FIFO_FULL_HOLD, 1);
347 XI2C_IOWRITE(pdata, IC_CON, reg);
348 }
349
350 static void
xgbe_i2c_get_features(struct xgbe_prv_data * pdata)351 xgbe_i2c_get_features(struct xgbe_prv_data *pdata)
352 {
353 struct xgbe_i2c *i2c = &pdata->i2c;
354 unsigned int reg;
355
356 reg = XI2C_IOREAD(pdata, IC_COMP_PARAM_1);
357 i2c->max_speed_mode = XI2C_GET_BITS(reg, IC_COMP_PARAM_1,
358 MAX_SPEED_MODE);
359 i2c->rx_fifo_size = XI2C_GET_BITS(reg, IC_COMP_PARAM_1,
360 RX_BUFFER_DEPTH);
361 i2c->tx_fifo_size = XI2C_GET_BITS(reg, IC_COMP_PARAM_1,
362 TX_BUFFER_DEPTH);
363
364 axgbe_printf(3, "%s: I2C features: %s=%u, %s=%u, %s=%u\n", __func__,
365 "MAX_SPEED_MODE", i2c->max_speed_mode,
366 "RX_BUFFER_DEPTH", i2c->rx_fifo_size,
367 "TX_BUFFER_DEPTH", i2c->tx_fifo_size);
368 }
369
370 static void
xgbe_i2c_set_target(struct xgbe_prv_data * pdata,unsigned int addr)371 xgbe_i2c_set_target(struct xgbe_prv_data *pdata, unsigned int addr)
372 {
373 XI2C_IOWRITE(pdata, IC_TAR, addr);
374 }
375
376 static void
xgbe_i2c_combined_isr(struct xgbe_prv_data * pdata)377 xgbe_i2c_combined_isr(struct xgbe_prv_data *pdata)
378 {
379 xgbe_i2c_isr(pdata);
380 }
381
382 static int
xgbe_i2c_xfer(struct xgbe_prv_data * pdata,struct xgbe_i2c_op * op)383 xgbe_i2c_xfer(struct xgbe_prv_data *pdata, struct xgbe_i2c_op *op)
384 {
385 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
386 unsigned long timeout;
387 int ret;
388
389 mtx_lock(&pdata->i2c_mutex);
390
391 axgbe_printf(3, "i2c xfer started ---->>>\n");
392
393 ret = xgbe_i2c_disable(pdata);
394 if (ret) {
395 axgbe_error("failed to disable i2c master\n");
396 goto out;
397 }
398
399 xgbe_i2c_set_target(pdata, op->target);
400
401 memset(state, 0, sizeof(*state));
402 state->op = op;
403 state->tx_len = op->len;
404 state->tx_buf = op->buf;
405 state->rx_len = op->len;
406 state->rx_buf = op->buf;
407
408 xgbe_i2c_clear_all_interrupts(pdata);
409 ret = xgbe_i2c_enable(pdata);
410 if (ret) {
411 axgbe_error("failed to enable i2c master\n");
412 goto out;
413 }
414
415 /* Enabling the interrupts will cause the TX FIFO empty interrupt to
416 * fire and begin to process the command via the ISR.
417 */
418 xgbe_i2c_enable_interrupts(pdata);
419
420 timeout = ticks + (20 * hz);
421 while (ticks < timeout) {
422
423 if (!pdata->i2c_complete) {
424 DELAY(200);
425 continue;
426 }
427
428 axgbe_printf(1, "%s: I2C OP complete\n", __func__);
429 break;
430 }
431
432 if ((ticks >= timeout) && !pdata->i2c_complete) {
433 axgbe_error("%s: operation timed out\n", __func__);
434 ret = -ETIMEDOUT;
435 goto disable;
436 }
437
438 ret = state->ret;
439 axgbe_printf(3, "%s: i2c xfer ret %d abrt_source 0x%x\n", __func__,
440 ret, state->tx_abort_source);
441 if (ret) {
442 axgbe_printf(1, "%s: i2c xfer ret %d abrt_source 0x%x\n", __func__,
443 ret, state->tx_abort_source);
444 if (state->tx_abort_source & IC_TX_ABRT_7B_ADDR_NOACK)
445 ret = -ENOTCONN;
446 else if (state->tx_abort_source & IC_TX_ABRT_ARB_LOST)
447 ret = -EAGAIN;
448 }
449
450 axgbe_printf(3, "i2c xfer finished ---->>>\n");
451
452 disable:
453 pdata->i2c_complete = false;
454 xgbe_i2c_disable_interrupts(pdata);
455 xgbe_i2c_disable(pdata);
456
457 out:
458 mtx_unlock(&pdata->i2c_mutex);
459 return (ret);
460 }
461
462 static void
xgbe_i2c_stop(struct xgbe_prv_data * pdata)463 xgbe_i2c_stop(struct xgbe_prv_data *pdata)
464 {
465 if (!pdata->i2c.started)
466 return;
467
468 axgbe_printf(3, "stopping I2C\n");
469
470 pdata->i2c.started = 0;
471
472 xgbe_i2c_disable_interrupts(pdata);
473 xgbe_i2c_disable(pdata);
474 xgbe_i2c_clear_all_interrupts(pdata);
475 }
476
477 static int
xgbe_i2c_start(struct xgbe_prv_data * pdata)478 xgbe_i2c_start(struct xgbe_prv_data *pdata)
479 {
480 if (pdata->i2c.started)
481 return (0);
482
483 pdata->i2c.started = 1;
484
485 return (0);
486 }
487
488 static int
xgbe_i2c_init(struct xgbe_prv_data * pdata)489 xgbe_i2c_init(struct xgbe_prv_data *pdata)
490 {
491 int ret;
492
493 /* initialize lock for i2c */
494 mtx_init(&pdata->i2c_mutex, "xgbe i2c mutex lock", NULL, MTX_DEF);
495 pdata->i2c_complete = false;
496
497 xgbe_i2c_disable_interrupts(pdata);
498
499 ret = xgbe_i2c_disable(pdata);
500 if (ret) {
501 axgbe_error("failed to disable i2c master\n");
502 return (ret);
503 }
504
505 xgbe_i2c_get_features(pdata);
506
507 xgbe_i2c_set_mode(pdata);
508
509 xgbe_i2c_clear_all_interrupts(pdata);
510
511 xgbe_dump_i2c_registers(pdata);
512
513 return (0);
514 }
515
516 void
xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if * i2c_if)517 xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *i2c_if)
518 {
519 i2c_if->i2c_init = xgbe_i2c_init;
520
521 i2c_if->i2c_start = xgbe_i2c_start;
522 i2c_if->i2c_stop = xgbe_i2c_stop;
523
524 i2c_if->i2c_xfer = xgbe_i2c_xfer;
525
526 i2c_if->i2c_isr = xgbe_i2c_combined_isr;
527 }
528