1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2010-2022 Hans Petter Selasky
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 #include <sys/stdint.h>
30 #include <sys/stddef.h>
31 #include <sys/param.h>
32 #include <sys/queue.h>
33 #include <sys/types.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/bus.h>
37 #include <sys/module.h>
38 #include <sys/lock.h>
39 #include <sys/mutex.h>
40 #include <sys/condvar.h>
41 #include <sys/sysctl.h>
42 #include <sys/sx.h>
43 #include <sys/unistd.h>
44 #include <sys/callout.h>
45 #include <sys/malloc.h>
46 #include <sys/priv.h>
47
48 #include <dev/usb/usb.h>
49 #include <dev/usb/usbdi.h>
50
51 #include <dev/usb/usb_core.h>
52 #include <dev/usb/usb_busdma.h>
53 #include <dev/usb/usb_process.h>
54 #include <dev/usb/usb_util.h>
55
56 #include <dev/usb/usb_controller.h>
57 #include <dev/usb/usb_bus.h>
58 #include <dev/usb/usb_pci.h>
59 #include <dev/usb/controller/xhci.h>
60 #include <dev/usb/controller/xhcireg.h>
61 #include "usb_if.h"
62
63 #define PCI_XHCI_VENDORID_AMD 0x1022
64 #define PCI_XHCI_VENDORID_INTEL 0x8086
65 #define PCI_XHCI_VENDORID_VMWARE 0x15ad
66 #define PCI_XHCI_VENDORID_ZHAOXIN 0x1d17
67
68 static device_probe_t xhci_pci_probe;
69 static device_detach_t xhci_pci_detach;
70 static usb_take_controller_t xhci_pci_take_controller;
71
72 static device_method_t xhci_device_methods[] = {
73 /* device interface */
74 DEVMETHOD(device_probe, xhci_pci_probe),
75 DEVMETHOD(device_attach, xhci_pci_attach),
76 DEVMETHOD(device_detach, xhci_pci_detach),
77 DEVMETHOD(device_suspend, bus_generic_suspend),
78 DEVMETHOD(device_resume, bus_generic_resume),
79 DEVMETHOD(device_shutdown, bus_generic_shutdown),
80 DEVMETHOD(usb_take_controller, xhci_pci_take_controller),
81
82 DEVMETHOD_END
83 };
84
85 DEFINE_CLASS_0(xhci, xhci_pci_driver, xhci_device_methods,
86 sizeof(struct xhci_softc));
87
88 DRIVER_MODULE(xhci, pci, xhci_pci_driver, NULL, NULL);
89 MODULE_DEPEND(xhci, usb, 1, 1, 1);
90
91 static const char *
xhci_pci_match(device_t self)92 xhci_pci_match(device_t self)
93 {
94 uint32_t device_id = pci_get_devid(self);
95
96 switch (device_id) {
97 case 0x145c1022:
98 return ("AMD KERNCZ USB 3.0 controller");
99 case 0x148c1022:
100 return ("AMD Starship USB 3.0 controller");
101 case 0x149c1022:
102 return ("AMD Matisse USB 3.0 controller");
103 case 0x15e01022:
104 case 0x15e11022:
105 return ("AMD Raven USB 3.1 controller");
106 case 0x43ba1022:
107 return ("AMD X399 USB 3.0 controller");
108 case 0x43b91022: /* X370 */
109 case 0x43bb1022: /* B350 */
110 return ("AMD 300 Series USB 3.1 controller");
111 case 0x43d51022:
112 return ("AMD 400 Series USB 3.1 controller");
113 case 0x78121022:
114 case 0x78141022:
115 case 0x79141022:
116 return ("AMD FCH USB 3.0 controller");
117
118 case 0x077815ad:
119 case 0x077915ad:
120 return ("VMware USB 3.0 controller");
121
122 case 0x145f1d94:
123 return ("Hygon USB 3.0 controller");
124
125 case 0x01941033:
126 return ("NEC uPD720200 USB 3.0 controller");
127 case 0x00151912:
128 return ("NEC uPD720202 USB 3.0 controller");
129
130 case 0x10001b73:
131 return ("Fresco Logic FL1000G USB 3.0 controller");
132 case 0x10091b73:
133 return ("Fresco Logic FL1009 USB 3.0 controller");
134 case 0x11001b73:
135 return ("Fresco Logic FL1100 USB 3.0 controller");
136
137 case 0x10421b21:
138 return ("ASMedia ASM1042 USB 3.0 controller");
139 case 0x11421b21:
140 return ("ASMedia ASM1042A USB 3.0 controller");
141 case 0x13431b21:
142 return ("ASMedia ASM1143 USB 3.1 controller");
143 case 0x32421b21:
144 return ("ASMedia ASM3242 USB 3.2 controller");
145
146 case 0x0b278086:
147 return ("Intel Goshen Ridge Thunderbolt 4 USB controller");
148 case 0x0f358086:
149 return ("Intel BayTrail USB 3.0 controller");
150 case 0x11388086:
151 return ("Intel Maple Ridge Thunderbolt 4 USB controller");
152 case 0x15c18086:
153 case 0x15d48086:
154 case 0x15db8086:
155 return ("Intel Alpine Ridge Thunderbolt 3 USB controller");
156 case 0x15e98086:
157 case 0x15ec8086:
158 case 0x15f08086:
159 return ("Intel Titan Ridge Thunderbolt 3 USB controller");
160 case 0x19d08086:
161 return ("Intel Denverton USB 3.0 controller");
162 case 0x9c318086:
163 case 0x1e318086:
164 return ("Intel Panther Point USB 3.0 controller");
165 case 0x22b58086:
166 return ("Intel Braswell USB 3.0 controller");
167 case 0x31a88086:
168 return ("Intel Gemini Lake USB 3.0 controller");
169 case 0x34ed8086:
170 return ("Intel Ice Lake-LP USB 3.1 controller");
171 case 0x43ed8086:
172 return ("Intel Tiger Lake-H USB 3.2 controller");
173 case 0x461e8086:
174 return ("Intel Alder Lake-P Thunderbolt 4 USB controller");
175 case 0x51ed8086:
176 return ("Intel Alder Lake USB 3.2 controller");
177 case 0x5aa88086:
178 return ("Intel Apollo Lake USB 3.0 controller");
179 case 0x7ae08086:
180 return ("Intel Alder Lake USB 3.2 controller");
181 case 0x8a138086:
182 return ("Intel Ice Lake Thunderbolt 3 USB controller");
183 case 0x8c318086:
184 return ("Intel Lynx Point USB 3.0 controller");
185 case 0x8cb18086:
186 return ("Intel Wildcat Point USB 3.0 controller");
187 case 0x8d318086:
188 return ("Intel Wellsburg USB 3.0 controller");
189 case 0x9a138086:
190 return ("Intel Tiger Lake-LP Thunderbolt 4 USB controller");
191 case 0x9a178086:
192 return ("Intel Tiger Lake-H Thunderbolt 4 USB controller");
193 case 0x9cb18086:
194 return ("Broadwell Integrated PCH-LP chipset USB 3.0 controller");
195 case 0x9d2f8086:
196 return ("Intel Sunrise Point-LP USB 3.0 controller");
197 case 0xa0ed8086:
198 return ("Intel Tiger Lake-LP USB 3.2 controller");
199 case 0xa12f8086:
200 return ("Intel Sunrise Point USB 3.0 controller");
201 case 0xa1af8086:
202 return ("Intel Lewisburg USB 3.0 controller");
203 case 0xa2af8086:
204 return ("Intel Union Point USB 3.0 controller");
205 case 0xa36d8086:
206 return ("Intel Cannon Lake USB 3.1 controller");
207
208 case 0xa01b177d:
209 return ("Cavium ThunderX USB 3.0 controller");
210
211 case 0x1ada10de:
212 return ("NVIDIA TU106 USB 3.1 controller");
213
214 case 0x92021d17:
215 return ("Zhaoxin ZX-100 USB 3.0 controller");
216 case 0x92031d17:
217 return ("Zhaoxin ZX-200 USB 3.0 controller");
218 case 0x92041d17:
219 return ("Zhaoxin ZX-E USB 3.0 controller");
220
221 default:
222 break;
223 }
224
225 if ((pci_get_class(self) == PCIC_SERIALBUS)
226 && (pci_get_subclass(self) == PCIS_SERIALBUS_USB)
227 && (pci_get_progif(self) == PCIP_SERIALBUS_USB_XHCI)) {
228 return ("XHCI (generic) USB 3.0 controller");
229 }
230 return (NULL); /* dunno */
231 }
232
233 static int
xhci_pci_probe(device_t self)234 xhci_pci_probe(device_t self)
235 {
236 const char *desc = xhci_pci_match(self);
237
238 if (desc) {
239 device_set_desc(self, desc);
240 return (BUS_PROBE_DEFAULT);
241 } else {
242 return (ENXIO);
243 }
244 }
245
246 static int xhci_use_msi = 1;
247 TUNABLE_INT("hw.usb.xhci.msi", &xhci_use_msi);
248 static int xhci_use_msix = 1;
249 TUNABLE_INT("hw.usb.xhci.msix", &xhci_use_msix);
250
251 static void
xhci_interrupt_poll(void * _sc)252 xhci_interrupt_poll(void *_sc)
253 {
254 struct xhci_softc *sc = _sc;
255 USB_BUS_UNLOCK(&sc->sc_bus);
256 xhci_interrupt(sc);
257 USB_BUS_LOCK(&sc->sc_bus);
258 usb_callout_reset(&sc->sc_callout, 1, (void *)&xhci_interrupt_poll, sc);
259 }
260
261 static int
xhci_pci_port_route(device_t self,uint32_t set,uint32_t clear)262 xhci_pci_port_route(device_t self, uint32_t set, uint32_t clear)
263 {
264 uint32_t temp;
265 uint32_t usb3_mask;
266 uint32_t usb2_mask;
267
268 temp = pci_read_config(self, PCI_XHCI_INTEL_USB3_PSSEN, 4) |
269 pci_read_config(self, PCI_XHCI_INTEL_XUSB2PR, 4);
270
271 temp |= set;
272 temp &= ~clear;
273
274 /* Don't set bits which the hardware doesn't support */
275 usb3_mask = pci_read_config(self, PCI_XHCI_INTEL_USB3PRM, 4);
276 usb2_mask = pci_read_config(self, PCI_XHCI_INTEL_USB2PRM, 4);
277
278 pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, temp & usb3_mask, 4);
279 pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, temp & usb2_mask, 4);
280
281 device_printf(self, "Port routing mask set to 0x%08x\n", temp);
282
283 return (0);
284 }
285
286 int
xhci_pci_attach(device_t self)287 xhci_pci_attach(device_t self)
288 {
289 struct xhci_softc *sc = device_get_softc(self);
290 int count, err, msix_table, rid;
291 uint8_t usemsi = 1;
292 uint8_t usedma32 = 0;
293
294 rid = PCI_XHCI_CBMEM;
295 sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid,
296 RF_ACTIVE);
297 if (!sc->sc_io_res) {
298 device_printf(self, "Could not map memory\n");
299 return (ENOMEM);
300 }
301 sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
302 sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
303 sc->sc_io_size = rman_get_size(sc->sc_io_res);
304
305 switch (pci_get_devid(self)) {
306 case 0x10091b73: /* Fresco Logic FL1009 USB3.0 xHCI Controller */
307 case 0x8241104c: /* TUSB73x0 USB3.0 xHCI Controller */
308 sc->sc_no_deconfigure = 1;
309 break;
310 case 0x01941033: /* NEC uPD720200 USB 3.0 controller */
311 case 0x00141912: /* NEC uPD720201 USB 3.0 controller */
312 /* Don't use 64-bit DMA on these controllers. */
313 usedma32 = 1;
314 break;
315 case 0x10001b73: /* FL1000G */
316 /* Fresco Logic host doesn't support MSI. */
317 usemsi = 0;
318 break;
319 case 0x0f358086: /* BayTrail */
320 case 0x9c318086: /* Panther Point */
321 case 0x1e318086: /* Panther Point */
322 case 0x8c318086: /* Lynx Point */
323 case 0x8cb18086: /* Wildcat Point */
324 case 0x9cb18086: /* Broadwell Mobile Integrated */
325 /*
326 * On Intel chipsets, reroute ports from EHCI to XHCI
327 * controller and use a different IMOD value.
328 */
329 sc->sc_port_route = &xhci_pci_port_route;
330 sc->sc_imod_default = XHCI_IMOD_DEFAULT_LP;
331 sc->sc_ctlstep = 1;
332 break;
333 default:
334 break;
335 }
336
337 if (xhci_init(sc, self, usedma32)) {
338 device_printf(self, "Could not initialize softc\n");
339 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM,
340 sc->sc_io_res);
341 return (ENXIO);
342 }
343
344 pci_enable_busmaster(self);
345
346 usb_callout_init_mtx(&sc->sc_callout, &sc->sc_bus.bus_mtx, 0);
347
348 rid = 0;
349 if (xhci_use_msix && (msix_table = pci_msix_table_bar(self)) >= 0) {
350 if (msix_table == PCI_XHCI_CBMEM) {
351 sc->sc_msix_res = sc->sc_io_res;
352 } else {
353 sc->sc_msix_res = bus_alloc_resource_any(self,
354 SYS_RES_MEMORY, &msix_table, RF_ACTIVE);
355 if (sc->sc_msix_res == NULL) {
356 /* May not be enabled */
357 device_printf(self,
358 "Unable to map MSI-X table\n");
359 }
360 }
361 if (sc->sc_msix_res != NULL) {
362 count = 1;
363 if (pci_alloc_msix(self, &count) == 0) {
364 if (bootverbose)
365 device_printf(self, "MSI-X enabled\n");
366 rid = 1;
367 } else {
368 if (sc->sc_msix_res != sc->sc_io_res) {
369 bus_release_resource(self,
370 SYS_RES_MEMORY,
371 msix_table, sc->sc_msix_res);
372 }
373 sc->sc_msix_res = NULL;
374 }
375 }
376 }
377 if (rid == 0 && xhci_use_msi && usemsi) {
378 count = 1;
379 if (pci_alloc_msi(self, &count) == 0) {
380 if (bootverbose)
381 device_printf(self, "MSI enabled\n");
382 rid = 1;
383 }
384 }
385 sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
386 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
387 if (sc->sc_irq_res == NULL) {
388 pci_release_msi(self);
389 device_printf(self, "Could not allocate IRQ\n");
390 /* goto error; FALLTHROUGH - use polling */
391 }
392 sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
393 if (sc->sc_bus.bdev == NULL) {
394 device_printf(self, "Could not add USB device\n");
395 goto error;
396 }
397 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
398
399 switch (pci_get_vendor(self)) {
400 case PCI_XHCI_VENDORID_AMD:
401 strlcpy(sc->sc_vendor, "AMD", sizeof(sc->sc_vendor));
402 break;
403 case PCI_XHCI_VENDORID_INTEL:
404 strlcpy(sc->sc_vendor, "Intel", sizeof(sc->sc_vendor));
405 break;
406 case PCI_XHCI_VENDORID_VMWARE:
407 strlcpy(sc->sc_vendor, "VMware", sizeof(sc->sc_vendor));
408 break;
409 case PCI_XHCI_VENDORID_ZHAOXIN:
410 strlcpy(sc->sc_vendor, "Zhaoxin", sizeof(sc->sc_vendor));
411 break;
412 default:
413 if (bootverbose)
414 device_printf(self, "(New XHCI DeviceId=0x%08x)\n",
415 pci_get_devid(self));
416 snprintf(sc->sc_vendor, sizeof(sc->sc_vendor),
417 "(0x%04x)", pci_get_vendor(self));
418 break;
419 }
420
421 if (sc->sc_irq_res != NULL && xhci_use_polling() == 0) {
422 err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
423 NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl);
424 if (err != 0) {
425 bus_release_resource(self, SYS_RES_IRQ,
426 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
427 sc->sc_irq_res = NULL;
428 pci_release_msi(self);
429 device_printf(self, "Could not setup IRQ, err=%d\n", err);
430 sc->sc_intr_hdl = NULL;
431 }
432 }
433 if (sc->sc_irq_res == NULL || sc->sc_intr_hdl == NULL) {
434 if (xhci_use_polling() != 0) {
435 device_printf(self, "Interrupt polling at %dHz\n", hz);
436 USB_BUS_LOCK(&sc->sc_bus);
437 xhci_interrupt_poll(sc);
438 USB_BUS_UNLOCK(&sc->sc_bus);
439 } else
440 goto error;
441 }
442
443 xhci_pci_take_controller(self);
444
445 err = xhci_halt_controller(sc);
446
447 if (err == 0)
448 err = xhci_start_controller(sc);
449
450 if (err == 0)
451 err = device_probe_and_attach(sc->sc_bus.bdev);
452
453 if (err) {
454 device_printf(self, "XHCI halt/start/probe failed err=%d\n", err);
455 goto error;
456 }
457 return (0);
458
459 error:
460 xhci_pci_detach(self);
461 return (ENXIO);
462 }
463
464 static int
xhci_pci_detach(device_t self)465 xhci_pci_detach(device_t self)
466 {
467 struct xhci_softc *sc = device_get_softc(self);
468
469 /* during module unload there are lots of children leftover */
470 device_delete_children(self);
471
472 usb_callout_drain(&sc->sc_callout);
473 xhci_halt_controller(sc);
474 xhci_reset_controller(sc);
475
476 pci_disable_busmaster(self);
477
478 if (sc->sc_irq_res && sc->sc_intr_hdl) {
479 bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl);
480 sc->sc_intr_hdl = NULL;
481 }
482 if (sc->sc_irq_res) {
483 bus_release_resource(self, SYS_RES_IRQ,
484 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
485 sc->sc_irq_res = NULL;
486 pci_release_msi(self);
487 }
488 if (sc->sc_msix_res != NULL && sc->sc_msix_res != sc->sc_io_res) {
489 bus_release_resource(self, SYS_RES_MEMORY,
490 rman_get_rid(sc->sc_msix_res), sc->sc_msix_res);
491 sc->sc_msix_res = NULL;
492 }
493 if (sc->sc_io_res) {
494 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM,
495 sc->sc_io_res);
496 sc->sc_io_res = NULL;
497 }
498
499 xhci_uninit(sc);
500
501 return (0);
502 }
503
504 static int
xhci_pci_take_controller(device_t self)505 xhci_pci_take_controller(device_t self)
506 {
507 struct xhci_softc *sc = device_get_softc(self);
508 uint32_t cparams;
509 uint32_t eecp;
510 uint32_t eec;
511 uint16_t to;
512 uint8_t bios_sem;
513
514 cparams = XREAD4(sc, capa, XHCI_HCSPARAMS0);
515
516 eec = -1;
517
518 /* Synchronise with the BIOS if it owns the controller. */
519 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec);
520 eecp += XHCI_XECP_NEXT(eec) << 2) {
521 eec = XREAD4(sc, capa, eecp);
522
523 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY)
524 continue;
525 bios_sem = XREAD1(sc, capa, eecp +
526 XHCI_XECP_BIOS_SEM);
527 if (bios_sem == 0)
528 continue;
529 device_printf(sc->sc_bus.bdev, "waiting for BIOS "
530 "to give up control\n");
531 XWRITE1(sc, capa, eecp +
532 XHCI_XECP_OS_SEM, 1);
533 to = 500;
534 while (1) {
535 bios_sem = XREAD1(sc, capa, eecp +
536 XHCI_XECP_BIOS_SEM);
537 if (bios_sem == 0)
538 break;
539
540 if (--to == 0) {
541 device_printf(sc->sc_bus.bdev,
542 "timed out waiting for BIOS\n");
543 break;
544 }
545 usb_pause_mtx(NULL, hz / 100); /* wait 10ms */
546 }
547 }
548 return (0);
549 }
550