1 /* $NetBSD: if_xi.c,v 1.77 2016/06/10 13:27:15 ozaki-r Exp $ */
2 /* OpenBSD: if_xe.c,v 1.9 1999/09/16 11:28:42 niklas Exp */
3
4 /*
5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Charles M. Hannum.
18 * 4. The name of the author may not be used to endorse or promote products
19 * derived from this software without specific prior written permission.
20 */
21
22 /*
23 * Copyright (c) 1999 Niklas Hallqvist, Brandon Creighton, Job de Haas
24 * All rights reserved.
25 *
26 * Redistribution and use in source and binary forms, with or without
27 * modification, are permitted provided that the following conditions
28 * are met:
29 * 1. Redistributions of source code must retain the above copyright
30 * notice, this list of conditions and the following disclaimer.
31 * 2. Redistributions in binary form must reproduce the above copyright
32 * notice, this list of conditions and the following disclaimer in the
33 * documentation and/or other materials provided with the distribution.
34 * 3. All advertising materials mentioning features or use of this software
35 * must display the following acknowledgement:
36 * This product includes software developed by Niklas Hallqvist,
37 * Brandon Creighton and Job de Haas.
38 * 4. The name of the author may not be used to endorse or promote products
39 * derived from this software without specific prior written permission
40 *
41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
44 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
46 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
50 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51 */
52
53 /*
54 * A driver for Xircom CreditCard PCMCIA Ethernet adapters.
55 */
56
57 #include <sys/cdefs.h>
58 __KERNEL_RCSID(0, "$NetBSD: if_xi.c,v 1.77 2016/06/10 13:27:15 ozaki-r Exp $");
59
60 #include "opt_inet.h"
61
62 #include <sys/param.h>
63 #include <sys/systm.h>
64 #include <sys/device.h>
65 #include <sys/ioctl.h>
66 #include <sys/mbuf.h>
67 #include <sys/malloc.h>
68 #include <sys/socket.h>
69 #include <sys/kernel.h>
70 #include <sys/proc.h>
71
72 #include <net/if.h>
73 #include <net/if_dl.h>
74 #include <net/if_media.h>
75 #include <net/if_types.h>
76 #include <net/if_ether.h>
77
78 #ifdef INET
79 #include <netinet/in.h>
80 #include <netinet/in_systm.h>
81 #include <netinet/in_var.h>
82 #include <netinet/ip.h>
83 #include <netinet/if_inarp.h>
84 #endif
85
86 #include <net/bpf.h>
87 #include <net/bpfdesc.h>
88
89 /*
90 * Maximum number of bytes to read per interrupt. Linux recommends
91 * somewhere between 2000-22000.
92 * XXX This is currently a hard maximum.
93 */
94 #define MAX_BYTES_INTR 12000
95
96 #include <dev/mii/mii.h>
97 #include <dev/mii/miivar.h>
98
99 #include <dev/pcmcia/pcmciareg.h>
100 #include <dev/pcmcia/pcmciavar.h>
101 #include <dev/pcmcia/pcmciadevs.h>
102
103 #include <dev/pcmcia/if_xireg.h>
104 #include <dev/pcmcia/if_xivar.h>
105
106 #ifdef __GNUC__
107 #define INLINE inline
108 #else
109 #define INLINE
110 #endif /* __GNUC__ */
111
112 #define XIDEBUG
113 #define XIDEBUG_VALUE 0
114
115 #ifdef XIDEBUG
116 #define DPRINTF(cat, x) if (xidebug & (cat)) printf x
117
118 #define XID_CONFIG 0x01
119 #define XID_MII 0x02
120 #define XID_INTR 0x04
121 #define XID_FIFO 0x08
122 #define XID_MCAST 0x10
123
124 #ifdef XIDEBUG_VALUE
125 int xidebug = XIDEBUG_VALUE;
126 #else
127 int xidebug = 0;
128 #endif
129 #else
130 #define DPRINTF(cat, x) (void)0
131 #endif
132
133 #define STATIC
134
135 STATIC int xi_enable(struct xi_softc *);
136 STATIC void xi_disable(struct xi_softc *);
137 STATIC void xi_cycle_power(struct xi_softc *);
138 STATIC int xi_ether_ioctl(struct ifnet *, u_long cmd, void *);
139 STATIC void xi_full_reset(struct xi_softc *);
140 STATIC void xi_init(struct xi_softc *);
141 STATIC int xi_ioctl(struct ifnet *, u_long, void *);
142 STATIC int xi_mdi_read(device_t, int, int);
143 STATIC void xi_mdi_write(device_t, int, int, int);
144 STATIC int xi_mediachange(struct ifnet *);
145 STATIC u_int16_t xi_get(struct xi_softc *);
146 STATIC void xi_reset(struct xi_softc *);
147 STATIC void xi_set_address(struct xi_softc *);
148 STATIC void xi_start(struct ifnet *);
149 STATIC void xi_statchg(struct ifnet *);
150 STATIC void xi_stop(struct xi_softc *);
151 STATIC void xi_watchdog(struct ifnet *);
152
153 void
xi_attach(struct xi_softc * sc,u_int8_t * myea)154 xi_attach(struct xi_softc *sc, u_int8_t *myea)
155 {
156 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
157
158 #if 0
159 /*
160 * Configuration as advised by DINGO documentation.
161 * Dingo has some extra configuration registers in the CCR space.
162 */
163 if (sc->sc_chipset >= XI_CHIPSET_DINGO) {
164 struct pcmcia_mem_handle pcmh;
165 int ccr_window;
166 bus_size_t ccr_offset;
167
168 /* get access to the DINGO CCR space */
169 if (pcmcia_mem_alloc(psc->sc_pf, PCMCIA_CCR_SIZE_DINGO,
170 &pcmh)) {
171 DPRINTF(XID_CONFIG, ("xi: bad mem alloc\n"));
172 goto fail;
173 }
174 if (pcmcia_mem_map(psc->sc_pf, PCMCIA_MEM_ATTR,
175 psc->sc_pf->ccr_base, PCMCIA_CCR_SIZE_DINGO,
176 &pcmh, &ccr_offset, &ccr_window)) {
177 DPRINTF(XID_CONFIG, ("xi: bad mem map\n"));
178 pcmcia_mem_free(psc->sc_pf, &pcmh);
179 goto fail;
180 }
181
182 /* enable the second function - usually modem */
183 bus_space_write_1(pcmh.memt, pcmh.memh,
184 ccr_offset + PCMCIA_CCR_DCOR0, PCMCIA_CCR_DCOR0_SFINT);
185 bus_space_write_1(pcmh.memt, pcmh.memh,
186 ccr_offset + PCMCIA_CCR_DCOR1,
187 PCMCIA_CCR_DCOR1_FORCE_LEVIREQ | PCMCIA_CCR_DCOR1_D6);
188 bus_space_write_1(pcmh.memt, pcmh.memh,
189 ccr_offset + PCMCIA_CCR_DCOR2, 0);
190 bus_space_write_1(pcmh.memt, pcmh.memh,
191 ccr_offset + PCMCIA_CCR_DCOR3, 0);
192 bus_space_write_1(pcmh.memt, pcmh.memh,
193 ccr_offset + PCMCIA_CCR_DCOR4, 0);
194
195 /* We don't need them anymore and can free them (I think). */
196 pcmcia_mem_unmap(psc->sc_pf, ccr_window);
197 pcmcia_mem_free(psc->sc_pf, &pcmh);
198 }
199 #endif
200
201 /* Reset and initialize the card. */
202 xi_full_reset(sc);
203
204 printf("%s: MAC address %s\n", device_xname(sc->sc_dev), ether_sprintf(myea));
205
206 ifp = &sc->sc_ethercom.ec_if;
207 /* Initialize the ifnet structure. */
208 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
209 ifp->if_softc = sc;
210 ifp->if_start = xi_start;
211 ifp->if_ioctl = xi_ioctl;
212 ifp->if_watchdog = xi_watchdog;
213 ifp->if_flags =
214 IFF_BROADCAST | IFF_NOTRAILERS | IFF_SIMPLEX | IFF_MULTICAST;
215 IFQ_SET_READY(&ifp->if_snd);
216
217 /* 802.1q capability */
218 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU;
219
220 /* Attach the interface. */
221 if_attach(ifp);
222 ether_ifattach(ifp, myea);
223
224 /*
225 * Initialize our media structures and probe the MII.
226 */
227 sc->sc_mii.mii_ifp = ifp;
228 sc->sc_mii.mii_readreg = xi_mdi_read;
229 sc->sc_mii.mii_writereg = xi_mdi_write;
230 sc->sc_mii.mii_statchg = xi_statchg;
231 sc->sc_ethercom.ec_mii = &sc->sc_mii;
232 ifmedia_init(&sc->sc_mii.mii_media, 0, xi_mediachange,
233 ether_mediastatus);
234 DPRINTF(XID_MII | XID_CONFIG,
235 ("xi: bmsr %x\n", xi_mdi_read(sc->sc_dev, 0, 1)));
236
237 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
238 MII_OFFSET_ANY, 0);
239 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL)
240 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO, 0,
241 NULL);
242 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO);
243
244 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev),
245 RND_TYPE_NET, RND_FLAG_DEFAULT);
246 }
247
248 int
xi_detach(device_t self,int flags)249 xi_detach(device_t self, int flags)
250 {
251 struct xi_softc *sc = device_private(self);
252 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
253
254 DPRINTF(XID_CONFIG, ("xi_detach()\n"));
255
256 xi_disable(sc);
257
258 rnd_detach_source(&sc->sc_rnd_source);
259
260 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY);
261 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY);
262 ether_ifdetach(ifp);
263 if_detach(ifp);
264
265 return 0;
266 }
267
268 int
xi_intr(void * arg)269 xi_intr(void *arg)
270 {
271 struct xi_softc *sc = arg;
272 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
273 u_int8_t esr, rsr, isr, rx_status;
274 u_int16_t tx_status, recvcount = 0, tempint;
275
276 DPRINTF(XID_CONFIG, ("xi_intr()\n"));
277
278 if (sc->sc_enabled == 0 || !device_is_active(sc->sc_dev))
279 return (0);
280
281 ifp->if_timer = 0; /* turn watchdog timer off */
282
283 PAGE(sc, 0);
284 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) {
285 /* Disable interrupt (Linux does it). */
286 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, 0);
287 }
288
289 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR);
290 isr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ISR0);
291 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR);
292
293 /* Check to see if card has been ejected. */
294 if (isr == 0xff) {
295 #ifdef DIAGNOSTIC
296 printf("%s: interrupt for dead card\n",
297 device_xname(sc->sc_dev));
298 #endif
299 goto end;
300 }
301 DPRINTF(XID_INTR, ("xi: isr=%02x\n", isr));
302
303 PAGE(sc, 0x40);
304 rx_status =
305 bus_space_read_1(sc->sc_bst, sc->sc_bsh, RXST0);
306 bus_space_write_1(sc->sc_bst, sc->sc_bsh, RXST0, ~rx_status & 0xff);
307 tx_status =
308 bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST0);
309 tx_status |=
310 bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST1) << 8;
311 bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST0, 0);
312 bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST1, 0);
313 DPRINTF(XID_INTR, ("xi: rx_status=%02x tx_status=%04x\n", rx_status,
314 tx_status));
315
316 PAGE(sc, 0);
317 while (esr & FULL_PKT_RCV) {
318 if (!(rsr & RSR_RX_OK))
319 break;
320
321 /* Compare bytes read this interrupt to hard maximum. */
322 if (recvcount > MAX_BYTES_INTR) {
323 DPRINTF(XID_INTR,
324 ("xi: too many bytes this interrupt\n"));
325 ifp->if_iqdrops++;
326 /* Drop packet. */
327 bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0,
328 DO_SKIP_RX_PKT);
329 }
330 tempint = xi_get(sc); /* XXX doesn't check the error! */
331 recvcount += tempint;
332 ifp->if_ibytes += tempint;
333 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR);
334 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR);
335 }
336
337 /* Packet too long? */
338 if (rsr & RSR_TOO_LONG) {
339 ifp->if_ierrors++;
340 DPRINTF(XID_INTR, ("xi: packet too long\n"));
341 }
342
343 /* CRC error? */
344 if (rsr & RSR_CRCERR) {
345 ifp->if_ierrors++;
346 DPRINTF(XID_INTR, ("xi: CRC error detected\n"));
347 }
348
349 /* Alignment error? */
350 if (rsr & RSR_ALIGNERR) {
351 ifp->if_ierrors++;
352 DPRINTF(XID_INTR, ("xi: alignment error detected\n"));
353 }
354
355 /* Check for rx overrun. */
356 if (rx_status & RX_OVERRUN) {
357 ifp->if_ierrors++;
358 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, CLR_RX_OVERRUN);
359 DPRINTF(XID_INTR, ("xi: overrun cleared\n"));
360 }
361
362 /* Try to start more packets transmitting. */
363 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0)
364 xi_start(ifp);
365
366 /* Detected excessive collisions? */
367 if ((tx_status & EXCESSIVE_COLL) && ifp->if_opackets > 0) {
368 DPRINTF(XID_INTR, ("xi: excessive collisions\n"));
369 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, RESTART_TX);
370 ifp->if_oerrors++;
371 }
372
373 if ((tx_status & TX_ABORT) && ifp->if_opackets > 0)
374 ifp->if_oerrors++;
375
376 /* have handled the interrupt */
377 rnd_add_uint32(&sc->sc_rnd_source, tx_status);
378
379 end:
380 /* Reenable interrupts. */
381 PAGE(sc, 0);
382 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, ENABLE_INT);
383
384 return (1);
385 }
386
387 /*
388 * Pull a packet from the card into an mbuf chain.
389 */
390 STATIC u_int16_t
xi_get(struct xi_softc * sc)391 xi_get(struct xi_softc *sc)
392 {
393 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
394 struct mbuf *top, **mp, *m;
395 u_int16_t pktlen, len, recvcount = 0;
396 u_int8_t *data;
397
398 DPRINTF(XID_CONFIG, ("xi_get()\n"));
399
400 PAGE(sc, 0);
401 pktlen =
402 bus_space_read_2(sc->sc_bst, sc->sc_bsh, RBC0) & RBC_COUNT_MASK;
403
404 DPRINTF(XID_CONFIG, ("xi_get: pktlen=%d\n", pktlen));
405
406 if (pktlen == 0) {
407 /*
408 * XXX At least one CE2 sets RBC0 == 0 occasionally, and only
409 * when MPE is set. It is not known why.
410 */
411 return (0);
412 }
413
414 /* XXX should this be incremented now ? */
415 recvcount += pktlen;
416
417 MGETHDR(m, M_DONTWAIT, MT_DATA);
418 if (m == NULL)
419 return (recvcount);
420 m_set_rcvif(m, ifp);
421 m->m_pkthdr.len = pktlen;
422 len = MHLEN;
423 top = NULL;
424 mp = ⊤
425
426 while (pktlen > 0) {
427 if (top) {
428 MGET(m, M_DONTWAIT, MT_DATA);
429 if (m == NULL) {
430 m_freem(top);
431 return (recvcount);
432 }
433 len = MLEN;
434 }
435 if (pktlen >= MINCLSIZE) {
436 MCLGET(m, M_DONTWAIT);
437 if (!(m->m_flags & M_EXT)) {
438 m_freem(m);
439 m_freem(top);
440 return (recvcount);
441 }
442 len = MCLBYTES;
443 }
444 if (top == NULL) {
445 char *newdata = (char *)ALIGN(m->m_data +
446 sizeof(struct ether_header)) -
447 sizeof(struct ether_header);
448 len -= newdata - m->m_data;
449 m->m_data = newdata;
450 }
451 len = min(pktlen, len);
452 data = mtod(m, u_int8_t *);
453 if (len > 1) {
454 len &= ~1;
455 bus_space_read_multi_2(sc->sc_bst, sc->sc_bsh, EDP,
456 (u_int16_t *)data, len>>1);
457 } else
458 *data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, EDP);
459 m->m_len = len;
460 pktlen -= len;
461 *mp = m;
462 mp = &m->m_next;
463 }
464
465 /* Skip Rx packet. */
466 bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0, DO_SKIP_RX_PKT);
467
468 if (top == NULL)
469 return recvcount;
470
471 /* Trim the CRC off the end of the packet. */
472 m_adj(top, -ETHER_CRC_LEN);
473
474 ifp->if_ipackets++;
475
476 bpf_mtap(ifp, top);
477
478 if_percpuq_enqueue(ifp->if_percpuq, top);
479 return (recvcount);
480 }
481
482 /*
483 * Serial management for the MII.
484 * The DELAY's below stem from the fact that the maximum frequency
485 * acceptable on the MDC pin is 2.5 MHz and fast processors can easily
486 * go much faster than that.
487 */
488
489 /* Let the MII serial management be idle for one period. */
490 static INLINE void xi_mdi_idle(struct xi_softc *);
491 static INLINE void
xi_mdi_idle(struct xi_softc * sc)492 xi_mdi_idle(struct xi_softc *sc)
493 {
494 bus_space_tag_t bst = sc->sc_bst;
495 bus_space_handle_t bsh = sc->sc_bsh;
496
497 /* Drive MDC low... */
498 bus_space_write_1(bst, bsh, GP2, MDC_LOW);
499 DELAY(1);
500
501 /* and high again. */
502 bus_space_write_1(bst, bsh, GP2, MDC_HIGH);
503 DELAY(1);
504 }
505
506 /* Pulse out one bit of data. */
507 static INLINE void xi_mdi_pulse(struct xi_softc *, int);
508 static INLINE void
xi_mdi_pulse(struct xi_softc * sc,int data)509 xi_mdi_pulse(struct xi_softc *sc, int data)
510 {
511 bus_space_tag_t bst = sc->sc_bst;
512 bus_space_handle_t bsh = sc->sc_bsh;
513 u_int8_t bit = data ? MDIO_HIGH : MDIO_LOW;
514
515 /* First latch the data bit MDIO with clock bit MDC low...*/
516 bus_space_write_1(bst, bsh, GP2, bit | MDC_LOW);
517 DELAY(1);
518
519 /* then raise the clock again, preserving the data bit. */
520 bus_space_write_1(bst, bsh, GP2, bit | MDC_HIGH);
521 DELAY(1);
522 }
523
524 /* Probe one bit of data. */
525 static INLINE int xi_mdi_probe(struct xi_softc *sc);
526 static INLINE int
xi_mdi_probe(struct xi_softc * sc)527 xi_mdi_probe(struct xi_softc *sc)
528 {
529 bus_space_tag_t bst = sc->sc_bst;
530 bus_space_handle_t bsh = sc->sc_bsh;
531 u_int8_t x;
532
533 /* Pull clock bit MDCK low... */
534 bus_space_write_1(bst, bsh, GP2, MDC_LOW);
535 DELAY(1);
536
537 /* Read data and drive clock high again. */
538 x = bus_space_read_1(bst, bsh, GP2);
539 bus_space_write_1(bst, bsh, GP2, MDC_HIGH);
540 DELAY(1);
541
542 return (x & MDIO);
543 }
544
545 /* Pulse out a sequence of data bits. */
546 static INLINE void xi_mdi_pulse_bits(struct xi_softc *, u_int32_t, int);
547 static INLINE void
xi_mdi_pulse_bits(struct xi_softc * sc,u_int32_t data,int len)548 xi_mdi_pulse_bits(struct xi_softc *sc, u_int32_t data, int len)
549 {
550 u_int32_t mask;
551
552 for (mask = 1 << (len - 1); mask; mask >>= 1)
553 xi_mdi_pulse(sc, data & mask);
554 }
555
556 /* Read a PHY register. */
557 STATIC int
xi_mdi_read(device_t self,int phy,int reg)558 xi_mdi_read(device_t self, int phy, int reg)
559 {
560 struct xi_softc *sc = device_private(self);
561 int i;
562 u_int32_t mask;
563 u_int32_t data = 0;
564
565 PAGE(sc, 2);
566 for (i = 0; i < 32; i++) /* Synchronize. */
567 xi_mdi_pulse(sc, 1);
568 xi_mdi_pulse_bits(sc, 0x06, 4); /* Start + Read opcode */
569 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */
570 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */
571 xi_mdi_idle(sc); /* Turn around. */
572 xi_mdi_probe(sc); /* Drop initial zero bit. */
573
574 for (mask = 1 << 15; mask; mask >>= 1) {
575 if (xi_mdi_probe(sc))
576 data |= mask;
577 }
578 xi_mdi_idle(sc);
579
580 DPRINTF(XID_MII,
581 ("xi_mdi_read: phy %d reg %d -> %x\n", phy, reg, data));
582
583 return (data);
584 }
585
586 /* Write a PHY register. */
587 STATIC void
xi_mdi_write(device_t self,int phy,int reg,int value)588 xi_mdi_write(device_t self, int phy, int reg, int value)
589 {
590 struct xi_softc *sc = device_private(self);
591 int i;
592
593 PAGE(sc, 2);
594 for (i = 0; i < 32; i++) /* Synchronize. */
595 xi_mdi_pulse(sc, 1);
596 xi_mdi_pulse_bits(sc, 0x05, 4); /* Start + Write opcode */
597 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */
598 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */
599 xi_mdi_pulse_bits(sc, 0x02, 2); /* Turn around. */
600 xi_mdi_pulse_bits(sc, value, 16); /* Write the data */
601 xi_mdi_idle(sc); /* Idle away. */
602
603 DPRINTF(XID_MII,
604 ("xi_mdi_write: phy %d reg %d val %x\n", phy, reg, value));
605 }
606
607 STATIC void
xi_statchg(struct ifnet * ifp)608 xi_statchg(struct ifnet *ifp)
609 {
610 /* XXX Update ifp->if_baudrate */
611 }
612
613 /*
614 * Change media according to request.
615 */
616 STATIC int
xi_mediachange(struct ifnet * ifp)617 xi_mediachange(struct ifnet *ifp)
618 {
619 int s;
620
621 DPRINTF(XID_CONFIG, ("xi_mediachange()\n"));
622
623 if (ifp->if_flags & IFF_UP) {
624 s = splnet();
625 xi_init(ifp->if_softc);
626 splx(s);
627 }
628 return (0);
629 }
630
631 STATIC void
xi_reset(struct xi_softc * sc)632 xi_reset(struct xi_softc *sc)
633 {
634 int s;
635
636 DPRINTF(XID_CONFIG, ("xi_reset()\n"));
637
638 s = splnet();
639 xi_stop(sc);
640 xi_init(sc);
641 splx(s);
642 }
643
644 STATIC void
xi_watchdog(struct ifnet * ifp)645 xi_watchdog(struct ifnet *ifp)
646 {
647 struct xi_softc *sc = ifp->if_softc;
648
649 printf("%s: device timeout\n", device_xname(sc->sc_dev));
650 ++ifp->if_oerrors;
651
652 xi_reset(sc);
653 }
654
655 STATIC void
xi_stop(register struct xi_softc * sc)656 xi_stop(register struct xi_softc *sc)
657 {
658 bus_space_tag_t bst = sc->sc_bst;
659 bus_space_handle_t bsh = sc->sc_bsh;
660
661 DPRINTF(XID_CONFIG, ("xi_stop()\n"));
662
663 PAGE(sc, 0x40);
664 bus_space_write_1(bst, bsh, CMD0, DISABLE_RX);
665
666 /* Disable interrupts. */
667 PAGE(sc, 0);
668 bus_space_write_1(bst, bsh, CR, 0);
669
670 PAGE(sc, 1);
671 bus_space_write_1(bst, bsh, IMR0, 0);
672
673 /* Cancel watchdog timer. */
674 sc->sc_ethercom.ec_if.if_timer = 0;
675 }
676
677 STATIC int
xi_enable(struct xi_softc * sc)678 xi_enable(struct xi_softc *sc)
679 {
680 int error;
681
682 if (!sc->sc_enabled) {
683 error = (*sc->sc_enable)(sc);
684 if (error)
685 return (error);
686 sc->sc_enabled = 1;
687 xi_full_reset(sc);
688 }
689 return (0);
690 }
691
692 STATIC void
xi_disable(struct xi_softc * sc)693 xi_disable(struct xi_softc *sc)
694 {
695
696 if (sc->sc_enabled) {
697 sc->sc_enabled = 0;
698 (*sc->sc_disable)(sc);
699 }
700 }
701
702 STATIC void
xi_init(struct xi_softc * sc)703 xi_init(struct xi_softc *sc)
704 {
705 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
706 bus_space_tag_t bst = sc->sc_bst;
707 bus_space_handle_t bsh = sc->sc_bsh;
708
709 DPRINTF(XID_CONFIG, ("xi_init()\n"));
710
711 /* Setup the ethernet interrupt mask. */
712 PAGE(sc, 1);
713 bus_space_write_1(bst, bsh, IMR0,
714 ISR_TX_OFLOW | ISR_PKT_TX | ISR_MAC_INT | /* ISR_RX_EARLY | */
715 ISR_RX_FULL | ISR_RX_PKT_REJ | ISR_FORCED_INT);
716 if (sc->sc_chipset < XI_CHIPSET_DINGO) {
717 /* XXX What is this? Not for Dingo at least. */
718 /* Unmask TX underrun detection */
719 bus_space_write_1(bst, bsh, IMR1, 1);
720 }
721
722 /* Enable interrupts. */
723 PAGE(sc, 0);
724 bus_space_write_1(bst, bsh, CR, ENABLE_INT);
725
726 xi_set_address(sc);
727
728 PAGE(sc, 0x40);
729 bus_space_write_1(bst, bsh, CMD0, ENABLE_RX | ONLINE);
730
731 PAGE(sc, 0);
732
733 /* Set current media. */
734 mii_mediachg(&sc->sc_mii);
735
736 ifp->if_flags |= IFF_RUNNING;
737 ifp->if_flags &= ~IFF_OACTIVE;
738
739 xi_start(ifp);
740 }
741
742 /*
743 * Start outputting on the interface.
744 * Always called as splnet().
745 */
746 STATIC void
xi_start(struct ifnet * ifp)747 xi_start(struct ifnet *ifp)
748 {
749 struct xi_softc *sc = ifp->if_softc;
750 bus_space_tag_t bst = sc->sc_bst;
751 bus_space_handle_t bsh = sc->sc_bsh;
752 unsigned int s, len, pad = 0;
753 struct mbuf *m0, *m;
754 u_int16_t space;
755
756 DPRINTF(XID_CONFIG, ("xi_start()\n"));
757
758 /* Don't transmit if interface is busy or not running. */
759 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) {
760 DPRINTF(XID_CONFIG, ("xi: interface busy or not running\n"));
761 return;
762 }
763
764 /* Peek at the next packet. */
765 IFQ_POLL(&ifp->if_snd, m0);
766 if (m0 == 0)
767 return;
768
769 /* We need to use m->m_pkthdr.len, so require the header. */
770 if (!(m0->m_flags & M_PKTHDR))
771 panic("xi_start: no header mbuf");
772
773 len = m0->m_pkthdr.len;
774
775 #if 1
776 /* Pad to ETHER_MIN_LEN - ETHER_CRC_LEN. */
777 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
778 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
779 #else
780 pad = 0;
781 #endif
782
783 PAGE(sc, 0);
784
785 bus_space_write_2(bst, bsh, TRS, (u_int16_t)len + pad + 2);
786 space = bus_space_read_2(bst, bsh, TSO) & 0x7fff;
787 if (len + pad + 2 > space) {
788 DPRINTF(XID_FIFO,
789 ("xi: not enough space in output FIFO (%d > %d)\n",
790 len + pad + 2, space));
791 return;
792 }
793
794 IFQ_DEQUEUE(&ifp->if_snd, m0);
795
796 bpf_mtap(ifp, m0);
797
798 /*
799 * Do the output at splhigh() so that an interrupt from another device
800 * won't cause a FIFO underrun.
801 */
802 s = splhigh();
803
804 bus_space_write_2(bst, bsh, EDP, (u_int16_t)len + pad);
805 for (m = m0; m; ) {
806 if (m->m_len > 1)
807 bus_space_write_multi_2(bst, bsh, EDP,
808 mtod(m, u_int16_t *), m->m_len>>1);
809 if (m->m_len & 1) {
810 DPRINTF(XID_CONFIG, ("xi: XXX odd!\n"));
811 bus_space_write_1(bst, bsh, EDP,
812 *(mtod(m, u_int8_t *) + m->m_len - 1));
813 }
814 MFREE(m, m0);
815 m = m0;
816 }
817 DPRINTF(XID_CONFIG, ("xi: len=%d pad=%d total=%d\n", len, pad, len+pad+4));
818 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK)
819 bus_space_write_1(bst, bsh, CR, TX_PKT | ENABLE_INT);
820 else {
821 for (; pad > 1; pad -= 2)
822 bus_space_write_2(bst, bsh, EDP, 0);
823 if (pad == 1)
824 bus_space_write_1(bst, bsh, EDP, 0);
825 }
826
827 splx(s);
828
829 ifp->if_timer = 5;
830 ++ifp->if_opackets;
831 }
832
833 STATIC int
xi_ether_ioctl(struct ifnet * ifp,u_long cmd,void * data)834 xi_ether_ioctl(struct ifnet *ifp, u_long cmd, void *data)
835 {
836 struct ifaddr *ifa = (struct ifaddr *)data;
837 struct xi_softc *sc = ifp->if_softc;
838 int error;
839
840 DPRINTF(XID_CONFIG, ("xi_ether_ioctl()\n"));
841
842 switch (cmd) {
843 case SIOCINITIFADDR:
844 if ((error = xi_enable(sc)) != 0)
845 break;
846
847 ifp->if_flags |= IFF_UP;
848
849 xi_init(sc);
850 switch (ifa->ifa_addr->sa_family) {
851 #ifdef INET
852 case AF_INET:
853 arp_ifinit(ifp, ifa);
854 break;
855 #endif /* INET */
856
857
858 default:
859 break;
860 }
861 break;
862
863 default:
864 return (EINVAL);
865 }
866
867 return (0);
868 }
869
870 STATIC int
xi_ioctl(struct ifnet * ifp,u_long cmd,void * data)871 xi_ioctl(struct ifnet *ifp, u_long cmd, void *data)
872 {
873 struct xi_softc *sc = ifp->if_softc;
874 int s, error = 0;
875
876 DPRINTF(XID_CONFIG, ("xi_ioctl()\n"));
877
878 s = splnet();
879
880 switch (cmd) {
881 case SIOCINITIFADDR:
882 error = xi_ether_ioctl(ifp, cmd, data);
883 break;
884
885 case SIOCSIFFLAGS:
886 if ((error = ifioctl_common(ifp, cmd, data)) != 0)
887 break;
888 /* XXX re-use ether_ioctl() */
889 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) {
890 case IFF_RUNNING:
891 /*
892 * If interface is marked down and it is running,
893 * stop it.
894 */
895 xi_stop(sc);
896 ifp->if_flags &= ~IFF_RUNNING;
897 xi_disable(sc);
898 break;
899 case IFF_UP:
900 /*
901 * If interface is marked up and it is stopped,
902 * start it.
903 */
904 if ((error = xi_enable(sc)) != 0)
905 break;
906 xi_init(sc);
907 break;
908 case IFF_UP|IFF_RUNNING:
909 /*
910 * Reset the interface to pick up changes in any
911 * other flags that affect hardware registers.
912 */
913 xi_set_address(sc);
914 break;
915 case 0:
916 break;
917 }
918 break;
919
920 case SIOCADDMULTI:
921 case SIOCDELMULTI:
922 if (sc->sc_enabled == 0) {
923 error = EIO;
924 break;
925 }
926 /*FALLTHROUGH*/
927 case SIOCSIFMEDIA:
928 case SIOCGIFMEDIA:
929 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) {
930 /*
931 * Multicast list has changed; set the hardware
932 * filter accordingly.
933 */
934 if (ifp->if_flags & IFF_RUNNING)
935 xi_set_address(sc);
936 error = 0;
937 }
938 break;
939
940 default:
941 error = ether_ioctl(ifp, cmd, data);
942 break;
943 }
944
945 splx(s);
946 return (error);
947 }
948
949 STATIC void
xi_set_address(struct xi_softc * sc)950 xi_set_address(struct xi_softc *sc)
951 {
952 bus_space_tag_t bst = sc->sc_bst;
953 bus_space_handle_t bsh = sc->sc_bsh;
954 struct ethercom *ether = &sc->sc_ethercom;
955 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
956 struct ether_multistep step;
957 struct ether_multi *enm;
958 int page, num;
959 int i;
960 u_int8_t x;
961 const u_int8_t *enaddr;
962 u_int8_t indaddr[64];
963
964 DPRINTF(XID_CONFIG, ("xi_set_address()\n"));
965
966 enaddr = (const u_int8_t *)CLLADDR(ifp->if_sadl);
967 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK)
968 for (i = 0; i < 6; i++)
969 indaddr[i] = enaddr[5 - i];
970 else
971 for (i = 0; i < 6; i++)
972 indaddr[i] = enaddr[i];
973 num = 1;
974
975 if (ether->ec_multicnt > 9) {
976 ifp->if_flags |= IFF_ALLMULTI;
977 goto done;
978 }
979
980 ETHER_FIRST_MULTI(step, ether, enm);
981 for (; enm; num++) {
982 if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
983 sizeof(enm->enm_addrlo)) != 0) {
984 /*
985 * The multicast address is really a range;
986 * it's easier just to accept all multicasts.
987 * XXX should we be setting IFF_ALLMULTI here?
988 */
989 ifp->if_flags |= IFF_ALLMULTI;
990 goto done;
991 }
992 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK)
993 for (i = 0; i < 6; i++)
994 indaddr[num * 6 + i] = enm->enm_addrlo[5 - i];
995 else
996 for (i = 0; i < 6; i++)
997 indaddr[num * 6 + i] = enm->enm_addrlo[i];
998 ETHER_NEXT_MULTI(step, enm);
999 }
1000 ifp->if_flags &= ~IFF_ALLMULTI;
1001
1002 done:
1003 if (num < 10)
1004 memset(&indaddr[num * 6], 0xff, 6 * (10 - num));
1005
1006 for (page = 0; page < 8; page++) {
1007 #ifdef XIDEBUG
1008 if (xidebug & XID_MCAST) {
1009 printf("page %d before:", page);
1010 for (i = 0; i < 8; i++)
1011 printf(" %02x", indaddr[page * 8 + i]);
1012 printf("\n");
1013 }
1014 #endif
1015
1016 PAGE(sc, 0x50 + page);
1017 bus_space_write_region_1(bst, bsh, IA, &indaddr[page * 8],
1018 page == 7 ? 4 : 8);
1019 /*
1020 * XXX
1021 * Without this delay, the address registers on my CE2 get
1022 * trashed the first and I have to cycle it. I have no idea
1023 * why. - mycroft, 2004/08/09
1024 */
1025 DELAY(50);
1026
1027 #ifdef XIDEBUG
1028 if (xidebug & XID_MCAST) {
1029 bus_space_read_region_1(bst, bsh, IA,
1030 &indaddr[page * 8], page == 7 ? 4 : 8);
1031 printf("page %d after: ", page);
1032 for (i = 0; i < 8; i++)
1033 printf(" %02x", indaddr[page * 8 + i]);
1034 printf("\n");
1035 }
1036 #endif
1037 }
1038
1039 PAGE(sc, 0x42);
1040 x = SWC1_IND_ADDR;
1041 if (ifp->if_flags & IFF_PROMISC)
1042 x |= SWC1_PROMISC;
1043 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC))
1044 x |= SWC1_MCAST_PROM;
1045 if (!LIST_FIRST(&sc->sc_mii.mii_phys))
1046 x |= SWC1_AUTO_MEDIA;
1047 bus_space_write_1(sc->sc_bst, sc->sc_bsh, SWC1, x);
1048 }
1049
1050 STATIC void
xi_cycle_power(struct xi_softc * sc)1051 xi_cycle_power(struct xi_softc *sc)
1052 {
1053 bus_space_tag_t bst = sc->sc_bst;
1054 bus_space_handle_t bsh = sc->sc_bsh;
1055
1056 DPRINTF(XID_CONFIG, ("xi_cycle_power()\n"));
1057
1058 PAGE(sc, 4);
1059 DELAY(1);
1060 bus_space_write_1(bst, bsh, GP1, 0);
1061 tsleep(&xi_cycle_power, PWAIT, "xipwr1", hz * 40 / 1000);
1062 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK)
1063 bus_space_write_1(bst, bsh, GP1, POWER_UP);
1064 else
1065 /* XXX What is bit 2 (aka AIC)? */
1066 bus_space_write_1(bst, bsh, GP1, POWER_UP | 4);
1067 tsleep(&xi_cycle_power, PWAIT, "xipwr2", hz * 20 / 1000);
1068 }
1069
1070 STATIC void
xi_full_reset(struct xi_softc * sc)1071 xi_full_reset(struct xi_softc *sc)
1072 {
1073 bus_space_tag_t bst = sc->sc_bst;
1074 bus_space_handle_t bsh = sc->sc_bsh;
1075 u_int8_t x;
1076
1077 DPRINTF(XID_CONFIG, ("xi_full_reset()\n"));
1078
1079 /* Do an as extensive reset as possible on all functions. */
1080 xi_cycle_power(sc);
1081 bus_space_write_1(bst, bsh, CR, SOFT_RESET);
1082 tsleep(&xi_full_reset, PWAIT, "xirst1", hz * 20 / 1000);
1083 bus_space_write_1(bst, bsh, CR, 0);
1084 tsleep(&xi_full_reset, PWAIT, "xirst2", hz * 20 / 1000);
1085 PAGE(sc, 4);
1086 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) {
1087 /*
1088 * Drive GP1 low to power up ML6692 and GP2 high to power up
1089 * the 10MHz chip. XXX What chip is that? The phy?
1090 */
1091 bus_space_write_1(bst, bsh, GP0, GP1_OUT | GP2_OUT | GP2_WR);
1092 }
1093 tsleep(&xi_full_reset, PWAIT, "xirst3", hz * 500 / 1000);
1094
1095 /* Get revision information. XXX Symbolic constants. */
1096 sc->sc_rev = bus_space_read_1(bst, bsh, BV) &
1097 ((sc->sc_chipset >= XI_CHIPSET_MOHAWK) ? 0x70 : 0x30) >> 4;
1098 DPRINTF(XID_CONFIG, ("xi: rev=%02x\n", sc->sc_rev));
1099
1100 /* Media selection. XXX Maybe manual overriding too? */
1101 if (sc->sc_chipset < XI_CHIPSET_MOHAWK) {
1102 /*
1103 * XXX I have no idea what this really does, it is from the
1104 * Linux driver.
1105 */
1106 bus_space_write_1(bst, bsh, GP0, GP1_OUT);
1107 }
1108 tsleep(&xi_full_reset, PWAIT, "xirst4", hz * 40 / 1000);
1109
1110 /*
1111 * Disable source insertion.
1112 * XXX Dingo does not have this bit, but Linux does it unconditionally.
1113 */
1114 if (sc->sc_chipset < XI_CHIPSET_DINGO) {
1115 PAGE(sc, 0x42);
1116 bus_space_write_1(bst, bsh, SWC0, 0x20);
1117 }
1118
1119 /* Set the local memory dividing line. */
1120 if (sc->sc_rev != 1) {
1121 PAGE(sc, 2);
1122 /* XXX Symbolic constant preferrable. */
1123 bus_space_write_2(bst, bsh, RBS0, 0x2000);
1124 }
1125
1126 /*
1127 * Apparently the receive byte pointer can be bad after a reset, so
1128 * we hardwire it correctly.
1129 */
1130 PAGE(sc, 0);
1131 bus_space_write_2(bst, bsh, DO0, DO_CHG_OFFSET);
1132
1133 /* Setup ethernet MAC registers. XXX Symbolic constants. */
1134 PAGE(sc, 0x40);
1135 bus_space_write_1(bst, bsh, RX0MSK,
1136 PKT_TOO_LONG | CRC_ERR | RX_OVERRUN | RX_ABORT | RX_OK);
1137 bus_space_write_1(bst, bsh, TX0MSK,
1138 CARRIER_LOST | EXCESSIVE_COLL | TX_UNDERRUN | LATE_COLLISION |
1139 SQE | TX_ABORT | TX_OK);
1140 if (sc->sc_chipset < XI_CHIPSET_DINGO)
1141 /* XXX From Linux, dunno what 0xb0 means. */
1142 bus_space_write_1(bst, bsh, TX1MSK, 0xb0);
1143 bus_space_write_1(bst, bsh, RXST0, 0);
1144 bus_space_write_1(bst, bsh, TXST0, 0);
1145 bus_space_write_1(bst, bsh, TXST1, 0);
1146
1147 PAGE(sc, 2);
1148
1149 /* Enable MII function if available. */
1150 x = 0;
1151 if (LIST_FIRST(&sc->sc_mii.mii_phys))
1152 x |= SELECT_MII;
1153 bus_space_write_1(bst, bsh, MSR, x);
1154 tsleep(&xi_full_reset, PWAIT, "xirst5", hz * 20 / 1000);
1155
1156 /* Configure the LED registers. */
1157 /* XXX This is not good for 10base2. */
1158 bus_space_write_1(bst, bsh, LED,
1159 (LED_TX_ACT << LED1_SHIFT) | (LED_10MB_LINK << LED0_SHIFT));
1160 if (sc->sc_chipset >= XI_CHIPSET_DINGO)
1161 bus_space_write_1(bst, bsh, LED3, LED_100MB_LINK << LED3_SHIFT);
1162
1163 /*
1164 * The Linux driver says this:
1165 * We should switch back to page 0 to avoid a bug in revision 0
1166 * where regs with offset below 8 can't be read after an access
1167 * to the MAC registers.
1168 */
1169 PAGE(sc, 0);
1170 }
1171