1 /*
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: src/sys/pci/if_xl.c,v 1.72.2.28 2003/10/08 06:01:57 murray Exp $
33 */
34
35 /*
36 * 3Com 3c90x Etherlink XL PCI NIC driver
37 *
38 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI
39 * bus-master chips (3c90x cards and embedded controllers) including
40 * the following:
41 *
42 * 3Com 3c900-TPO 10Mbps/RJ-45
43 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC
44 * 3Com 3c905-TX 10/100Mbps/RJ-45
45 * 3Com 3c905-T4 10/100Mbps/RJ-45
46 * 3Com 3c900B-TPO 10Mbps/RJ-45
47 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC
48 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC
49 * 3Com 3c900B-FL 10Mbps/Fiber-optic
50 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC
51 * 3Com 3c905B-TX 10/100Mbps/RJ-45
52 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic
53 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC)
54 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC)
55 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC)
56 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC)
57 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC)
58 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane)
59 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
60 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
61 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
62 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
63 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
64 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
65 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
66 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC)
67 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
68 * Dell on-board 3c920 10/100Mbps/RJ-45
69 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
70 * Dell Latitude laptop docking station embedded 3c905-TX
71 *
72 * Written by Bill Paul <wpaul@ctr.columbia.edu>
73 * Electrical Engineering Department
74 * Columbia University, New York City
75 */
76
77 /*
78 * The 3c90x series chips use a bus-master DMA interface for transfering
79 * packets to and from the controller chip. Some of the "vortex" cards
80 * (3c59x) also supported a bus master mode, however for those chips
81 * you could only DMA packets to/from a contiguous memory buffer. For
82 * transmission this would mean copying the contents of the queued mbuf
83 * chain into an mbuf cluster and then DMAing the cluster. This extra
84 * copy would sort of defeat the purpose of the bus master support for
85 * any packet that doesn't fit into a single mbuf.
86 *
87 * By contrast, the 3c90x cards support a fragment-based bus master
88 * mode where mbuf chains can be encapsulated using TX descriptors.
89 * This is similar to other PCI chips such as the Texas Instruments
90 * ThunderLAN and the Intel 82557/82558.
91 *
92 * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
93 * bus master chips because they maintain the old PIO interface for
94 * backwards compatibility, but starting with the 3c905B and the
95 * "cyclone" chips, the compatibility interface has been dropped.
96 * Since using bus master DMA is a big win, we use this driver to
97 * support the PCI "boomerang" chips even though they work with the
98 * "vortex" driver in order to obtain better performance.
99 */
100
101 #include "opt_ifpoll.h"
102
103 #include <sys/param.h>
104 #include <sys/systm.h>
105 #include <sys/sockio.h>
106 #include <sys/endian.h>
107 #include <sys/malloc.h> /* for M_NOWAIT */
108 #include <sys/mbuf.h>
109 #include <sys/kernel.h>
110 #include <sys/socket.h>
111 #include <sys/serialize.h>
112 #include <sys/bus.h>
113 #include <sys/rman.h>
114 #include <sys/interrupt.h>
115
116 #include <net/if.h>
117 #include <net/ifq_var.h>
118 #include <net/if_arp.h>
119 #include <net/ethernet.h>
120 #include <net/if_dl.h>
121 #include <net/if_media.h>
122 #include <net/if_poll.h>
123 #include <net/vlan/if_vlan_var.h>
124
125 #include <net/bpf.h>
126
127 #include "../mii_layer/mii.h"
128 #include "../mii_layer/miivar.h"
129
130 #include <bus/pci/pcireg.h>
131 #include <bus/pci/pcivar.h>
132
133 /* "controller miibus0" required. See GENERIC if you get errors here. */
134 #include "miibus_if.h"
135
136 #include "if_xlreg.h"
137
138 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
139
140 /*
141 * Various supported device vendors/types and their names.
142 */
143 static struct xl_type xl_devs[] = {
144 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
145 "3Com 3c900-TPO Etherlink XL" },
146 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
147 "3Com 3c900-COMBO Etherlink XL" },
148 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
149 "3Com 3c905-TX Fast Etherlink XL" },
150 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
151 "3Com 3c905-T4 Fast Etherlink XL" },
152 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
153 "3Com 3c900B-TPO Etherlink XL" },
154 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
155 "3Com 3c900B-COMBO Etherlink XL" },
156 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
157 "3Com 3c900B-TPC Etherlink XL" },
158 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
159 "3Com 3c900B-FL Etherlink XL" },
160 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
161 "3Com 3c905B-TX Fast Etherlink XL" },
162 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
163 "3Com 3c905B-T4 Fast Etherlink XL" },
164 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
165 "3Com 3c905B-FX/SC Fast Etherlink XL" },
166 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
167 "3Com 3c905B-COMBO Fast Etherlink XL" },
168 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
169 "3Com 3c905C-TX Fast Etherlink XL" },
170 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B,
171 "3Com 3c920B-EMB Integrated Fast Etherlink XL" },
172 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
173 "3Com 3c980 Fast Etherlink XL" },
174 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
175 "3Com 3c980C Fast Etherlink XL" },
176 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
177 "3Com 3cSOHO100-TX OfficeConnect" },
178 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
179 "3Com 3c450-TX HomeConnect" },
180 { TC_VENDORID, TC_DEVICEID_HURRICANE_555,
181 "3Com 3c555 Fast Etherlink XL" },
182 { TC_VENDORID, TC_DEVICEID_HURRICANE_556,
183 "3Com 3c556 Fast Etherlink XL" },
184 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
185 "3Com 3c556B Fast Etherlink XL" },
186 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A,
187 "3Com 3c575TX Fast Etherlink XL" },
188 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
189 "3Com 3c575B Fast Etherlink XL" },
190 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
191 "3Com 3c575C Fast Etherlink XL" },
192 { TC_VENDORID, TC_DEVICEID_HURRICANE_656,
193 "3Com 3c656 Fast Etherlink XL" },
194 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B,
195 "3Com 3c656B Fast Etherlink XL" },
196 { TC_VENDORID, TC_DEVICEID_TORNADO_656C,
197 "3Com 3c656C Fast Etherlink XL" },
198 { 0, 0, NULL }
199 };
200
201 static int xl_probe (device_t);
202 static int xl_attach (device_t);
203 static int xl_detach (device_t);
204 static void xl_shutdown (device_t);
205 static int xl_suspend (device_t);
206 static int xl_resume (device_t);
207
208 static int xl_newbuf (struct xl_softc *, struct xl_chain_onefrag *,
209 int);
210 static void xl_stats_update (void *);
211 static void xl_stats_update_serialized(void *);
212 static int xl_encap (struct xl_softc *, struct xl_chain *,
213 struct mbuf *);
214 static void xl_rxeof (struct xl_softc *, int);
215 static int xl_rx_resync (struct xl_softc *);
216 static void xl_txeof (struct xl_softc *);
217 static void xl_txeof_90xB (struct xl_softc *);
218 static void xl_txeoc (struct xl_softc *);
219 static void xl_intr (void *);
220 static void xl_start_body (struct ifnet *, int);
221 static void xl_start (struct ifnet *, struct ifaltq_subque *);
222 static void xl_start_90xB (struct ifnet *, struct ifaltq_subque *);
223 static int xl_ioctl (struct ifnet *, u_long, caddr_t,
224 struct ucred *);
225 static void xl_init (void *);
226 static void xl_stop (struct xl_softc *);
227 static void xl_watchdog (struct ifnet *);
228 #ifdef IFPOLL_ENABLE
229 static void xl_start_poll (struct ifnet *, struct ifaltq_subque *);
230 static void xl_npoll (struct ifnet *, struct ifpoll_info *);
231 static void xl_npoll_compat (struct ifnet *, void *, int);
232 #endif
233 static void xl_enable_intrs (struct xl_softc *, uint16_t);
234
235 static int xl_ifmedia_upd (struct ifnet *);
236 static void xl_ifmedia_sts (struct ifnet *, struct ifmediareq *);
237
238 static int xl_eeprom_wait (struct xl_softc *);
239 static int xl_read_eeprom (struct xl_softc *, caddr_t, int, int, int);
240 static void xl_mii_sync (struct xl_softc *);
241 static void xl_mii_send (struct xl_softc *, u_int32_t, int);
242 static int xl_mii_readreg (struct xl_softc *, struct xl_mii_frame *);
243 static int xl_mii_writereg (struct xl_softc *, struct xl_mii_frame *);
244
245 static void xl_setcfg (struct xl_softc *);
246 static void xl_setmode (struct xl_softc *, int);
247 static void xl_setmulti (struct xl_softc *);
248 static void xl_setmulti_hash (struct xl_softc *);
249 static void xl_reset (struct xl_softc *);
250 static int xl_list_rx_init (struct xl_softc *);
251 static void xl_list_tx_init (struct xl_softc *);
252 static void xl_list_tx_init_90xB(struct xl_softc *);
253 static void xl_wait (struct xl_softc *);
254 static void xl_mediacheck (struct xl_softc *);
255 static void xl_choose_xcvr (struct xl_softc *, int);
256
257 static int xl_dma_alloc (device_t);
258 static void xl_dma_free (device_t);
259
260 #ifdef notdef
261 static void xl_testpacket (struct xl_softc *);
262 #endif
263
264 static int xl_miibus_readreg (device_t, int, int);
265 static int xl_miibus_writereg (device_t, int, int, int);
266 static void xl_miibus_statchg (device_t);
267 static void xl_miibus_mediainit (device_t);
268
269 static device_method_t xl_methods[] = {
270 /* Device interface */
271 DEVMETHOD(device_probe, xl_probe),
272 DEVMETHOD(device_attach, xl_attach),
273 DEVMETHOD(device_detach, xl_detach),
274 DEVMETHOD(device_shutdown, xl_shutdown),
275 DEVMETHOD(device_suspend, xl_suspend),
276 DEVMETHOD(device_resume, xl_resume),
277
278 /* bus interface */
279 DEVMETHOD(bus_print_child, bus_generic_print_child),
280 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
281
282 /* MII interface */
283 DEVMETHOD(miibus_readreg, xl_miibus_readreg),
284 DEVMETHOD(miibus_writereg, xl_miibus_writereg),
285 DEVMETHOD(miibus_statchg, xl_miibus_statchg),
286 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit),
287
288 DEVMETHOD_END
289 };
290
291 static driver_t xl_driver = {
292 "xl",
293 xl_methods,
294 sizeof(struct xl_softc)
295 };
296
297 static devclass_t xl_devclass;
298
299 DECLARE_DUMMY_MODULE(if_xl);
300 MODULE_DEPEND(if_xl, miibus, 1, 1, 1);
301 DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, NULL, NULL);
302 DRIVER_MODULE(if_xl, cardbus, xl_driver, xl_devclass, NULL, NULL);
303 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, NULL, NULL);
304
305 static void
xl_enable_intrs(struct xl_softc * sc,uint16_t intrs)306 xl_enable_intrs(struct xl_softc *sc, uint16_t intrs)
307 {
308 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK | 0xFF);
309 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB | intrs);
310 if (sc->xl_flags & XL_FLAG_FUNCREG)
311 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
312 sc->xl_npoll.ifpc_stcount = 0;
313 }
314
315 /*
316 * Murphy's law says that it's possible the chip can wedge and
317 * the 'command in progress' bit may never clear. Hence, we wait
318 * only a finite amount of time to avoid getting caught in an
319 * infinite loop. Normally this delay routine would be a macro,
320 * but it isn't called during normal operation so we can afford
321 * to make it a function.
322 */
323 static void
xl_wait(struct xl_softc * sc)324 xl_wait(struct xl_softc *sc)
325 {
326 int i;
327
328 for (i = 0; i < XL_TIMEOUT; i++) {
329 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
330 break;
331 }
332
333 if (i == XL_TIMEOUT)
334 if_printf(&sc->arpcom.ac_if, "command never completed!");
335
336 return;
337 }
338
339 /*
340 * MII access routines are provided for adapters with external
341 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
342 * autoneg logic that's faked up to look like a PHY (3c905B-TX).
343 * Note: if you don't perform the MDIO operations just right,
344 * it's possible to end up with code that works correctly with
345 * some chips/CPUs/processor speeds/bus speeds/etc but not
346 * with others.
347 */
348 #define MII_SET(x) \
349 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
350 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x))
351
352 #define MII_CLR(x) \
353 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
354 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x))
355
356 /*
357 * Sync the PHYs by setting data bit and strobing the clock 32 times.
358 */
359 static void
xl_mii_sync(struct xl_softc * sc)360 xl_mii_sync(struct xl_softc *sc)
361 {
362 int i;
363
364 XL_SEL_WIN(4);
365 MII_SET(XL_MII_DIR|XL_MII_DATA);
366
367 for (i = 0; i < 32; i++) {
368 MII_SET(XL_MII_CLK);
369 MII_SET(XL_MII_DATA);
370 MII_SET(XL_MII_DATA);
371 MII_CLR(XL_MII_CLK);
372 MII_SET(XL_MII_DATA);
373 MII_SET(XL_MII_DATA);
374 }
375
376 return;
377 }
378
379 /*
380 * Clock a series of bits through the MII.
381 */
382 static void
xl_mii_send(struct xl_softc * sc,u_int32_t bits,int cnt)383 xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt)
384 {
385 int i;
386
387 XL_SEL_WIN(4);
388 MII_CLR(XL_MII_CLK);
389
390 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
391 if (bits & i) {
392 MII_SET(XL_MII_DATA);
393 } else {
394 MII_CLR(XL_MII_DATA);
395 }
396 MII_CLR(XL_MII_CLK);
397 MII_SET(XL_MII_CLK);
398 }
399 }
400
401 /*
402 * Read an PHY register through the MII.
403 */
404 static int
xl_mii_readreg(struct xl_softc * sc,struct xl_mii_frame * frame)405 xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame)
406 {
407 int i, ack;
408
409 /*
410 * Set up frame for RX.
411 */
412 frame->mii_stdelim = XL_MII_STARTDELIM;
413 frame->mii_opcode = XL_MII_READOP;
414 frame->mii_turnaround = 0;
415 frame->mii_data = 0;
416
417 /*
418 * Select register window 4.
419 */
420
421 XL_SEL_WIN(4);
422
423 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0);
424 /*
425 * Turn on data xmit.
426 */
427 MII_SET(XL_MII_DIR);
428
429 xl_mii_sync(sc);
430
431 /*
432 * Send command/address info.
433 */
434 xl_mii_send(sc, frame->mii_stdelim, 2);
435 xl_mii_send(sc, frame->mii_opcode, 2);
436 xl_mii_send(sc, frame->mii_phyaddr, 5);
437 xl_mii_send(sc, frame->mii_regaddr, 5);
438
439 /* Idle bit */
440 MII_CLR((XL_MII_CLK|XL_MII_DATA));
441 MII_SET(XL_MII_CLK);
442
443 /* Turn off xmit. */
444 MII_CLR(XL_MII_DIR);
445
446 /* Check for ack */
447 MII_CLR(XL_MII_CLK);
448 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA;
449 MII_SET(XL_MII_CLK);
450
451 /*
452 * Now try reading data bits. If the ack failed, we still
453 * need to clock through 16 cycles to keep the PHY(s) in sync.
454 */
455 if (ack) {
456 for(i = 0; i < 16; i++) {
457 MII_CLR(XL_MII_CLK);
458 MII_SET(XL_MII_CLK);
459 }
460 goto fail;
461 }
462
463 for (i = 0x8000; i; i >>= 1) {
464 MII_CLR(XL_MII_CLK);
465 if (!ack) {
466 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA)
467 frame->mii_data |= i;
468 }
469 MII_SET(XL_MII_CLK);
470 }
471
472 fail:
473
474 MII_CLR(XL_MII_CLK);
475 MII_SET(XL_MII_CLK);
476
477 if (ack)
478 return(1);
479 return(0);
480 }
481
482 /*
483 * Write to a PHY register through the MII.
484 */
485 static int
xl_mii_writereg(struct xl_softc * sc,struct xl_mii_frame * frame)486 xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame)
487 {
488 /*
489 * Set up frame for TX.
490 */
491
492 frame->mii_stdelim = XL_MII_STARTDELIM;
493 frame->mii_opcode = XL_MII_WRITEOP;
494 frame->mii_turnaround = XL_MII_TURNAROUND;
495
496 /*
497 * Select the window 4.
498 */
499 XL_SEL_WIN(4);
500
501 /*
502 * Turn on data output.
503 */
504 MII_SET(XL_MII_DIR);
505
506 xl_mii_sync(sc);
507
508 xl_mii_send(sc, frame->mii_stdelim, 2);
509 xl_mii_send(sc, frame->mii_opcode, 2);
510 xl_mii_send(sc, frame->mii_phyaddr, 5);
511 xl_mii_send(sc, frame->mii_regaddr, 5);
512 xl_mii_send(sc, frame->mii_turnaround, 2);
513 xl_mii_send(sc, frame->mii_data, 16);
514
515 /* Idle bit. */
516 MII_SET(XL_MII_CLK);
517 MII_CLR(XL_MII_CLK);
518
519 /*
520 * Turn off xmit.
521 */
522 MII_CLR(XL_MII_DIR);
523
524 return(0);
525 }
526
527 static int
xl_miibus_readreg(device_t dev,int phy,int reg)528 xl_miibus_readreg(device_t dev, int phy, int reg)
529 {
530 struct xl_softc *sc;
531 struct xl_mii_frame frame;
532
533 sc = device_get_softc(dev);
534
535 /*
536 * Pretend that PHYs are only available at MII address 24.
537 * This is to guard against problems with certain 3Com ASIC
538 * revisions that incorrectly map the internal transceiver
539 * control registers at all MII addresses. This can cause
540 * the miibus code to attach the same PHY several times over.
541 */
542 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24)
543 return(0);
544
545 bzero((char *)&frame, sizeof(frame));
546
547 frame.mii_phyaddr = phy;
548 frame.mii_regaddr = reg;
549 xl_mii_readreg(sc, &frame);
550
551 return(frame.mii_data);
552 }
553
554 static int
xl_miibus_writereg(device_t dev,int phy,int reg,int data)555 xl_miibus_writereg(device_t dev, int phy, int reg, int data)
556 {
557 struct xl_softc *sc;
558 struct xl_mii_frame frame;
559
560 sc = device_get_softc(dev);
561
562 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24)
563 return(0);
564
565 bzero((char *)&frame, sizeof(frame));
566
567 frame.mii_phyaddr = phy;
568 frame.mii_regaddr = reg;
569 frame.mii_data = data;
570
571 xl_mii_writereg(sc, &frame);
572
573 return(0);
574 }
575
576 static void
xl_miibus_statchg(device_t dev)577 xl_miibus_statchg(device_t dev)
578 {
579 struct xl_softc *sc;
580 struct mii_data *mii;
581
582 sc = device_get_softc(dev);
583 mii = device_get_softc(sc->xl_miibus);
584
585 ASSERT_SERIALIZED(sc->arpcom.ac_if.if_serializer);
586
587 xl_setcfg(sc);
588
589 /* Set ASIC's duplex mode to match the PHY. */
590 XL_SEL_WIN(3);
591 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
592 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
593 else
594 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
595 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
596 }
597
598 /*
599 * Special support for the 3c905B-COMBO. This card has 10/100 support
600 * plus BNC and AUI ports. This means we will have both an miibus attached
601 * plus some non-MII media settings. In order to allow this, we have to
602 * add the extra media to the miibus's ifmedia struct, but we can't do
603 * that during xl_attach() because the miibus hasn't been attached yet.
604 * So instead, we wait until the miibus probe/attach is done, at which
605 * point we will get a callback telling is that it's safe to add our
606 * extra media.
607 */
608 static void
xl_miibus_mediainit(device_t dev)609 xl_miibus_mediainit(device_t dev)
610 {
611 struct xl_softc *sc;
612 struct mii_data *mii;
613 struct ifmedia *ifm;
614
615 sc = device_get_softc(dev);
616 mii = device_get_softc(sc->xl_miibus);
617 ifm = &mii->mii_media;
618
619 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
620 /*
621 * Check for a 10baseFL board in disguise.
622 */
623 if (sc->xl_type == XL_TYPE_905B &&
624 sc->xl_media == XL_MEDIAOPT_10FL) {
625 if (bootverbose)
626 device_printf(dev, "found 10baseFL\n");
627 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL);
628 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL);
629 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
630 ifmedia_add(ifm,
631 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
632 } else {
633 if (bootverbose)
634 device_printf(dev, "found AUI\n");
635 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL);
636 }
637 }
638
639 if (sc->xl_media & XL_MEDIAOPT_BNC) {
640 if (bootverbose)
641 device_printf(dev, "found BNC\n");
642 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL);
643 }
644
645 return;
646 }
647
648 /*
649 * The EEPROM is slow: give it time to come ready after issuing
650 * it a command.
651 */
652 static int
xl_eeprom_wait(struct xl_softc * sc)653 xl_eeprom_wait(struct xl_softc *sc)
654 {
655 int i;
656
657 for (i = 0; i < 100; i++) {
658 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
659 DELAY(162);
660 else
661 break;
662 }
663
664 if (i == 100) {
665 if_printf(&sc->arpcom.ac_if, "eeprom failed to come ready\n");
666 return(1);
667 }
668
669 return(0);
670 }
671
672 /*
673 * Read a sequence of words from the EEPROM. Note that ethernet address
674 * data is stored in the EEPROM in network byte order.
675 */
676 static int
xl_read_eeprom(struct xl_softc * sc,caddr_t dest,int off,int cnt,int swap)677 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap)
678 {
679 int err = 0, i;
680 u_int16_t word = 0, *ptr;
681 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
682 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
683 /* WARNING! DANGER!
684 * It's easy to accidentally overwrite the rom content!
685 * Note: the 3c575 uses 8bit EEPROM offsets.
686 */
687 XL_SEL_WIN(0);
688
689 if (xl_eeprom_wait(sc))
690 return(1);
691
692 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
693 off += 0x30;
694
695 for (i = 0; i < cnt; i++) {
696 if (sc->xl_flags & XL_FLAG_8BITROM)
697 CSR_WRITE_2(sc, XL_W0_EE_CMD,
698 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
699 else
700 CSR_WRITE_2(sc, XL_W0_EE_CMD,
701 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
702 err = xl_eeprom_wait(sc);
703 if (err)
704 break;
705 word = CSR_READ_2(sc, XL_W0_EE_DATA);
706 ptr = (u_int16_t *)(dest + (i * 2));
707 if (swap)
708 *ptr = ntohs(word);
709 else
710 *ptr = word;
711 }
712
713 return(err ? 1 : 0);
714 }
715
716 /*
717 * NICs older than the 3c905B have only one multicast option, which
718 * is to enable reception of all multicast frames.
719 */
720 static void
xl_setmulti(struct xl_softc * sc)721 xl_setmulti(struct xl_softc *sc)
722 {
723 struct ifnet *ifp;
724 struct ifmultiaddr *ifma;
725 u_int8_t rxfilt;
726 int mcnt = 0;
727
728 ifp = &sc->arpcom.ac_if;
729
730 XL_SEL_WIN(5);
731 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
732
733 if (ifp->if_flags & IFF_ALLMULTI) {
734 rxfilt |= XL_RXFILTER_ALLMULTI;
735 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
736 return;
737 }
738
739 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link)
740 mcnt++;
741
742 if (mcnt)
743 rxfilt |= XL_RXFILTER_ALLMULTI;
744 else
745 rxfilt &= ~XL_RXFILTER_ALLMULTI;
746
747 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
748
749 return;
750 }
751
752 /*
753 * 3c905B adapters have a hash filter that we can program.
754 */
755 static void
xl_setmulti_hash(struct xl_softc * sc)756 xl_setmulti_hash(struct xl_softc *sc)
757 {
758 struct ifnet *ifp;
759 int h = 0, i;
760 struct ifmultiaddr *ifma;
761 u_int8_t rxfilt;
762 int mcnt = 0;
763
764 ifp = &sc->arpcom.ac_if;
765
766 XL_SEL_WIN(5);
767 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
768
769 if (ifp->if_flags & IFF_ALLMULTI) {
770 rxfilt |= XL_RXFILTER_ALLMULTI;
771 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
772 return;
773 } else
774 rxfilt &= ~XL_RXFILTER_ALLMULTI;
775
776
777 /* first, zot all the existing hash bits */
778 for (i = 0; i < XL_HASHFILT_SIZE; i++)
779 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i);
780
781 /* now program new ones */
782 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
783 if (ifma->ifma_addr->sa_family != AF_LINK)
784 continue;
785
786 /*
787 * Note: the 3c905B currently only supports a 64-bit
788 * hash table, which means we really only need 6 bits,
789 * but the manual indicates that future chip revisions
790 * will have a 256-bit hash table, hence the routine is
791 * set up to calculate 8 bits of position info in case
792 * we need it some day.
793 * Note II, The Sequel: _CURRENT_ versions of the 3c905B
794 * have a 256 bit hash table. This means we have to use
795 * all 8 bits regardless. On older cards, the upper 2
796 * bits will be ignored. Grrrr....
797 */
798 h = ether_crc32_be(
799 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
800 ETHER_ADDR_LEN) & 0xff;
801 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h);
802 mcnt++;
803 }
804
805 if (mcnt)
806 rxfilt |= XL_RXFILTER_MULTIHASH;
807 else
808 rxfilt &= ~XL_RXFILTER_MULTIHASH;
809
810 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
811
812 return;
813 }
814
815 static void
xl_setcfg(struct xl_softc * sc)816 xl_setcfg(struct xl_softc *sc)
817 {
818 u_int32_t icfg;
819
820 XL_SEL_WIN(3);
821 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
822 icfg &= ~XL_ICFG_CONNECTOR_MASK;
823 if (sc->xl_media & XL_MEDIAOPT_MII ||
824 sc->xl_media & XL_MEDIAOPT_BT4)
825 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
826 if (sc->xl_media & XL_MEDIAOPT_BTX)
827 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
828
829 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
830 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
831
832 return;
833 }
834
835 static void
xl_setmode(struct xl_softc * sc,int media)836 xl_setmode(struct xl_softc *sc, int media)
837 {
838 struct ifnet *ifp = &sc->arpcom.ac_if;
839 u_int32_t icfg;
840 u_int16_t mediastat;
841
842 if_printf(ifp, "selecting ");
843
844 XL_SEL_WIN(4);
845 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
846 XL_SEL_WIN(3);
847 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
848
849 if (sc->xl_media & XL_MEDIAOPT_BT) {
850 if (IFM_SUBTYPE(media) == IFM_10_T) {
851 kprintf("10baseT transceiver, ");
852 sc->xl_xcvr = XL_XCVR_10BT;
853 icfg &= ~XL_ICFG_CONNECTOR_MASK;
854 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
855 mediastat |= XL_MEDIASTAT_LINKBEAT|
856 XL_MEDIASTAT_JABGUARD;
857 mediastat &= ~XL_MEDIASTAT_SQEENB;
858 }
859 }
860
861 if (sc->xl_media & XL_MEDIAOPT_BFX) {
862 if (IFM_SUBTYPE(media) == IFM_100_FX) {
863 kprintf("100baseFX port, ");
864 sc->xl_xcvr = XL_XCVR_100BFX;
865 icfg &= ~XL_ICFG_CONNECTOR_MASK;
866 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
867 mediastat |= XL_MEDIASTAT_LINKBEAT;
868 mediastat &= ~XL_MEDIASTAT_SQEENB;
869 }
870 }
871
872 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
873 if (IFM_SUBTYPE(media) == IFM_10_5) {
874 kprintf("AUI port, ");
875 sc->xl_xcvr = XL_XCVR_AUI;
876 icfg &= ~XL_ICFG_CONNECTOR_MASK;
877 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
878 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
879 XL_MEDIASTAT_JABGUARD);
880 mediastat |= ~XL_MEDIASTAT_SQEENB;
881 }
882 if (IFM_SUBTYPE(media) == IFM_10_FL) {
883 kprintf("10baseFL transceiver, ");
884 sc->xl_xcvr = XL_XCVR_AUI;
885 icfg &= ~XL_ICFG_CONNECTOR_MASK;
886 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
887 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
888 XL_MEDIASTAT_JABGUARD);
889 mediastat |= ~XL_MEDIASTAT_SQEENB;
890 }
891 }
892
893 if (sc->xl_media & XL_MEDIAOPT_BNC) {
894 if (IFM_SUBTYPE(media) == IFM_10_2) {
895 kprintf("BNC port, ");
896 sc->xl_xcvr = XL_XCVR_COAX;
897 icfg &= ~XL_ICFG_CONNECTOR_MASK;
898 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
899 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
900 XL_MEDIASTAT_JABGUARD|
901 XL_MEDIASTAT_SQEENB);
902 }
903 }
904
905 if ((media & IFM_GMASK) == IFM_FDX ||
906 IFM_SUBTYPE(media) == IFM_100_FX) {
907 kprintf("full duplex\n");
908 XL_SEL_WIN(3);
909 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
910 } else {
911 kprintf("half duplex\n");
912 XL_SEL_WIN(3);
913 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
914 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
915 }
916
917 if (IFM_SUBTYPE(media) == IFM_10_2)
918 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
919 else
920 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
921 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
922 XL_SEL_WIN(4);
923 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
924 DELAY(800);
925 XL_SEL_WIN(7);
926 }
927
928 static void
xl_reset(struct xl_softc * sc)929 xl_reset(struct xl_softc *sc)
930 {
931 int i;
932
933 XL_SEL_WIN(0);
934 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
935 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
936 XL_RESETOPT_DISADVFD:0));
937
938 /*
939 * If we're using memory mapped register mode, pause briefly
940 * after issuing the reset command before trying to access any
941 * other registers. With my 3c575C cardbus card, failing to do
942 * this results in the system locking up while trying to poll
943 * the command busy bit in the status register.
944 */
945 if (sc->xl_flags & XL_FLAG_USE_MMIO)
946 DELAY(100000);
947
948 for (i = 0; i < XL_TIMEOUT; i++) {
949 DELAY(10);
950 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
951 break;
952 }
953
954 if (i == XL_TIMEOUT)
955 if_printf(&sc->arpcom.ac_if, "reset didn't complete\n");
956
957 /* Reset TX and RX. */
958 /* Note: the RX reset takes an absurd amount of time
959 * on newer versions of the Tornado chips such as those
960 * on the 3c905CX and newer 3c908C cards. We wait an
961 * extra amount of time so that xl_wait() doesn't complain
962 * and annoy the users.
963 */
964 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
965 DELAY(100000);
966 xl_wait(sc);
967 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
968 xl_wait(sc);
969
970 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
971 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
972 XL_SEL_WIN(2);
973 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc,
974 XL_W2_RESET_OPTIONS)
975 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0)
976 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0)
977 );
978 }
979
980 /* Wait a little while for the chip to get its brains in order. */
981 DELAY(100000);
982 return;
983 }
984
985 /*
986 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
987 * IDs against our list and return a device name if we find a match.
988 */
989 static int
xl_probe(device_t dev)990 xl_probe(device_t dev)
991 {
992 struct xl_type *t;
993 uint16_t vid, did;
994
995 vid = pci_get_vendor(dev);
996 did = pci_get_device(dev);
997 for (t = xl_devs; t->xl_name != NULL; t++) {
998 if (vid == t->xl_vid && did == t->xl_did) {
999 device_set_desc(dev, t->xl_name);
1000 return(0);
1001 }
1002 }
1003 return(ENXIO);
1004 }
1005
1006 /*
1007 * This routine is a kludge to work around possible hardware faults
1008 * or manufacturing defects that can cause the media options register
1009 * (or reset options register, as it's called for the first generation
1010 * 3c90x adapters) to return an incorrect result. I have encountered
1011 * one Dell Latitude laptop docking station with an integrated 3c905-TX
1012 * which doesn't have any of the 'mediaopt' bits set. This screws up
1013 * the attach routine pretty badly because it doesn't know what media
1014 * to look for. If we find ourselves in this predicament, this routine
1015 * will try to guess the media options values and warn the user of a
1016 * possible manufacturing defect with his adapter/system/whatever.
1017 */
1018 static void
xl_mediacheck(struct xl_softc * sc)1019 xl_mediacheck(struct xl_softc *sc)
1020 {
1021 struct ifnet *ifp = &sc->arpcom.ac_if;
1022
1023 /*
1024 * If some of the media options bits are set, assume they are
1025 * correct. If not, try to figure it out down below.
1026 * XXX I should check for 10baseFL, but I don't have an adapter
1027 * to test with.
1028 */
1029 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
1030 /*
1031 * Check the XCVR value. If it's not in the normal range
1032 * of values, we need to fake it up here.
1033 */
1034 if (sc->xl_xcvr <= XL_XCVR_AUTO)
1035 return;
1036 else {
1037 if_printf(ifp, "bogus xcvr value in EEPROM (%x)\n",
1038 sc->xl_xcvr);
1039 if_printf(ifp,
1040 "choosing new default based on card type\n");
1041 }
1042 } else {
1043 if (sc->xl_type == XL_TYPE_905B &&
1044 sc->xl_media & XL_MEDIAOPT_10FL)
1045 return;
1046 if_printf(ifp, "WARNING: no media options bits set in "
1047 "the media options register!!\n");
1048 if_printf(ifp, "this could be a manufacturing defect in "
1049 "your adapter or system\n");
1050 if_printf(ifp, "attempting to guess media type; you "
1051 "should probably consult your vendor\n");
1052 }
1053
1054 xl_choose_xcvr(sc, 1);
1055 }
1056
1057 static void
xl_choose_xcvr(struct xl_softc * sc,int verbose)1058 xl_choose_xcvr(struct xl_softc *sc, int verbose)
1059 {
1060 struct ifnet *ifp = &sc->arpcom.ac_if;
1061 u_int16_t devid;
1062
1063 /*
1064 * Read the device ID from the EEPROM.
1065 * This is what's loaded into the PCI device ID register, so it has
1066 * to be correct otherwise we wouldn't have gotten this far.
1067 */
1068 devid = 0; /* silence gcc warnings */
1069 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
1070
1071 switch(devid) {
1072 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */
1073 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */
1074 sc->xl_media = XL_MEDIAOPT_BT;
1075 sc->xl_xcvr = XL_XCVR_10BT;
1076 if (verbose)
1077 if_printf(ifp, "guessing 10BaseT transceiver\n");
1078 break;
1079 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */
1080 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */
1081 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1082 sc->xl_xcvr = XL_XCVR_10BT;
1083 if (verbose)
1084 if_printf(ifp, "guessing COMBO (AUI/BNC/TP)\n");
1085 break;
1086 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */
1087 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
1088 sc->xl_xcvr = XL_XCVR_10BT;
1089 if (verbose)
1090 if_printf(ifp, "guessing TPC (BNC/TP)\n");
1091 break;
1092 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */
1093 sc->xl_media = XL_MEDIAOPT_10FL;
1094 sc->xl_xcvr = XL_XCVR_AUI;
1095 if (verbose)
1096 if_printf(ifp, "guessing 10baseFL\n");
1097 break;
1098 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1099 case TC_DEVICEID_HURRICANE_555: /* 3c555 */
1100 case TC_DEVICEID_HURRICANE_556: /* 3c556 */
1101 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */
1102 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */
1103 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */
1104 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */
1105 case TC_DEVICEID_HURRICANE_656: /* 3c656 */
1106 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */
1107 case TC_DEVICEID_TORNADO_656C: /* 3c656C */
1108 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */
1109 sc->xl_media = XL_MEDIAOPT_MII;
1110 sc->xl_xcvr = XL_XCVR_MII;
1111 if (verbose)
1112 if_printf(ifp, "guessing MII\n");
1113 break;
1114 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */
1115 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */
1116 sc->xl_media = XL_MEDIAOPT_BT4;
1117 sc->xl_xcvr = XL_XCVR_MII;
1118 if (verbose)
1119 if_printf(ifp, "guessing 100BaseT4/MII\n");
1120 break;
1121 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */
1122 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1123 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */
1124 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */
1125 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */
1126 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */
1127 sc->xl_media = XL_MEDIAOPT_BTX;
1128 sc->xl_xcvr = XL_XCVR_AUTO;
1129 if (verbose)
1130 if_printf(ifp, "guessing 10/100 internal\n");
1131 break;
1132 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */
1133 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1134 sc->xl_xcvr = XL_XCVR_AUTO;
1135 if (verbose)
1136 if_printf(ifp, "guessing 10/100 plus BNC/AUI\n");
1137 break;
1138 default:
1139 if_printf(ifp,
1140 "unknown device ID: %x -- defaulting to 10baseT\n", devid);
1141 sc->xl_media = XL_MEDIAOPT_BT;
1142 break;
1143 }
1144
1145 return;
1146 }
1147
1148 /*
1149 * Attach the interface. Allocate softc structures, do ifmedia
1150 * setup and ethernet/BPF attach.
1151 */
1152 static int
xl_attach(device_t dev)1153 xl_attach(device_t dev)
1154 {
1155 u_char eaddr[ETHER_ADDR_LEN];
1156 u_int16_t xcvr[2];
1157 struct xl_softc *sc;
1158 struct ifnet *ifp;
1159 int media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1160 int error = 0, rid, res;
1161 uint16_t did;
1162
1163 sc = device_get_softc(dev);
1164
1165 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1166
1167 did = pci_get_device(dev);
1168
1169 sc->xl_flags = 0;
1170 if (did == TC_DEVICEID_HURRICANE_555)
1171 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK;
1172 if (did == TC_DEVICEID_HURRICANE_556 ||
1173 did == TC_DEVICEID_HURRICANE_556B)
1174 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1175 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
1176 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
1177 if (did == TC_DEVICEID_HURRICANE_555 ||
1178 did == TC_DEVICEID_HURRICANE_556)
1179 sc->xl_flags |= XL_FLAG_8BITROM;
1180 if (did == TC_DEVICEID_HURRICANE_556B)
1181 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR;
1182 if (did == TC_DEVICEID_HURRICANE_575B ||
1183 did == TC_DEVICEID_HURRICANE_575C ||
1184 did == TC_DEVICEID_HURRICANE_656B ||
1185 did == TC_DEVICEID_TORNADO_656C)
1186 sc->xl_flags |= XL_FLAG_FUNCREG;
1187 if (did == TC_DEVICEID_HURRICANE_575A ||
1188 did == TC_DEVICEID_HURRICANE_575B ||
1189 did == TC_DEVICEID_HURRICANE_575C ||
1190 did == TC_DEVICEID_HURRICANE_656B ||
1191 did == TC_DEVICEID_TORNADO_656C)
1192 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 |
1193 XL_FLAG_8BITROM;
1194 if (did == TC_DEVICEID_HURRICANE_656)
1195 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK;
1196 if (did == TC_DEVICEID_HURRICANE_575B)
1197 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1198 if (did == TC_DEVICEID_HURRICANE_575C)
1199 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1200 if (did == TC_DEVICEID_TORNADO_656C)
1201 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1202 if (did == TC_DEVICEID_HURRICANE_656 ||
1203 did == TC_DEVICEID_HURRICANE_656B)
1204 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR |
1205 XL_FLAG_INVERT_LED_PWR;
1206 if (did == TC_DEVICEID_TORNADO_10_100BT_920B)
1207 sc->xl_flags |= XL_FLAG_PHYOK;
1208 #ifndef BURN_BRIDGES
1209 /*
1210 * If this is a 3c905B, we have to check one extra thing.
1211 * The 905B supports power management and may be placed in
1212 * a low-power mode (D3 mode), typically by certain operating
1213 * systems which shall not be named. The PCI BIOS is supposed
1214 * to reset the NIC and bring it out of low-power mode, but
1215 * some do not. Consequently, we have to see if this chip
1216 * supports power management, and if so, make sure it's not
1217 * in low-power mode. If power management is available, the
1218 * capid byte will be 0x01.
1219 *
1220 * I _think_ that what actually happens is that the chip
1221 * loses its PCI configuration during the transition from
1222 * D3 back to D0; this means that it should be possible for
1223 * us to save the PCI iobase, membase and IRQ, put the chip
1224 * back in the D0 state, then restore the PCI config ourselves.
1225 */
1226
1227 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1228 u_int32_t iobase, membase, irq;
1229
1230 /* Save important PCI config data. */
1231 iobase = pci_read_config(dev, XL_PCI_LOIO, 4);
1232 membase = pci_read_config(dev, XL_PCI_LOMEM, 4);
1233 irq = pci_read_config(dev, XL_PCI_INTLINE, 4);
1234
1235 /* Reset the power state. */
1236 device_printf(dev, "chip is in D%d power mode "
1237 "-- setting to D0\n", pci_get_powerstate(dev));
1238
1239 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1240
1241 /* Restore PCI config data. */
1242 pci_write_config(dev, XL_PCI_LOIO, iobase, 4);
1243 pci_write_config(dev, XL_PCI_LOMEM, membase, 4);
1244 pci_write_config(dev, XL_PCI_INTLINE, irq, 4);
1245 }
1246 #endif
1247 /*
1248 * Map control/status registers.
1249 */
1250 pci_enable_busmaster(dev);
1251
1252 rid = XL_PCI_LOMEM;
1253 res = SYS_RES_MEMORY;
1254
1255 #if 0
1256 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1257 #endif
1258
1259 if (sc->xl_res != NULL) {
1260 sc->xl_flags |= XL_FLAG_USE_MMIO;
1261 if (bootverbose)
1262 device_printf(dev, "using memory mapped I/O\n");
1263 } else {
1264 rid = XL_PCI_LOIO;
1265 res = SYS_RES_IOPORT;
1266 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1267 if (sc->xl_res == NULL) {
1268 device_printf(dev, "couldn't map ports/memory\n");
1269 error = ENXIO;
1270 goto fail;
1271 }
1272 if (bootverbose)
1273 device_printf(dev, "using port I/O\n");
1274 }
1275
1276 sc->xl_btag = rman_get_bustag(sc->xl_res);
1277 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1278
1279 if (sc->xl_flags & XL_FLAG_FUNCREG) {
1280 rid = XL_PCI_FUNCMEM;
1281 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1282 RF_ACTIVE);
1283
1284 if (sc->xl_fres == NULL) {
1285 device_printf(dev, "couldn't map funcreg memory\n");
1286 error = ENXIO;
1287 goto fail;
1288 }
1289
1290 sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1291 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1292 }
1293
1294 /* Allocate interrupt */
1295 rid = 0;
1296 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1297 RF_SHAREABLE | RF_ACTIVE);
1298 if (sc->xl_irq == NULL) {
1299 device_printf(dev, "couldn't map interrupt\n");
1300 error = ENXIO;
1301 goto fail;
1302 }
1303
1304 ifp = &sc->arpcom.ac_if;
1305 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1306
1307 /* Reset the adapter. */
1308 xl_reset(sc);
1309
1310 /*
1311 * Get station address from the EEPROM.
1312 */
1313 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1314 device_printf(dev, "failed to read station address\n");
1315 error = ENXIO;
1316 goto fail;
1317 }
1318
1319 callout_init(&sc->xl_stat_timer);
1320
1321 error = xl_dma_alloc(dev);
1322 if (error)
1323 goto fail;
1324
1325 /*
1326 * Figure out the card type. 3c905B adapters have the
1327 * 'supportsNoTxLength' bit set in the capabilities
1328 * word in the EEPROM.
1329 * Note: my 3c575C cardbus card lies. It returns a value
1330 * of 0x1578 for its capabilities word, which is somewhat
1331 * nonsensical. Another way to distinguish a 3c90x chip
1332 * from a 3c90xB/C chip is to check for the 'supportsLargePackets'
1333 * bit. This will only be set for 3c90x boomerage chips.
1334 */
1335 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1336 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH ||
1337 !(sc->xl_caps & XL_CAPS_LARGE_PKTS))
1338 sc->xl_type = XL_TYPE_905B;
1339 else
1340 sc->xl_type = XL_TYPE_90X;
1341 if (bootverbose) {
1342 device_printf(dev, "type %s\n",
1343 sc->xl_type == XL_TYPE_905B ? "90XB" : "90X");
1344 }
1345
1346 ifp->if_softc = sc;
1347 ifp->if_mtu = ETHERMTU;
1348 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1349 ifp->if_ioctl = xl_ioctl;
1350 if (sc->xl_type == XL_TYPE_905B) {
1351 ifp->if_start = xl_start_90xB;
1352 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_VLAN_MTU;
1353 } else {
1354 ifp->if_start = xl_start;
1355 }
1356 ifp->if_watchdog = xl_watchdog;
1357 ifp->if_init = xl_init;
1358 #ifdef IFPOLL_ENABLE
1359 ifp->if_npoll = xl_npoll;
1360 #endif
1361 ifp->if_baudrate = 10000000;
1362 ifq_set_maxlen(&ifp->if_snd, XL_TX_LIST_CNT - 1);
1363 ifq_set_ready(&ifp->if_snd);
1364 /*
1365 * NOTE: Hardware checksum features disabled by default.
1366 * This seems to corrupt tx packet data one out of a
1367 * million packets or so and then generates a good checksum
1368 * so the receiver doesn't know the packet is bad
1369 */
1370 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM;
1371 if (ifp->if_capenable & IFCAP_TXCSUM)
1372 ifp->if_hwassist = XL905B_CSUM_FEATURES;
1373
1374 /*
1375 * Now we have to see what sort of media we have.
1376 * This includes probing for an MII interace and a
1377 * possible PHY.
1378 */
1379 XL_SEL_WIN(3);
1380 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1381 if (bootverbose)
1382 if_printf(ifp, "media options word: %x\n", sc->xl_media);
1383
1384 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
1385 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
1386 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1387 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1388
1389 xl_mediacheck(sc);
1390
1391 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
1392 || sc->xl_media & XL_MEDIAOPT_BT4) {
1393 if (bootverbose)
1394 if_printf(ifp, "found MII/AUTO\n");
1395 xl_setcfg(sc);
1396
1397 error = mii_phy_probe(dev, &sc->xl_miibus,
1398 xl_ifmedia_upd, xl_ifmedia_sts);
1399 if (error) {
1400 if_printf(ifp, "no PHY found!\n");
1401 goto fail;
1402 }
1403
1404 goto done;
1405 }
1406
1407 /*
1408 * Sanity check. If the user has selected "auto" and this isn't
1409 * a 10/100 card of some kind, we need to force the transceiver
1410 * type to something sane.
1411 */
1412 if (sc->xl_xcvr == XL_XCVR_AUTO)
1413 xl_choose_xcvr(sc, bootverbose);
1414
1415 /*
1416 * Do ifmedia setup.
1417 */
1418 if (sc->xl_media & XL_MEDIAOPT_BT) {
1419 if (bootverbose)
1420 if_printf(ifp, "found 10baseT\n");
1421 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1422 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1423 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1424 ifmedia_add(&sc->ifmedia,
1425 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1426 }
1427
1428 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1429 /*
1430 * Check for a 10baseFL board in disguise.
1431 */
1432 if (sc->xl_type == XL_TYPE_905B &&
1433 sc->xl_media == XL_MEDIAOPT_10FL) {
1434 if (bootverbose)
1435 if_printf(ifp, "found 10baseFL\n");
1436 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1437 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1438 0, NULL);
1439 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1440 ifmedia_add(&sc->ifmedia,
1441 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1442 } else {
1443 if (bootverbose)
1444 if_printf(ifp, "found AUI\n");
1445 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1446 }
1447 }
1448
1449 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1450 if (bootverbose)
1451 if_printf(ifp, "found BNC\n");
1452 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1453 }
1454
1455 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1456 if (bootverbose)
1457 if_printf(ifp, "found 100baseFX\n");
1458 ifp->if_baudrate = 100000000;
1459 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1460 }
1461
1462 /* Choose a default media. */
1463 switch(sc->xl_xcvr) {
1464 case XL_XCVR_10BT:
1465 media = IFM_ETHER|IFM_10_T;
1466 xl_setmode(sc, media);
1467 break;
1468 case XL_XCVR_AUI:
1469 if (sc->xl_type == XL_TYPE_905B &&
1470 sc->xl_media == XL_MEDIAOPT_10FL) {
1471 media = IFM_ETHER|IFM_10_FL;
1472 xl_setmode(sc, media);
1473 } else {
1474 media = IFM_ETHER|IFM_10_5;
1475 xl_setmode(sc, media);
1476 }
1477 break;
1478 case XL_XCVR_COAX:
1479 media = IFM_ETHER|IFM_10_2;
1480 xl_setmode(sc, media);
1481 break;
1482 case XL_XCVR_AUTO:
1483 case XL_XCVR_100BTX:
1484 case XL_XCVR_MII:
1485 /* Chosen by miibus */
1486 break;
1487 case XL_XCVR_100BFX:
1488 media = IFM_ETHER|IFM_100_FX;
1489 break;
1490 default:
1491 if_printf(ifp, "unknown XCVR type: %d\n", sc->xl_xcvr);
1492 /*
1493 * This will probably be wrong, but it prevents
1494 * the ifmedia code from panicking.
1495 */
1496 media = IFM_ETHER|IFM_10_T;
1497 break;
1498 }
1499
1500 if (sc->xl_miibus == NULL)
1501 ifmedia_set(&sc->ifmedia, media);
1502
1503 done:
1504
1505 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
1506 XL_SEL_WIN(0);
1507 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
1508 }
1509
1510 /*
1511 * Call MI attach routine.
1512 */
1513 ether_ifattach(ifp, eaddr, NULL);
1514
1515 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->xl_irq));
1516
1517 #ifdef IFPOLL_ENABLE
1518 ifpoll_compat_setup(&sc->xl_npoll, NULL, NULL, device_get_unit(dev),
1519 ifp->if_serializer);
1520 #endif
1521
1522 /*
1523 * Tell the upper layer(s) we support long frames.
1524 */
1525 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1526
1527 /* Hook interrupt last to avoid having to lock softc */
1528 error = bus_setup_intr(dev, sc->xl_irq, INTR_MPSAFE,
1529 xl_intr, sc, &sc->xl_intrhand,
1530 ifp->if_serializer);
1531 if (error) {
1532 if_printf(ifp, "couldn't set up irq\n");
1533 ether_ifdetach(ifp);
1534 goto fail;
1535 }
1536
1537 return 0;
1538
1539 fail:
1540 xl_detach(dev);
1541 return error;
1542 }
1543
1544 /*
1545 * Shutdown hardware and free up resources. This can be called any
1546 * time after the mutex has been initialized. It is called in both
1547 * the error case in attach and the normal detach case so it needs
1548 * to be careful about only freeing resources that have actually been
1549 * allocated.
1550 */
1551 static int
xl_detach(device_t dev)1552 xl_detach(device_t dev)
1553 {
1554 struct xl_softc *sc;
1555 struct ifnet *ifp;
1556 int rid, res;
1557
1558 sc = device_get_softc(dev);
1559 ifp = &sc->arpcom.ac_if;
1560
1561 if (sc->xl_flags & XL_FLAG_USE_MMIO) {
1562 rid = XL_PCI_LOMEM;
1563 res = SYS_RES_MEMORY;
1564 } else {
1565 rid = XL_PCI_LOIO;
1566 res = SYS_RES_IOPORT;
1567 }
1568
1569 if (device_is_attached(dev)) {
1570 lwkt_serialize_enter(ifp->if_serializer);
1571 xl_reset(sc);
1572 xl_stop(sc);
1573 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1574 lwkt_serialize_exit(ifp->if_serializer);
1575
1576 ether_ifdetach(ifp);
1577 }
1578
1579 if (sc->xl_miibus)
1580 device_delete_child(dev, sc->xl_miibus);
1581 bus_generic_detach(dev);
1582 ifmedia_removeall(&sc->ifmedia);
1583
1584 if (sc->xl_irq)
1585 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1586 if (sc->xl_fres != NULL)
1587 bus_release_resource(dev, SYS_RES_MEMORY,
1588 XL_PCI_FUNCMEM, sc->xl_fres);
1589 if (sc->xl_res)
1590 bus_release_resource(dev, res, rid, sc->xl_res);
1591
1592 xl_dma_free(dev);
1593
1594 return(0);
1595 }
1596
1597 static int
xl_dma_alloc(device_t dev)1598 xl_dma_alloc(device_t dev)
1599 {
1600 struct xl_softc *sc;
1601 struct xl_chain_data *cd;
1602 struct xl_list_data *ld;
1603 bus_dmamem_t dmem;
1604 int i, error;
1605
1606 sc = device_get_softc(dev);
1607 cd = &sc->xl_cdata;
1608 ld = &sc->xl_ldata;
1609
1610 /*
1611 * Allocate the parent bus DMA tag appropriate for PCI.
1612 */
1613 error = bus_dma_tag_create(NULL, 1, 0,
1614 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1615 BUS_SPACE_MAXSIZE_32BIT, 0,
1616 BUS_SPACE_MAXSIZE_32BIT,
1617 0, &sc->xl_parent_tag);
1618 if (error) {
1619 device_printf(dev, "could not allocate parent dma tag\n");
1620 return error;
1621 }
1622
1623 /*
1624 * Now allocate a tag for the DMA descriptor lists and a chunk
1625 * of DMA-able memory based on the tag. Also obtain the DMA
1626 * addresses of the RX and TX ring, which we'll need later.
1627 * All of our lists are allocated as a contiguous block
1628 * of memory.
1629 */
1630 error = bus_dmamem_coherent(sc->xl_parent_tag, XL_LIST_ALIGN, 0,
1631 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1632 XL_RX_LIST_SZ, BUS_DMA_WAITOK, &dmem);
1633 if (error) {
1634 device_printf(dev, "failed to allocate rx list\n");
1635 return error;
1636 }
1637 ld->xl_rx_tag = dmem.dmem_tag;
1638 ld->xl_rx_dmamap = dmem.dmem_map;
1639 ld->xl_rx_list = dmem.dmem_addr;
1640 ld->xl_rx_dmaaddr = dmem.dmem_busaddr;
1641
1642 error = bus_dmamem_coherent(sc->xl_parent_tag, XL_LIST_ALIGN, 0,
1643 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1644 XL_TX_LIST_SZ, BUS_DMA_WAITOK, &dmem);
1645 if (error) {
1646 device_printf(dev, "failed to allocate tx list\n");
1647 return error;
1648 }
1649 ld->xl_tx_tag = dmem.dmem_tag;
1650 ld->xl_tx_dmamap = dmem.dmem_map;
1651 ld->xl_tx_list = dmem.dmem_addr;
1652 ld->xl_tx_dmaaddr = dmem.dmem_busaddr;
1653
1654 /*
1655 * Allocate a DMA tag for the mapping of mbufs.
1656 */
1657 error = bus_dma_tag_create(sc->xl_parent_tag, 1, 0,
1658 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1659 MCLBYTES, 1, MCLBYTES,
1660 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW,
1661 &sc->xl_rx_mtag);
1662 if (error) {
1663 device_printf(dev, "failed to allocate RX mbuf dma tag\n");
1664 return error;
1665 }
1666
1667 /*
1668 * Allocate a spare DMA map for the RX ring.
1669 */
1670 error = bus_dmamap_create(sc->xl_rx_mtag, BUS_DMA_WAITOK,
1671 &sc->xl_tmpmap);
1672 if (error) {
1673 device_printf(dev, "failed to create RX mbuf tmp dma map\n");
1674 bus_dma_tag_destroy(sc->xl_rx_mtag);
1675 sc->xl_rx_mtag = NULL;
1676 return error;
1677 }
1678
1679 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1680 error = bus_dmamap_create(sc->xl_rx_mtag, BUS_DMA_WAITOK,
1681 &cd->xl_rx_chain[i].xl_map);
1682 if (error) {
1683 device_printf(dev, "failed to create %dth "
1684 "rx descriptor dma map!\n", i);
1685 return error;
1686 }
1687 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i];
1688 }
1689
1690 error = bus_dma_tag_create(sc->xl_parent_tag, 1, 0,
1691 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1692 MCLBYTES, XL_MAXFRAGS, MCLBYTES,
1693 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
1694 &sc->xl_tx_mtag);
1695 if (error) {
1696 device_printf(dev, "failed to allocate TX mbuf dma tag\n");
1697 return error;
1698 }
1699
1700 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1701 error = bus_dmamap_create(sc->xl_tx_mtag, BUS_DMA_WAITOK,
1702 &cd->xl_tx_chain[i].xl_map);
1703 if (error) {
1704 device_printf(dev, "failed to create %dth "
1705 "tx descriptor dma map!\n", i);
1706 return error;
1707 }
1708 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1709 }
1710 return 0;
1711 }
1712
1713 static void
xl_dma_free(device_t dev)1714 xl_dma_free(device_t dev)
1715 {
1716 struct xl_softc *sc;
1717 struct xl_chain_data *cd;
1718 struct xl_list_data *ld;
1719 int i;
1720
1721 sc = device_get_softc(dev);
1722 cd = &sc->xl_cdata;
1723 ld = &sc->xl_ldata;
1724
1725 for (i = 0; i < XL_RX_LIST_CNT; ++i) {
1726 if (cd->xl_rx_chain[i].xl_ptr != NULL) {
1727 if (cd->xl_rx_chain[i].xl_mbuf != NULL) {
1728 bus_dmamap_unload(sc->xl_rx_mtag,
1729 cd->xl_rx_chain[i].xl_map);
1730 m_freem(cd->xl_rx_chain[i].xl_mbuf);
1731 }
1732 bus_dmamap_destroy(sc->xl_rx_mtag,
1733 cd->xl_rx_chain[i].xl_map);
1734 }
1735 }
1736
1737 for (i = 0; i < XL_TX_LIST_CNT; ++i) {
1738 if (cd->xl_tx_chain[i].xl_ptr != NULL) {
1739 if (cd->xl_tx_chain[i].xl_mbuf != NULL) {
1740 bus_dmamap_unload(sc->xl_tx_mtag,
1741 cd->xl_tx_chain[i].xl_map);
1742 m_freem(cd->xl_tx_chain[i].xl_mbuf);
1743 }
1744 bus_dmamap_destroy(sc->xl_tx_mtag,
1745 cd->xl_tx_chain[i].xl_map);
1746 }
1747 }
1748
1749 if (ld->xl_rx_tag) {
1750 bus_dmamap_unload(ld->xl_rx_tag, ld->xl_rx_dmamap);
1751 bus_dmamem_free(ld->xl_rx_tag, ld->xl_rx_list,
1752 ld->xl_rx_dmamap);
1753 bus_dma_tag_destroy(ld->xl_rx_tag);
1754 }
1755
1756 if (ld->xl_tx_tag) {
1757 bus_dmamap_unload(ld->xl_tx_tag, ld->xl_tx_dmamap);
1758 bus_dmamem_free(ld->xl_tx_tag, ld->xl_tx_list,
1759 ld->xl_tx_dmamap);
1760 bus_dma_tag_destroy(ld->xl_tx_tag);
1761 }
1762
1763 if (sc->xl_rx_mtag) {
1764 bus_dmamap_destroy(sc->xl_rx_mtag, sc->xl_tmpmap);
1765 bus_dma_tag_destroy(sc->xl_rx_mtag);
1766 }
1767 if (sc->xl_tx_mtag)
1768 bus_dma_tag_destroy(sc->xl_tx_mtag);
1769
1770 if (sc->xl_parent_tag)
1771 bus_dma_tag_destroy(sc->xl_parent_tag);
1772 }
1773
1774 /*
1775 * Initialize the transmit descriptors.
1776 */
1777 static void
xl_list_tx_init(struct xl_softc * sc)1778 xl_list_tx_init(struct xl_softc *sc)
1779 {
1780 struct xl_chain_data *cd;
1781 struct xl_list_data *ld;
1782 int i;
1783
1784 cd = &sc->xl_cdata;
1785 ld = &sc->xl_ldata;
1786 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1787 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1788 i * sizeof(struct xl_list);
1789 if (i == (XL_TX_LIST_CNT - 1))
1790 cd->xl_tx_chain[i].xl_next = NULL;
1791 else
1792 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1793 }
1794
1795 cd->xl_tx_free = &cd->xl_tx_chain[0];
1796 cd->xl_tx_tail = cd->xl_tx_head = NULL;
1797 }
1798
1799 /*
1800 * Initialize the transmit descriptors.
1801 */
1802 static void
xl_list_tx_init_90xB(struct xl_softc * sc)1803 xl_list_tx_init_90xB(struct xl_softc *sc)
1804 {
1805 struct xl_chain_data *cd;
1806 struct xl_list_data *ld;
1807 int i;
1808
1809 cd = &sc->xl_cdata;
1810 ld = &sc->xl_ldata;
1811 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1812 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1813 i * sizeof(struct xl_list);
1814 if (i == (XL_TX_LIST_CNT - 1))
1815 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1816 else
1817 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1818 if (i == 0) {
1819 cd->xl_tx_chain[i].xl_prev =
1820 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1821 } else {
1822 cd->xl_tx_chain[i].xl_prev =
1823 &cd->xl_tx_chain[i - 1];
1824 }
1825 }
1826
1827 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY);
1828
1829 cd->xl_tx_prod = 1;
1830 cd->xl_tx_cons = 1;
1831 cd->xl_tx_cnt = 0;
1832 }
1833
1834 /*
1835 * Initialize the RX descriptors and allocate mbufs for them. Note that
1836 * we arrange the descriptors in a closed ring, so that the last descriptor
1837 * points back to the first.
1838 */
1839 static int
xl_list_rx_init(struct xl_softc * sc)1840 xl_list_rx_init(struct xl_softc *sc)
1841 {
1842 struct xl_chain_data *cd;
1843 struct xl_list_data *ld;
1844 int error, i, next;
1845 u_int32_t nextptr;
1846
1847 cd = &sc->xl_cdata;
1848 ld = &sc->xl_ldata;
1849
1850 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1851 error = xl_newbuf(sc, &cd->xl_rx_chain[i], 1);
1852 if (error)
1853 return(error);
1854 if (i == (XL_RX_LIST_CNT - 1))
1855 next = 0;
1856 else
1857 next = i + 1;
1858 nextptr = ld->xl_rx_dmaaddr +
1859 next * sizeof(struct xl_list_onefrag);
1860 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next];
1861 ld->xl_rx_list[i].xl_next = htole32(nextptr);
1862 }
1863
1864 cd->xl_rx_head = &cd->xl_rx_chain[0];
1865
1866 return(0);
1867 }
1868
1869 /*
1870 * Initialize an RX descriptor and attach an MBUF cluster.
1871 * If we fail to do so, we need to leave the old mbuf and
1872 * the old DMA map untouched so that it can be reused.
1873 */
1874 static int
xl_newbuf(struct xl_softc * sc,struct xl_chain_onefrag * c,int init)1875 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c, int init)
1876 {
1877 struct mbuf *m_new;
1878 bus_dmamap_t map;
1879 int error, nsegs;
1880 bus_dma_segment_t seg;
1881
1882 m_new = m_getcl(init ? M_WAITOK : M_NOWAIT, MT_DATA, M_PKTHDR);
1883 if (m_new == NULL)
1884 return(ENOBUFS);
1885
1886 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1887
1888 /* Force longword alignment for packet payload. */
1889 m_adj(m_new, ETHER_ALIGN);
1890
1891 error = bus_dmamap_load_mbuf_segment(sc->xl_rx_mtag, sc->xl_tmpmap,
1892 m_new, &seg, 1, &nsegs, BUS_DMA_NOWAIT);
1893 if (error) {
1894 m_freem(m_new);
1895 if (init) {
1896 if_printf(&sc->arpcom.ac_if,
1897 "can't map mbuf (error %d)\n", error);
1898 }
1899 return(error);
1900 }
1901
1902 if (c->xl_mbuf != NULL) {
1903 bus_dmamap_sync(sc->xl_rx_mtag, c->xl_map,
1904 BUS_DMASYNC_POSTREAD);
1905 bus_dmamap_unload(sc->xl_rx_mtag, c->xl_map);
1906 }
1907
1908 map = c->xl_map;
1909 c->xl_map = sc->xl_tmpmap;
1910 sc->xl_tmpmap = map;
1911 c->xl_mbuf = m_new;
1912
1913 c->xl_ptr->xl_frag.xl_len = htole32(seg.ds_len | XL_LAST_FRAG);
1914 c->xl_ptr->xl_frag.xl_addr = htole32(seg.ds_addr);
1915 c->xl_ptr->xl_status = 0;
1916
1917 return(0);
1918 }
1919
1920 static int
xl_rx_resync(struct xl_softc * sc)1921 xl_rx_resync(struct xl_softc *sc)
1922 {
1923 struct xl_chain_onefrag *pos;
1924 int i;
1925
1926 pos = sc->xl_cdata.xl_rx_head;
1927
1928 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1929 if (pos->xl_ptr->xl_status)
1930 break;
1931 pos = pos->xl_next;
1932 }
1933
1934 if (i == XL_RX_LIST_CNT)
1935 return(0);
1936
1937 sc->xl_cdata.xl_rx_head = pos;
1938
1939 return(EAGAIN);
1940 }
1941
1942 /*
1943 * A frame has been uploaded: pass the resulting mbuf chain up to
1944 * the higher level protocols.
1945 */
1946 static void
xl_rxeof(struct xl_softc * sc,int count)1947 xl_rxeof(struct xl_softc *sc, int count)
1948 {
1949 struct mbuf *m;
1950 struct ifnet *ifp;
1951 struct xl_chain_onefrag *cur_rx;
1952 int total_len = 0;
1953 u_int32_t rxstat;
1954
1955 ifp = &sc->arpcom.ac_if;
1956 again:
1957 while((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) {
1958 #ifdef IFPOLL_ENABLE
1959 if (count >= 0 && count-- == 0)
1960 break;
1961 #endif
1962 cur_rx = sc->xl_cdata.xl_rx_head;
1963 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
1964 total_len = rxstat & XL_RXSTAT_LENMASK;
1965
1966 /*
1967 * Since we have told the chip to allow large frames,
1968 * we need to trap giant frame errors in software. We allow
1969 * a little more than the normal frame size to account for
1970 * frames with VLAN tags.
1971 */
1972 if (total_len > XL_MAX_FRAMELEN)
1973 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE);
1974
1975 /*
1976 * If an error occurs, update stats, clear the
1977 * status word and leave the mbuf cluster in place:
1978 * it should simply get re-used next time this descriptor
1979 * comes up in the ring.
1980 */
1981 if (rxstat & XL_RXSTAT_UP_ERROR) {
1982 IFNET_STAT_INC(ifp, ierrors, 1);
1983 cur_rx->xl_ptr->xl_status = 0;
1984 continue;
1985 }
1986
1987 /*
1988 * If the error bit was not set, the upload complete
1989 * bit should be set which means we have a valid packet.
1990 * If not, something truly strange has happened.
1991 */
1992 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
1993 if_printf(ifp,
1994 "bad receive status -- packet dropped\n");
1995 IFNET_STAT_INC(ifp, ierrors, 1);
1996 cur_rx->xl_ptr->xl_status = 0;
1997 continue;
1998 }
1999
2000 /* No errors; receive the packet. */
2001 m = cur_rx->xl_mbuf;
2002
2003 /*
2004 * Try to conjure up a new mbuf cluster. If that
2005 * fails, it means we have an out of memory condition and
2006 * should leave the buffer in place and continue. This will
2007 * result in a lost packet, but there's little else we
2008 * can do in this situation.
2009 */
2010 if (xl_newbuf(sc, cur_rx, 0)) {
2011 IFNET_STAT_INC(ifp, ierrors, 1);
2012 cur_rx->xl_ptr->xl_status = 0;
2013 continue;
2014 }
2015
2016 IFNET_STAT_INC(ifp, ipackets, 1);
2017 m->m_pkthdr.rcvif = ifp;
2018 m->m_pkthdr.len = m->m_len = total_len;
2019
2020 if (ifp->if_capenable & IFCAP_RXCSUM) {
2021 /* Do IP checksum checking. */
2022 if (rxstat & XL_RXSTAT_IPCKOK)
2023 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2024 if (!(rxstat & XL_RXSTAT_IPCKERR))
2025 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2026 if ((rxstat & XL_RXSTAT_TCPCOK &&
2027 !(rxstat & XL_RXSTAT_TCPCKERR)) ||
2028 (rxstat & XL_RXSTAT_UDPCKOK &&
2029 !(rxstat & XL_RXSTAT_UDPCKERR))) {
2030 m->m_pkthdr.csum_flags |=
2031 CSUM_DATA_VALID|CSUM_PSEUDO_HDR|
2032 CSUM_FRAG_NOT_CHECKED;
2033 m->m_pkthdr.csum_data = 0xffff;
2034 }
2035 }
2036
2037 ifp->if_input(ifp, m, NULL, -1);
2038 }
2039
2040 if (sc->xl_type != XL_TYPE_905B) {
2041 /*
2042 * Handle the 'end of channel' condition. When the upload
2043 * engine hits the end of the RX ring, it will stall. This
2044 * is our cue to flush the RX ring, reload the uplist pointer
2045 * register and unstall the engine.
2046 * XXX This is actually a little goofy. With the ThunderLAN
2047 * chip, you get an interrupt when the receiver hits the end
2048 * of the receive ring, which tells you exactly when you
2049 * you need to reload the ring pointer. Here we have to
2050 * fake it. I'm mad at myself for not being clever enough
2051 * to avoid the use of a goto here.
2052 */
2053 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
2054 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
2055 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2056 xl_wait(sc);
2057 CSR_WRITE_4(sc, XL_UPLIST_PTR,
2058 sc->xl_ldata.xl_rx_dmaaddr);
2059 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
2060 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2061 goto again;
2062 }
2063 }
2064 }
2065
2066 /*
2067 * A frame was downloaded to the chip. It's safe for us to clean up
2068 * the list buffers.
2069 */
2070 static void
xl_txeof(struct xl_softc * sc)2071 xl_txeof(struct xl_softc *sc)
2072 {
2073 struct xl_chain *cur_tx;
2074 struct ifnet *ifp;
2075
2076 ifp = &sc->arpcom.ac_if;
2077
2078 /* Clear the timeout timer. */
2079 ifp->if_timer = 0;
2080
2081 /*
2082 * Go through our tx list and free mbufs for those
2083 * frames that have been uploaded. Note: the 3c905B
2084 * sets a special bit in the status word to let us
2085 * know that a frame has been downloaded, but the
2086 * original 3c900/3c905 adapters don't do that.
2087 * Consequently, we have to use a different test if
2088 * xl_type != XL_TYPE_905B.
2089 */
2090 while(sc->xl_cdata.xl_tx_head != NULL) {
2091 cur_tx = sc->xl_cdata.xl_tx_head;
2092
2093 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
2094 break;
2095
2096 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
2097 bus_dmamap_unload(sc->xl_tx_mtag, cur_tx->xl_map);
2098 m_freem(cur_tx->xl_mbuf);
2099 cur_tx->xl_mbuf = NULL;
2100 IFNET_STAT_INC(ifp, opackets, 1);
2101
2102 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
2103 sc->xl_cdata.xl_tx_free = cur_tx;
2104 }
2105
2106 if (sc->xl_cdata.xl_tx_head == NULL) {
2107 ifq_clr_oactive(&ifp->if_snd);
2108 sc->xl_cdata.xl_tx_tail = NULL;
2109 } else {
2110 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
2111 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
2112 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2113 sc->xl_cdata.xl_tx_head->xl_phys);
2114 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2115 }
2116 }
2117
2118 return;
2119 }
2120
2121 static void
xl_txeof_90xB(struct xl_softc * sc)2122 xl_txeof_90xB(struct xl_softc *sc)
2123 {
2124 struct xl_chain *cur_tx = NULL;
2125 struct ifnet *ifp;
2126 int idx;
2127
2128 ifp = &sc->arpcom.ac_if;
2129
2130 idx = sc->xl_cdata.xl_tx_cons;
2131 while(idx != sc->xl_cdata.xl_tx_prod) {
2132
2133 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2134
2135 if (!(le32toh(cur_tx->xl_ptr->xl_status) &
2136 XL_TXSTAT_DL_COMPLETE))
2137 break;
2138
2139 if (cur_tx->xl_mbuf != NULL) {
2140 bus_dmamap_unload(sc->xl_tx_mtag, cur_tx->xl_map);
2141 m_freem(cur_tx->xl_mbuf);
2142 cur_tx->xl_mbuf = NULL;
2143 }
2144
2145 IFNET_STAT_INC(ifp, opackets, 1);
2146
2147 sc->xl_cdata.xl_tx_cnt--;
2148 XL_INC(idx, XL_TX_LIST_CNT);
2149 ifp->if_timer = 0;
2150 }
2151
2152 sc->xl_cdata.xl_tx_cons = idx;
2153
2154 if (cur_tx != NULL)
2155 ifq_clr_oactive(&ifp->if_snd);
2156
2157 return;
2158 }
2159
2160 /*
2161 * TX 'end of channel' interrupt handler. Actually, we should
2162 * only get a 'TX complete' interrupt if there's a transmit error,
2163 * so this is really TX error handler.
2164 */
2165 static void
xl_txeoc(struct xl_softc * sc)2166 xl_txeoc(struct xl_softc *sc)
2167 {
2168 struct ifnet *ifp = &sc->arpcom.ac_if;
2169 u_int8_t txstat;
2170
2171 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2172 if (txstat & XL_TXSTATUS_UNDERRUN ||
2173 txstat & XL_TXSTATUS_JABBER ||
2174 txstat & XL_TXSTATUS_RECLAIM) {
2175 if_printf(ifp, "transmission error: %x\n", txstat);
2176 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2177 xl_wait(sc);
2178 if (sc->xl_type == XL_TYPE_905B) {
2179 if (sc->xl_cdata.xl_tx_cnt) {
2180 int i;
2181 struct xl_chain *c;
2182 i = sc->xl_cdata.xl_tx_cons;
2183 c = &sc->xl_cdata.xl_tx_chain[i];
2184 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2185 c->xl_phys);
2186 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2187 }
2188 } else {
2189 if (sc->xl_cdata.xl_tx_head != NULL)
2190 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2191 sc->xl_cdata.xl_tx_head->xl_phys);
2192 }
2193 /*
2194 * Remember to set this for the
2195 * first generation 3c90X chips.
2196 */
2197 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2198 if (txstat & XL_TXSTATUS_UNDERRUN &&
2199 sc->xl_tx_thresh < XL_PACKET_SIZE) {
2200 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2201 if_printf(ifp, "tx underrun, increasing tx start"
2202 " threshold to %d bytes\n",
2203 sc->xl_tx_thresh);
2204 }
2205 CSR_WRITE_2(sc, XL_COMMAND,
2206 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2207 if (sc->xl_type == XL_TYPE_905B) {
2208 CSR_WRITE_2(sc, XL_COMMAND,
2209 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2210 }
2211 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2212 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2213 } else {
2214 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2215 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2216 }
2217 /*
2218 * Write an arbitrary byte to the TX_STATUS register
2219 * to clear this interrupt/error and advance to the next.
2220 */
2221 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2222 }
2223
2224 return;
2225 }
2226
2227 #ifdef IFPOLL_ENABLE
2228
2229 static void
xl_start_poll(struct ifnet * ifp,struct ifaltq_subque * ifsq)2230 xl_start_poll(struct ifnet *ifp, struct ifaltq_subque *ifsq)
2231 {
2232 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
2233 xl_start_body(ifp, 0);
2234 }
2235
2236 static void
xl_npoll_compat(struct ifnet * ifp,void * arg __unused,int count)2237 xl_npoll_compat(struct ifnet *ifp, void *arg __unused, int count)
2238 {
2239 struct xl_softc *sc = ifp->if_softc;
2240
2241 ASSERT_SERIALIZED(ifp->if_serializer);
2242
2243 if (sc->xl_npoll.ifpc_stcount-- == 0) {
2244 uint16_t status;
2245
2246 sc->xl_npoll.ifpc_stcount = sc->xl_npoll.ifpc_stfrac;
2247
2248 /* XXX copy & pasted from xl_intr() */
2249 status = CSR_READ_2(sc, XL_STATUS);
2250 if ((status & XL_INTRS) && status != 0xFFFF) {
2251 CSR_WRITE_2(sc, XL_COMMAND,
2252 XL_CMD_INTR_ACK | (status & XL_INTRS));
2253
2254 if (status & XL_STAT_TX_COMPLETE) {
2255 IFNET_STAT_INC(ifp, oerrors, 1);
2256 xl_txeoc(sc);
2257 }
2258
2259 if (status & XL_STAT_ADFAIL) {
2260 xl_reset(sc);
2261 xl_init(sc);
2262 }
2263
2264 if (status & XL_STAT_STATSOFLOW) {
2265 sc->xl_stats_no_timeout = 1;
2266 xl_stats_update_serialized(sc);
2267 sc->xl_stats_no_timeout = 0;
2268 }
2269 }
2270 }
2271
2272 xl_rxeof(sc, count);
2273 if (sc->xl_type == XL_TYPE_905B)
2274 xl_txeof_90xB(sc);
2275 else
2276 xl_txeof(sc);
2277
2278 if (!ifq_is_empty(&ifp->if_snd))
2279 if_devstart(ifp);
2280 }
2281
2282 static void
xl_npoll(struct ifnet * ifp,struct ifpoll_info * info)2283 xl_npoll(struct ifnet *ifp, struct ifpoll_info *info)
2284 {
2285 struct xl_softc *sc = ifp->if_softc;
2286
2287 ASSERT_SERIALIZED(ifp->if_serializer);
2288
2289 if (info != NULL) {
2290 int cpuid = sc->xl_npoll.ifpc_cpuid;
2291
2292 info->ifpi_rx[cpuid].poll_func = xl_npoll_compat;
2293 info->ifpi_rx[cpuid].arg = NULL;
2294 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
2295
2296 if (ifp->if_flags & IFF_RUNNING)
2297 xl_enable_intrs(sc, 0);
2298 if (sc->xl_type != XL_TYPE_905B)
2299 ifp->if_start = xl_start_poll;
2300 ifq_set_cpuid(&ifp->if_snd, cpuid);
2301 } else {
2302 if (sc->xl_type != XL_TYPE_905B)
2303 ifp->if_start = xl_start;
2304 if (ifp->if_flags & IFF_RUNNING)
2305 xl_enable_intrs(sc, XL_INTRS);
2306 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->xl_irq));
2307 }
2308 }
2309
2310 #endif /* IFPOLL_ENABLE */
2311
2312 static void
xl_intr(void * arg)2313 xl_intr(void *arg)
2314 {
2315 struct xl_softc *sc;
2316 struct ifnet *ifp;
2317 u_int16_t status;
2318
2319 sc = arg;
2320 ifp = &sc->arpcom.ac_if;
2321
2322 ASSERT_SERIALIZED(ifp->if_serializer);
2323
2324 while(((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS) &&
2325 status != 0xFFFF) {
2326
2327 CSR_WRITE_2(sc, XL_COMMAND,
2328 XL_CMD_INTR_ACK|(status & XL_INTRS));
2329
2330 if (status & XL_STAT_UP_COMPLETE) {
2331 u_long curpkts, ncurpkts;
2332
2333 IFNET_STAT_GET(ifp, ipackets, curpkts);
2334 xl_rxeof(sc, -1);
2335 IFNET_STAT_GET(ifp, ipackets, ncurpkts);
2336
2337 if (curpkts == ncurpkts) {
2338 while (xl_rx_resync(sc))
2339 xl_rxeof(sc, -1);
2340 }
2341 }
2342
2343 if (status & XL_STAT_DOWN_COMPLETE) {
2344 if (sc->xl_type == XL_TYPE_905B)
2345 xl_txeof_90xB(sc);
2346 else
2347 xl_txeof(sc);
2348 }
2349
2350 if (status & XL_STAT_TX_COMPLETE) {
2351 IFNET_STAT_INC(ifp, oerrors, 1);
2352 xl_txeoc(sc);
2353 }
2354
2355 if (status & XL_STAT_ADFAIL) {
2356 xl_reset(sc);
2357 xl_init(sc);
2358 }
2359
2360 if (status & XL_STAT_STATSOFLOW) {
2361 sc->xl_stats_no_timeout = 1;
2362 xl_stats_update_serialized(sc);
2363 sc->xl_stats_no_timeout = 0;
2364 }
2365 }
2366
2367 if (!ifq_is_empty(&ifp->if_snd))
2368 if_devstart(ifp);
2369 }
2370
2371 static void
xl_stats_update(void * xsc)2372 xl_stats_update(void *xsc)
2373 {
2374 struct xl_softc *sc = xsc;
2375
2376 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
2377 xl_stats_update_serialized(xsc);
2378 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
2379 }
2380
2381 static void
xl_stats_update_serialized(void * xsc)2382 xl_stats_update_serialized(void *xsc)
2383 {
2384 struct xl_softc *sc;
2385 struct ifnet *ifp;
2386 struct xl_stats xl_stats;
2387 u_int8_t *p;
2388 int i;
2389 struct mii_data *mii = NULL;
2390
2391 bzero((char *)&xl_stats, sizeof(struct xl_stats));
2392
2393 sc = xsc;
2394 ifp = &sc->arpcom.ac_if;
2395 if (sc->xl_miibus != NULL)
2396 mii = device_get_softc(sc->xl_miibus);
2397
2398 p = (u_int8_t *)&xl_stats;
2399
2400 /* Read all the stats registers. */
2401 XL_SEL_WIN(6);
2402
2403 for (i = 0; i < 16; i++)
2404 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2405
2406 IFNET_STAT_INC(ifp, ierrors, xl_stats.xl_rx_overrun);
2407
2408 IFNET_STAT_INC(ifp, collisions,
2409 xl_stats.xl_tx_multi_collision +
2410 xl_stats.xl_tx_single_collision +
2411 xl_stats.xl_tx_late_collision);
2412
2413 /*
2414 * Boomerang and cyclone chips have an extra stats counter
2415 * in window 4 (BadSSD). We have to read this too in order
2416 * to clear out all the stats registers and avoid a statsoflow
2417 * interrupt.
2418 */
2419 XL_SEL_WIN(4);
2420 CSR_READ_1(sc, XL_W4_BADSSD);
2421
2422 if ((mii != NULL) && (!sc->xl_stats_no_timeout))
2423 mii_tick(mii);
2424
2425 XL_SEL_WIN(7);
2426
2427 if (!sc->xl_stats_no_timeout)
2428 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc);
2429
2430 return;
2431 }
2432
2433 /*
2434 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2435 * pointers to the fragment pointers.
2436 */
2437 static int
xl_encap(struct xl_softc * sc,struct xl_chain * c,struct mbuf * m_head)2438 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf *m_head)
2439 {
2440 int error, nsegs, i;
2441 u_int32_t status;
2442 bus_dma_segment_t segs[XL_MAXFRAGS];
2443 struct xl_list *l;
2444
2445 error = bus_dmamap_load_mbuf_defrag(sc->xl_tx_mtag, c->xl_map, &m_head,
2446 segs, XL_MAXFRAGS, &nsegs, BUS_DMA_NOWAIT);
2447 if (error) {
2448 m_freem(m_head);
2449 return error;
2450 }
2451 bus_dmamap_sync(sc->xl_tx_mtag, c->xl_map, BUS_DMASYNC_PREWRITE);
2452
2453 if (sc->xl_type == XL_TYPE_905B) {
2454 status = XL_TXSTAT_RND_DEFEAT;
2455 if (m_head->m_pkthdr.csum_flags) {
2456 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2457 status |= XL_TXSTAT_IPCKSUM;
2458 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
2459 status |= XL_TXSTAT_TCPCKSUM;
2460 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
2461 status |= XL_TXSTAT_UDPCKSUM;
2462 }
2463 } else {
2464 status = m_head->m_pkthdr.len;
2465 }
2466
2467 l = c->xl_ptr;
2468 for (i = 0; i < nsegs; i++) {
2469 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr);
2470 l->xl_frag[i].xl_len = htole32(segs[i].ds_len);
2471 }
2472 l->xl_frag[nsegs - 1].xl_len =
2473 htole32(segs[nsegs - 1].ds_len | XL_LAST_FRAG);
2474 l->xl_status = htole32(status);
2475 l->xl_next = 0;
2476
2477 c->xl_mbuf = m_head;
2478
2479 return(0);
2480 }
2481
2482 static void
xl_start(struct ifnet * ifp,struct ifaltq_subque * ifsq)2483 xl_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
2484 {
2485 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
2486 ASSERT_SERIALIZED(ifp->if_serializer);
2487 xl_start_body(ifp, 1);
2488 }
2489
2490 /*
2491 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2492 * to the mbuf data regions directly in the transmit lists. We also save a
2493 * copy of the pointers since the transmit list fragment pointers are
2494 * physical addresses.
2495 */
2496 static void
xl_start_body(struct ifnet * ifp,int proc_rx)2497 xl_start_body(struct ifnet *ifp, int proc_rx)
2498 {
2499 struct xl_softc *sc;
2500 struct mbuf *m_head = NULL;
2501 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2502 struct xl_chain *prev_tx;
2503 u_int32_t status;
2504 int error;
2505
2506 sc = ifp->if_softc;
2507 /*
2508 * Check for an available queue slot. If there are none,
2509 * punt.
2510 */
2511 if (sc->xl_cdata.xl_tx_free == NULL) {
2512 xl_txeoc(sc);
2513 xl_txeof(sc);
2514 if (sc->xl_cdata.xl_tx_free == NULL) {
2515 ifq_set_oactive(&ifp->if_snd);
2516 return;
2517 }
2518 }
2519
2520 start_tx = sc->xl_cdata.xl_tx_free;
2521
2522 while(sc->xl_cdata.xl_tx_free != NULL) {
2523 m_head = ifq_dequeue(&ifp->if_snd);
2524 if (m_head == NULL)
2525 break;
2526
2527 /* Pick a descriptor off the free list. */
2528 prev_tx = cur_tx;
2529 cur_tx = sc->xl_cdata.xl_tx_free;
2530
2531 /* Pack the data into the descriptor. */
2532 error = xl_encap(sc, cur_tx, m_head);
2533 if (error) {
2534 cur_tx = prev_tx;
2535 continue;
2536 }
2537
2538 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2539 cur_tx->xl_next = NULL;
2540
2541 /* Chain it together. */
2542 if (prev != NULL) {
2543 prev->xl_next = cur_tx;
2544 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2545 }
2546 prev = cur_tx;
2547
2548 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2549 }
2550
2551 /*
2552 * If there are no packets queued, bail.
2553 */
2554 if (cur_tx == NULL)
2555 return;
2556
2557 /*
2558 * Place the request for the upload interrupt
2559 * in the last descriptor in the chain. This way, if
2560 * we're chaining several packets at once, we'll only
2561 * get an interupt once for the whole chain rather than
2562 * once for each packet.
2563 */
2564 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2565 XL_TXSTAT_DL_INTR);
2566
2567 /*
2568 * Queue the packets. If the TX channel is clear, update
2569 * the downlist pointer register.
2570 */
2571 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2572 xl_wait(sc);
2573
2574 if (sc->xl_cdata.xl_tx_head != NULL) {
2575 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2576 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2577 htole32(start_tx->xl_phys);
2578 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status;
2579 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status =
2580 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR);
2581 sc->xl_cdata.xl_tx_tail = cur_tx;
2582 } else {
2583 sc->xl_cdata.xl_tx_head = start_tx;
2584 sc->xl_cdata.xl_tx_tail = cur_tx;
2585 }
2586
2587 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2588 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys);
2589
2590 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2591
2592 XL_SEL_WIN(7);
2593
2594 /*
2595 * Set a timeout in case the chip goes out to lunch.
2596 */
2597 ifp->if_timer = 5;
2598
2599 if (proc_rx) {
2600 /*
2601 * XXX Under certain conditions, usually on slower machines
2602 * where interrupts may be dropped, it's possible for the
2603 * adapter to chew up all the buffers in the receive ring
2604 * and stall, without us being able to do anything about it.
2605 * To guard against this, we need to make a pass over the
2606 * RX queue to make sure there aren't any packets pending.
2607 * Doing it here means we can flush the receive ring at the
2608 * same time the chip is DMAing the transmit descriptors we
2609 * just gave it.
2610 *
2611 * 3Com goes to some lengths to emphasize the Parallel
2612 * Tasking (tm) nature of their chips in all their marketing
2613 * literature; we may as well take advantage of it. :)
2614 */
2615 xl_rxeof(sc, -1);
2616 }
2617 }
2618
2619 static void
xl_start_90xB(struct ifnet * ifp,struct ifaltq_subque * ifsq)2620 xl_start_90xB(struct ifnet *ifp, struct ifaltq_subque *ifsq)
2621 {
2622 struct xl_softc *sc;
2623 struct mbuf *m_head = NULL;
2624 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2625 struct xl_chain *prev_tx;
2626 int error, idx;
2627
2628 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
2629 ASSERT_SERIALIZED(ifp->if_serializer);
2630
2631 sc = ifp->if_softc;
2632
2633 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
2634 return;
2635
2636 idx = sc->xl_cdata.xl_tx_prod;
2637 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2638
2639 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) {
2640
2641 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2642 ifq_set_oactive(&ifp->if_snd);
2643 break;
2644 }
2645
2646 m_head = ifq_dequeue(&ifp->if_snd);
2647 if (m_head == NULL)
2648 break;
2649
2650 prev_tx = cur_tx;
2651 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2652
2653 /* Pack the data into the descriptor. */
2654 error = xl_encap(sc, cur_tx, m_head);
2655 if (error) {
2656 cur_tx = prev_tx;
2657 continue;
2658 }
2659
2660 /* Chain it together. */
2661 if (prev != NULL)
2662 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2663 prev = cur_tx;
2664
2665 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2666
2667 XL_INC(idx, XL_TX_LIST_CNT);
2668 sc->xl_cdata.xl_tx_cnt++;
2669 }
2670
2671 /*
2672 * If there are no packets queued, bail.
2673 */
2674 if (cur_tx == NULL)
2675 return;
2676
2677 /*
2678 * Place the request for the upload interrupt
2679 * in the last descriptor in the chain. This way, if
2680 * we're chaining several packets at once, we'll only
2681 * get an interupt once for the whole chain rather than
2682 * once for each packet.
2683 */
2684 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2685 XL_TXSTAT_DL_INTR);
2686
2687 /* Start transmission */
2688 sc->xl_cdata.xl_tx_prod = idx;
2689 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys);
2690
2691 /*
2692 * Set a timeout in case the chip goes out to lunch.
2693 */
2694 ifp->if_timer = 5;
2695 }
2696
2697 static void
xl_init(void * xsc)2698 xl_init(void *xsc)
2699 {
2700 struct xl_softc *sc = xsc;
2701 struct ifnet *ifp = &sc->arpcom.ac_if;
2702 int error, i;
2703 u_int16_t rxfilt = 0;
2704 struct mii_data *mii = NULL;
2705
2706 ASSERT_SERIALIZED(ifp->if_serializer);
2707
2708 /*
2709 * Cancel pending I/O and free all RX/TX buffers.
2710 */
2711 xl_stop(sc);
2712
2713 if (sc->xl_miibus == NULL) {
2714 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2715 xl_wait(sc);
2716 }
2717 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2718 xl_wait(sc);
2719 DELAY(10000);
2720
2721 if (sc->xl_miibus != NULL)
2722 mii = device_get_softc(sc->xl_miibus);
2723
2724 /* Init our MAC address */
2725 XL_SEL_WIN(2);
2726 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2727 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2728 sc->arpcom.ac_enaddr[i]);
2729 }
2730
2731 /* Clear the station mask. */
2732 for (i = 0; i < 3; i++)
2733 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2734 #ifdef notdef
2735 /* Reset TX and RX. */
2736 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2737 xl_wait(sc);
2738 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2739 xl_wait(sc);
2740 #endif
2741 /* Init circular RX list. */
2742 error = xl_list_rx_init(sc);
2743 if (error) {
2744 if_printf(ifp, "initialization of the rx ring failed (%d)\n",
2745 error);
2746 xl_stop(sc);
2747 return;
2748 }
2749
2750 /* Init TX descriptors. */
2751 if (sc->xl_type == XL_TYPE_905B)
2752 xl_list_tx_init_90xB(sc);
2753 else
2754 xl_list_tx_init(sc);
2755
2756 /*
2757 * Set the TX freethresh value.
2758 * Note that this has no effect on 3c905B "cyclone"
2759 * cards but is required for 3c900/3c905 "boomerang"
2760 * cards in order to enable the download engine.
2761 */
2762 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2763
2764 /* Set the TX start threshold for best performance. */
2765 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
2766 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2767
2768 /*
2769 * If this is a 3c905B, also set the tx reclaim threshold.
2770 * This helps cut down on the number of tx reclaim errors
2771 * that could happen on a busy network. The chip multiplies
2772 * the register value by 16 to obtain the actual threshold
2773 * in bytes, so we divide by 16 when setting the value here.
2774 * The existing threshold value can be examined by reading
2775 * the register at offset 9 in window 5.
2776 */
2777 if (sc->xl_type == XL_TYPE_905B) {
2778 CSR_WRITE_2(sc, XL_COMMAND,
2779 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2780 }
2781
2782 /* Set RX filter bits. */
2783 XL_SEL_WIN(5);
2784 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
2785
2786 /* Set the individual bit to receive frames for this host only. */
2787 rxfilt |= XL_RXFILTER_INDIVIDUAL;
2788
2789 /* If we want promiscuous mode, set the allframes bit. */
2790 if (ifp->if_flags & IFF_PROMISC) {
2791 rxfilt |= XL_RXFILTER_ALLFRAMES;
2792 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2793 } else {
2794 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
2795 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2796 }
2797
2798 /*
2799 * Set capture broadcast bit to capture broadcast frames.
2800 */
2801 if (ifp->if_flags & IFF_BROADCAST) {
2802 rxfilt |= XL_RXFILTER_BROADCAST;
2803 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2804 } else {
2805 rxfilt &= ~XL_RXFILTER_BROADCAST;
2806 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2807 }
2808
2809 /*
2810 * Program the multicast filter, if necessary.
2811 */
2812 if (sc->xl_type == XL_TYPE_905B)
2813 xl_setmulti_hash(sc);
2814 else
2815 xl_setmulti(sc);
2816
2817 if (sc->xl_type == XL_TYPE_905B) {
2818 /* Set UP polling interval */
2819 CSR_WRITE_1(sc, XL_UP_POLL, 64);
2820 }
2821
2822 /*
2823 * Load the address of the RX list. We have to
2824 * stall the upload engine before we can manipulate
2825 * the uplist pointer register, then unstall it when
2826 * we're finished. We also have to wait for the
2827 * stall command to complete before proceeding.
2828 * Note that we have to do this after any RX resets
2829 * have completed since the uplist register is cleared
2830 * by a reset.
2831 */
2832 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2833 xl_wait(sc);
2834 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2835 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2836 xl_wait(sc);
2837
2838 if (sc->xl_type == XL_TYPE_905B) {
2839 /* Set DN polling interval */
2840 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2841
2842 /* Load the address of the TX list */
2843 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2844 xl_wait(sc);
2845 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2846 sc->xl_cdata.xl_tx_chain[0].xl_phys);
2847 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2848 xl_wait(sc);
2849 }
2850
2851 /*
2852 * If the coax transceiver is on, make sure to enable
2853 * the DC-DC converter.
2854 */
2855 XL_SEL_WIN(3);
2856 if (sc->xl_xcvr == XL_XCVR_COAX)
2857 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2858 else
2859 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2860
2861 /*
2862 * increase packet size to allow reception of 802.1q or ISL packets.
2863 * For the 3c90x chip, set the 'allow large packets' bit in the MAC
2864 * control register. For 3c90xB/C chips, use the RX packet size
2865 * register.
2866 */
2867
2868 if (sc->xl_type == XL_TYPE_905B) {
2869 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
2870 } else {
2871 u_int8_t macctl;
2872 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
2873 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK;
2874 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
2875 }
2876
2877 /* Clear out the stats counters. */
2878 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2879 sc->xl_stats_no_timeout = 1;
2880 xl_stats_update_serialized(sc);
2881 sc->xl_stats_no_timeout = 0;
2882 XL_SEL_WIN(4);
2883 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2884 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2885
2886 /*
2887 * Enable interrupts.
2888 */
2889 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB | XL_INTRS);
2890 #ifdef IFPOLL_ENABLE
2891 /* Do not enable interrupt if polling(4) is enabled */
2892 if (ifp->if_flags & IFF_NPOLLING)
2893 xl_enable_intrs(sc, 0);
2894 else
2895 #endif
2896 xl_enable_intrs(sc, XL_INTRS);
2897
2898 /* Set the RX early threshold */
2899 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2900 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
2901
2902 /* Enable receiver and transmitter. */
2903 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2904 xl_wait(sc);
2905 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
2906 xl_wait(sc);
2907
2908 if (mii != NULL)
2909 mii_mediachg(mii);
2910
2911 /* Select window 7 for normal operations. */
2912 XL_SEL_WIN(7);
2913
2914 ifp->if_flags |= IFF_RUNNING;
2915 ifq_clr_oactive(&ifp->if_snd);
2916
2917 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc);
2918 }
2919
2920 /*
2921 * Set media options.
2922 */
2923 static int
xl_ifmedia_upd(struct ifnet * ifp)2924 xl_ifmedia_upd(struct ifnet *ifp)
2925 {
2926 struct xl_softc *sc;
2927 struct ifmedia *ifm = NULL;
2928 struct mii_data *mii = NULL;
2929
2930 ASSERT_SERIALIZED(ifp->if_serializer);
2931
2932 sc = ifp->if_softc;
2933 if (sc->xl_miibus != NULL)
2934 mii = device_get_softc(sc->xl_miibus);
2935 if (mii == NULL)
2936 ifm = &sc->ifmedia;
2937 else
2938 ifm = &mii->mii_media;
2939
2940 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2941 case IFM_100_FX:
2942 case IFM_10_FL:
2943 case IFM_10_2:
2944 case IFM_10_5:
2945 xl_setmode(sc, ifm->ifm_media);
2946 return(0);
2947 break;
2948 default:
2949 break;
2950 }
2951
2952 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
2953 || sc->xl_media & XL_MEDIAOPT_BT4) {
2954 xl_init(sc);
2955 } else {
2956 xl_setmode(sc, ifm->ifm_media);
2957 }
2958
2959 return(0);
2960 }
2961
2962 /*
2963 * Report current media status.
2964 */
2965 static void
xl_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)2966 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2967 {
2968 struct xl_softc *sc;
2969 u_int32_t icfg;
2970 struct mii_data *mii = NULL;
2971
2972 ASSERT_SERIALIZED(ifp->if_serializer);
2973
2974 sc = ifp->if_softc;
2975 if (sc->xl_miibus != NULL)
2976 mii = device_get_softc(sc->xl_miibus);
2977
2978 XL_SEL_WIN(3);
2979 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
2980 icfg >>= XL_ICFG_CONNECTOR_BITS;
2981
2982 ifmr->ifm_active = IFM_ETHER;
2983
2984 switch(icfg) {
2985 case XL_XCVR_10BT:
2986 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2987 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2988 ifmr->ifm_active |= IFM_FDX;
2989 else
2990 ifmr->ifm_active |= IFM_HDX;
2991 break;
2992 case XL_XCVR_AUI:
2993 if (sc->xl_type == XL_TYPE_905B &&
2994 sc->xl_media == XL_MEDIAOPT_10FL) {
2995 ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
2996 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2997 ifmr->ifm_active |= IFM_FDX;
2998 else
2999 ifmr->ifm_active |= IFM_HDX;
3000 } else
3001 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
3002 break;
3003 case XL_XCVR_COAX:
3004 ifmr->ifm_active = IFM_ETHER|IFM_10_2;
3005 break;
3006 /*
3007 * XXX MII and BTX/AUTO should be separate cases.
3008 */
3009
3010 case XL_XCVR_100BTX:
3011 case XL_XCVR_AUTO:
3012 case XL_XCVR_MII:
3013 if (mii != NULL) {
3014 mii_pollstat(mii);
3015 ifmr->ifm_active = mii->mii_media_active;
3016 ifmr->ifm_status = mii->mii_media_status;
3017 }
3018 break;
3019 case XL_XCVR_100BFX:
3020 ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
3021 break;
3022 default:
3023 if_printf(ifp, "unknown XCVR type: %d\n", icfg);
3024 break;
3025 }
3026
3027 return;
3028 }
3029
3030 static int
xl_ioctl(struct ifnet * ifp,u_long command,caddr_t data,struct ucred * cr)3031 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3032 {
3033 struct xl_softc *sc = ifp->if_softc;
3034 struct ifreq *ifr = (struct ifreq *) data;
3035 int error = 0;
3036 struct mii_data *mii = NULL;
3037 u_int8_t rxfilt;
3038
3039 ASSERT_SERIALIZED(ifp->if_serializer);
3040
3041 switch(command) {
3042 case SIOCSIFFLAGS:
3043 XL_SEL_WIN(5);
3044 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
3045 if (ifp->if_flags & IFF_UP) {
3046 if (ifp->if_flags & IFF_RUNNING &&
3047 ifp->if_flags & IFF_PROMISC &&
3048 !(sc->xl_if_flags & IFF_PROMISC)) {
3049 rxfilt |= XL_RXFILTER_ALLFRAMES;
3050 CSR_WRITE_2(sc, XL_COMMAND,
3051 XL_CMD_RX_SET_FILT|rxfilt);
3052 XL_SEL_WIN(7);
3053 } else if (ifp->if_flags & IFF_RUNNING &&
3054 !(ifp->if_flags & IFF_PROMISC) &&
3055 sc->xl_if_flags & IFF_PROMISC) {
3056 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
3057 CSR_WRITE_2(sc, XL_COMMAND,
3058 XL_CMD_RX_SET_FILT|rxfilt);
3059 XL_SEL_WIN(7);
3060 } else
3061 xl_init(sc);
3062 } else {
3063 if (ifp->if_flags & IFF_RUNNING)
3064 xl_stop(sc);
3065 }
3066 sc->xl_if_flags = ifp->if_flags;
3067 error = 0;
3068 break;
3069 case SIOCADDMULTI:
3070 case SIOCDELMULTI:
3071 if (sc->xl_type == XL_TYPE_905B)
3072 xl_setmulti_hash(sc);
3073 else
3074 xl_setmulti(sc);
3075 error = 0;
3076 break;
3077 case SIOCGIFMEDIA:
3078 case SIOCSIFMEDIA:
3079 if (sc->xl_miibus != NULL)
3080 mii = device_get_softc(sc->xl_miibus);
3081 if (mii == NULL)
3082 error = ifmedia_ioctl(ifp, ifr,
3083 &sc->ifmedia, command);
3084 else
3085 error = ifmedia_ioctl(ifp, ifr,
3086 &mii->mii_media, command);
3087 break;
3088 case SIOCSIFCAP:
3089 ifp->if_capenable &= ~IFCAP_HWCSUM;
3090 ifp->if_capenable |= (ifr->ifr_reqcap & IFCAP_HWCSUM);
3091 if (ifp->if_capenable & IFCAP_HWCSUM)
3092 ifp->if_hwassist = XL905B_CSUM_FEATURES;
3093 else
3094 ifp->if_hwassist = 0;
3095 break;
3096 default:
3097 error = ether_ioctl(ifp, command, data);
3098 break;
3099 }
3100 return(error);
3101 }
3102
3103 static void
xl_watchdog(struct ifnet * ifp)3104 xl_watchdog(struct ifnet *ifp)
3105 {
3106 struct xl_softc *sc;
3107 u_int16_t status = 0;
3108
3109 ASSERT_SERIALIZED(ifp->if_serializer);
3110
3111 sc = ifp->if_softc;
3112
3113 IFNET_STAT_INC(ifp, oerrors, 1);
3114 XL_SEL_WIN(4);
3115 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3116 if_printf(ifp, "watchdog timeout\n");
3117
3118 if (status & XL_MEDIASTAT_CARRIER)
3119 if_printf(ifp, "no carrier - transceiver cable problem?\n");
3120 xl_txeoc(sc);
3121 xl_txeof(sc);
3122 xl_rxeof(sc, -1);
3123 xl_reset(sc);
3124 xl_init(sc);
3125
3126 if (!ifq_is_empty(&ifp->if_snd))
3127 if_devstart(ifp);
3128 }
3129
3130 /*
3131 * Stop the adapter and free any mbufs allocated to the
3132 * RX and TX lists.
3133 */
3134 static void
xl_stop(struct xl_softc * sc)3135 xl_stop(struct xl_softc *sc)
3136 {
3137 int i;
3138 struct ifnet *ifp;
3139
3140 ifp = &sc->arpcom.ac_if;
3141 ASSERT_SERIALIZED(ifp->if_serializer);
3142
3143 ifp->if_timer = 0;
3144
3145 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
3146 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
3147 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
3148 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
3149 xl_wait(sc);
3150 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
3151 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
3152 DELAY(800);
3153
3154 #ifdef foo
3155 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
3156 xl_wait(sc);
3157 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
3158 xl_wait(sc);
3159 #endif
3160
3161 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
3162 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
3163 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3164 if (sc->xl_flags & XL_FLAG_FUNCREG)
3165 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3166
3167 /* Stop the stats updater. */
3168 callout_stop(&sc->xl_stat_timer);
3169
3170 /*
3171 * Free data in the RX lists.
3172 */
3173 for (i = 0; i < XL_RX_LIST_CNT; i++) {
3174 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
3175 bus_dmamap_unload(sc->xl_rx_mtag,
3176 sc->xl_cdata.xl_rx_chain[i].xl_map);
3177 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
3178 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
3179 }
3180 }
3181 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
3182
3183 /*
3184 * Free the TX list buffers.
3185 */
3186 for (i = 0; i < XL_TX_LIST_CNT; i++) {
3187 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
3188 bus_dmamap_unload(sc->xl_tx_mtag,
3189 sc->xl_cdata.xl_tx_chain[i].xl_map);
3190 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
3191 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
3192 }
3193 }
3194 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
3195
3196 ifp->if_flags &= ~IFF_RUNNING;
3197 ifq_clr_oactive(&ifp->if_snd);
3198 }
3199
3200 /*
3201 * Stop all chip I/O so that the kernel's probe routines don't
3202 * get confused by errant DMAs when rebooting.
3203 */
3204 static void
xl_shutdown(device_t dev)3205 xl_shutdown(device_t dev)
3206 {
3207 struct xl_softc *sc = device_get_softc(dev);
3208
3209 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
3210 xl_reset(sc);
3211 xl_stop(sc);
3212 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
3213 }
3214
3215 static int
xl_suspend(device_t dev)3216 xl_suspend(device_t dev)
3217 {
3218 struct xl_softc *sc = device_get_softc(dev);
3219
3220 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
3221 xl_stop(sc);
3222 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
3223
3224 return(0);
3225 }
3226
3227 static int
xl_resume(device_t dev)3228 xl_resume(device_t dev)
3229 {
3230 struct xl_softc *sc;
3231 struct ifnet *ifp;
3232
3233 sc = device_get_softc(dev);
3234 ifp = &sc->arpcom.ac_if;
3235
3236 lwkt_serialize_enter(ifp->if_serializer);
3237 xl_reset(sc);
3238 if (ifp->if_flags & IFF_UP)
3239 xl_init(sc);
3240 lwkt_serialize_exit(ifp->if_serializer);
3241
3242 return(0);
3243 }
3244