1 /* $NetBSD: fpu_explode.c,v 1.13 2022/08/28 22:09:26 rin Exp $ */
2
3 /*
4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved.
6 *
7 * This software was developed by the Computer Systems Engineering group
8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
9 * contributed to Berkeley.
10 *
11 * All advertising materials mentioning features or use of this software
12 * must display the following acknowledgement:
13 * This product includes software developed by the University of
14 * California, Lawrence Berkeley Laboratory.
15 *
16 * Redistribution and use in source and binary forms, with or without
17 * modification, are permitted provided that the following conditions
18 * are met:
19 * 1. Redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution.
24 * 3. Neither the name of the University nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * SUCH DAMAGE.
39 *
40 * @(#)fpu_explode.c 8.1 (Berkeley) 6/11/93
41 */
42
43 /*
44 * FPU subroutines: `explode' the machine's `packed binary' format numbers
45 * into our internal format.
46 */
47
48 #include <sys/cdefs.h>
49 __KERNEL_RCSID(0, "$NetBSD: fpu_explode.c,v 1.13 2022/08/28 22:09:26 rin Exp $");
50
51 #if defined(_KERNEL_OPT)
52 #include "opt_sparc_arch.h"
53 #endif
54
55 #include <sys/types.h>
56 #include <sys/systm.h>
57
58 #include <machine/ieee.h>
59 #include <machine/instr.h>
60 #include <machine/reg.h>
61
62 #include <sparc/fpu/fpu_arith.h>
63 #include <sparc/fpu/fpu_emu.h>
64 #include <sparc/fpu/fpu_extern.h>
65
66 /*
67 * N.B.: in all of the following, we assume the FP format is
68 *
69 * ---------------------------
70 * | s | exponent | fraction |
71 * ---------------------------
72 *
73 * (which represents -1**s * 1.fraction * 2**exponent), so that the
74 * sign bit is way at the top (bit 31), the exponent is next, and
75 * then the remaining bits mark the fraction. A zero exponent means
76 * zero or denormalized (0.fraction rather than 1.fraction), and the
77 * maximum possible exponent, 2bias+1, signals inf (fraction==0) or NaN.
78 *
79 * Since the sign bit is always the topmost bit---this holds even for
80 * integers---we set that outside all the *tof functions. Each function
81 * returns the class code for the new number (but note that we use
82 * FPC_QNAN for all NaNs; fpu_explode will fix this if appropriate).
83 */
84
85 /*
86 * int -> fpn.
87 */
88 int
fpu_itof(struct fpn * fp,u_int i)89 fpu_itof(struct fpn *fp, u_int i)
90 {
91
92 if (i == 0)
93 return (FPC_ZERO);
94 /*
95 * The value FP_1 represents 2^FP_LG, so set the exponent
96 * there and let normalization fix it up. Convert negative
97 * numbers to sign-and-magnitude. Note that this relies on
98 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c.
99 */
100 fp->fp_exp = FP_LG;
101 fp->fp_mant[0] = (int)i < 0 ? -i : i;
102 fp->fp_mant[1] = 0;
103 fp->fp_mant[2] = 0;
104 fp->fp_mant[3] = 0;
105 fpu_norm(fp);
106 return (FPC_NUM);
107 }
108
109 #ifdef SUN4U
110 /*
111 * 64-bit int -> fpn.
112 */
113 int
fpu_xtof(struct fpn * fp,uint64_t i)114 fpu_xtof(struct fpn *fp, uint64_t i)
115 {
116
117 if (i == 0)
118 return (FPC_ZERO);
119 /*
120 * The value FP_1 represents 2^FP_LG, so set the exponent
121 * there and let normalization fix it up. Convert negative
122 * numbers to sign-and-magnitude. Note that this relies on
123 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c.
124 */
125 fp->fp_exp = FP_LG2;
126 *((int64_t*)fp->fp_mant) = (int64_t)i < 0 ? -i : i;
127 fp->fp_mant[2] = 0;
128 fp->fp_mant[3] = 0;
129 fpu_norm(fp);
130 return (FPC_NUM);
131 }
132 #endif /* SUN4U */
133
134 #define mask(nbits) ((1L << (nbits)) - 1)
135
136 /*
137 * All external floating formats convert to internal in the same manner,
138 * as defined here. Note that only normals get an implied 1.0 inserted.
139 */
140 #define FP_TOF(exp, expbias, allfrac, f0, f1, f2, f3) \
141 if (exp == 0) { \
142 if (allfrac == 0) \
143 return (FPC_ZERO); \
144 fp->fp_exp = 1 - expbias; \
145 fp->fp_mant[0] = f0; \
146 fp->fp_mant[1] = f1; \
147 fp->fp_mant[2] = f2; \
148 fp->fp_mant[3] = f3; \
149 fpu_norm(fp); \
150 return (FPC_NUM); \
151 } \
152 if (exp == (2 * expbias + 1)) { \
153 if (allfrac == 0) \
154 return (FPC_INF); \
155 fp->fp_mant[0] = f0; \
156 fp->fp_mant[1] = f1; \
157 fp->fp_mant[2] = f2; \
158 fp->fp_mant[3] = f3; \
159 return (FPC_QNAN); \
160 } \
161 fp->fp_exp = exp - expbias; \
162 fp->fp_mant[0] = FP_1 | f0; \
163 fp->fp_mant[1] = f1; \
164 fp->fp_mant[2] = f2; \
165 fp->fp_mant[3] = f3; \
166 return (FPC_NUM)
167
168 /*
169 * 32-bit single precision -> fpn.
170 * We assume a single occupies at most (64-FP_LG) bits in the internal
171 * format: i.e., needs at most fp_mant[0] and fp_mant[1].
172 */
173 int
fpu_stof(struct fpn * fp,u_int i)174 fpu_stof(struct fpn *fp, u_int i)
175 {
176 int exp;
177 u_int frac, f0, f1;
178 #define SNG_SHIFT (SNG_FRACBITS - FP_LG)
179
180 exp = (i >> (32 - 1 - SNG_EXPBITS)) & mask(SNG_EXPBITS);
181 frac = i & mask(SNG_FRACBITS);
182 f0 = frac >> SNG_SHIFT;
183 f1 = frac << (32 - SNG_SHIFT);
184 FP_TOF(exp, SNG_EXP_BIAS, frac, f0, f1, 0, 0);
185 }
186
187 /*
188 * 64-bit double -> fpn.
189 * We assume this uses at most (96-FP_LG) bits.
190 */
191 int
fpu_dtof(struct fpn * fp,u_int i,u_int j)192 fpu_dtof(struct fpn *fp, u_int i, u_int j)
193 {
194 int exp;
195 u_int frac, f0, f1, f2;
196 #define DBL_SHIFT (DBL_FRACBITS - 32 - FP_LG)
197
198 exp = (i >> (32 - 1 - DBL_EXPBITS)) & mask(DBL_EXPBITS);
199 frac = i & mask(DBL_FRACBITS - 32);
200 f0 = frac >> DBL_SHIFT;
201 f1 = (frac << (32 - DBL_SHIFT)) | (j >> DBL_SHIFT);
202 f2 = j << (32 - DBL_SHIFT);
203 frac |= j;
204 FP_TOF(exp, DBL_EXP_BIAS, frac, f0, f1, f2, 0);
205 }
206
207 /*
208 * 128-bit extended -> fpn.
209 */
210 int
fpu_qtof(struct fpn * fp,u_int i,u_int j,u_int k,u_int l)211 fpu_qtof(struct fpn *fp, u_int i, u_int j, u_int k, u_int l)
212 {
213 int exp;
214 u_int frac, f0, f1, f2, f3;
215 #define EXT_SHIFT (-(EXT_FRACBITS - 3 * 32 - FP_LG)) /* left shift! */
216
217 /*
218 * Note that ext and fpn `line up', hence no shifting needed.
219 */
220 exp = (i >> (32 - 1 - EXT_EXPBITS)) & mask(EXT_EXPBITS);
221 frac = i & mask(EXT_FRACBITS - 3 * 32);
222 f0 = (frac << EXT_SHIFT) | (j >> (32 - EXT_SHIFT));
223 f1 = (j << EXT_SHIFT) | (k >> (32 - EXT_SHIFT));
224 f2 = (k << EXT_SHIFT) | (l >> (32 - EXT_SHIFT));
225 f3 = l << EXT_SHIFT;
226 frac |= j | k | l;
227 FP_TOF(exp, EXT_EXP_BIAS, frac, f0, f1, f2, f3);
228 }
229
230 /*
231 * Explode the contents of a register / regpair / regquad.
232 * If the input is a signalling NaN, an NV (invalid) exception
233 * will be set. (Note that nothing but NV can occur until ALU
234 * operations are performed.)
235 */
236 void
fpu_explode(struct fpemu * fe,struct fpn * fp,int type,int reg)237 fpu_explode(struct fpemu *fe, struct fpn *fp, int type, int reg)
238 {
239 u_int s, *space;
240 #ifdef SUN4U
241 uint64_t l, *xspace;
242
243 xspace = (uint64_t *)&fe->fe_fpstate->fs_regs[reg & ~1];
244 l = xspace[0];
245 #endif /* SUN4U */
246 space = &fe->fe_fpstate->fs_regs[reg];
247 s = space[0];
248 fp->fp_sign = s >> 31;
249 fp->fp_sticky = 0;
250 switch (type) {
251 #ifdef SUN4U
252 case FTYPE_LNG:
253 s = fpu_xtof(fp, l);
254 break;
255 #endif /* SUN4U */
256
257 case FTYPE_INT:
258 s = fpu_itof(fp, s);
259 break;
260
261 case FTYPE_SNG:
262 s = fpu_stof(fp, s);
263 break;
264
265 case FTYPE_DBL:
266 s = fpu_dtof(fp, s, space[1]);
267 break;
268
269 case FTYPE_EXT:
270 s = fpu_qtof(fp, s, space[1], space[2], space[3]);
271 break;
272
273 default:
274 panic("fpu_explode");
275 }
276
277 if (s == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) {
278 /*
279 * Input is a signalling NaN. All operations that return
280 * an input NaN operand put it through a ``NaN conversion'',
281 * which basically just means ``turn on the quiet bit''.
282 * We do this here so that all NaNs internally look quiet
283 * (we can tell signalling ones by their class).
284 */
285 fp->fp_mant[0] |= FP_QUIETBIT;
286 fe->fe_cx = FSR_NV; /* assert invalid operand */
287 s = FPC_SNAN;
288 }
289 fp->fp_class = s;
290 DPRINTF(FPE_REG, ("fpu_explode: %%%c%d => ", (type == FTYPE_LNG) ? 'x' :
291 ((type == FTYPE_INT) ? 'i' :
292 ((type == FTYPE_SNG) ? 's' :
293 ((type == FTYPE_DBL) ? 'd' :
294 ((type == FTYPE_EXT) ? 'q' : '?')))),
295 reg));
296 #ifdef DEBUG
297 if (fpe_debug & FPE_REG) {
298 if (type == FTYPE_INT) printf("%d ", s);
299 #ifdef SUN4U
300 #ifdef _LP64
301 if (type == FTYPE_LNG) printf("%ld ", l);
302 #else
303 if (type == FTYPE_LNG) printf("%lld ", l);
304 #endif
305 #endif /* SUN4U */
306 }
307 #endif /* DEBUG */
308 DUMPFPN(FPE_REG, fp);
309 DPRINTF(FPE_REG, ("\n"));
310 }
311