1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include "amdgpu.h"
27 #include "amdgpu_smu.h"
28 #include "smu_v13_0.h"
29 #include "smu13_driver_if_yellow_carp.h"
30 #include "yellow_carp_ppt.h"
31 #include "smu_v13_0_1_ppsmc.h"
32 #include "smu_v13_0_1_pmfw.h"
33 #include "smu_cmn.h"
34
35 /*
36 * DO NOT use these for err/warn/info/debug messages.
37 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
38 * They are more MGPU friendly.
39 */
40 #undef pr_err
41 #undef pr_warn
42 #undef pr_info
43 #undef pr_debug
44
45 #define regSMUIO_GFX_MISC_CNTL 0x00c5
46 #define regSMUIO_GFX_MISC_CNTL_BASE_IDX 0
47 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK 0x00000006L
48 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT 0x1L
49
50 #define SMU_13_0_8_UMD_PSTATE_GFXCLK 533
51 #define SMU_13_0_8_UMD_PSTATE_SOCCLK 533
52 #define SMU_13_0_8_UMD_PSTATE_FCLK 800
53
54 #define SMU_13_0_1_UMD_PSTATE_GFXCLK 700
55 #define SMU_13_0_1_UMD_PSTATE_SOCCLK 678
56 #define SMU_13_0_1_UMD_PSTATE_FCLK 1800
57
58 #define FEATURE_MASK(feature) (1ULL << feature)
59 #define SMC_DPM_FEATURE ( \
60 FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
61 FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \
62 FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \
63 FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \
64 FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \
65 FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \
66 FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \
67 FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \
68 FEATURE_MASK(FEATURE_GFX_DPM_BIT))
69
70 static struct cmn2asic_msg_mapping yellow_carp_message_map[SMU_MSG_MAX_COUNT] = {
71 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
72 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
73 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
74 MSG_MAP(EnableGfxOff, PPSMC_MSG_EnableGfxOff, 1),
75 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 1),
76 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 1),
77 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1),
78 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1),
79 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1),
80 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
81 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
82 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
83 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
84 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1),
85 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1),
86 MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 1),
87 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 1),
88 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1),
89 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1),
90 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 1),
91 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1),
92 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1),
93 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 1),
94 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 1),
95 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1),
96 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 1),
97 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1),
98 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1),
99 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 1),
100 MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 1),
101 };
102
103 static struct cmn2asic_mapping yellow_carp_feature_mask_map[SMU_FEATURE_COUNT] = {
104 FEA_MAP(CCLK_DPM),
105 FEA_MAP(FAN_CONTROLLER),
106 FEA_MAP(PPT),
107 FEA_MAP(TDC),
108 FEA_MAP(THERMAL),
109 FEA_MAP(ULV),
110 FEA_MAP(VCN_DPM),
111 FEA_MAP_REVERSE(FCLK),
112 FEA_MAP_REVERSE(SOCCLK),
113 FEA_MAP(LCLK_DPM),
114 FEA_MAP(SHUBCLK_DPM),
115 FEA_MAP(DCFCLK_DPM),
116 FEA_MAP_HALF_REVERSE(GFX),
117 FEA_MAP(DS_GFXCLK),
118 FEA_MAP(DS_SOCCLK),
119 FEA_MAP(DS_LCLK),
120 FEA_MAP(DS_DCFCLK),
121 FEA_MAP(DS_FCLK),
122 FEA_MAP(DS_MP1CLK),
123 FEA_MAP(DS_MP0CLK),
124 FEA_MAP(GFX_DEM),
125 FEA_MAP(PSI),
126 FEA_MAP(PROCHOT),
127 FEA_MAP(CPUOFF),
128 FEA_MAP(STAPM),
129 FEA_MAP(S0I3),
130 FEA_MAP(PERF_LIMIT),
131 FEA_MAP(CORE_DLDO),
132 FEA_MAP(RSMU_LOW_POWER),
133 FEA_MAP(SMN_LOW_POWER),
134 FEA_MAP(THM_LOW_POWER),
135 FEA_MAP(SMUIO_LOW_POWER),
136 FEA_MAP(MP1_LOW_POWER),
137 FEA_MAP(DS_VCN),
138 FEA_MAP(CPPC),
139 FEA_MAP(DF_CSTATES),
140 FEA_MAP(MSMU_LOW_POWER),
141 FEA_MAP(ATHUB_PG),
142 };
143
144 static struct cmn2asic_mapping yellow_carp_table_map[SMU_TABLE_COUNT] = {
145 TAB_MAP_VALID(WATERMARKS),
146 TAB_MAP_VALID(SMU_METRICS),
147 TAB_MAP_VALID(CUSTOM_DPM),
148 TAB_MAP_VALID(DPMCLOCKS),
149 };
150
yellow_carp_init_smc_tables(struct smu_context * smu)151 static int yellow_carp_init_smc_tables(struct smu_context *smu)
152 {
153 struct smu_table_context *smu_table = &smu->smu_table;
154 struct smu_table *tables = smu_table->tables;
155
156 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
157 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
158 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
159 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
160 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
161 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
162
163 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
164 if (!smu_table->clocks_table)
165 goto err0_out;
166
167 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
168 if (!smu_table->metrics_table)
169 goto err1_out;
170 smu_table->metrics_time = 0;
171
172 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
173 if (!smu_table->watermarks_table)
174 goto err2_out;
175
176 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1);
177 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
178 if (!smu_table->gpu_metrics_table)
179 goto err3_out;
180
181 return 0;
182
183 err3_out:
184 kfree(smu_table->watermarks_table);
185 err2_out:
186 kfree(smu_table->metrics_table);
187 err1_out:
188 kfree(smu_table->clocks_table);
189 err0_out:
190 return -ENOMEM;
191 }
192
yellow_carp_fini_smc_tables(struct smu_context * smu)193 static int yellow_carp_fini_smc_tables(struct smu_context *smu)
194 {
195 struct smu_table_context *smu_table = &smu->smu_table;
196
197 kfree(smu_table->clocks_table);
198 smu_table->clocks_table = NULL;
199
200 kfree(smu_table->metrics_table);
201 smu_table->metrics_table = NULL;
202
203 kfree(smu_table->watermarks_table);
204 smu_table->watermarks_table = NULL;
205
206 kfree(smu_table->gpu_metrics_table);
207 smu_table->gpu_metrics_table = NULL;
208
209 return 0;
210 }
211
yellow_carp_system_features_control(struct smu_context * smu,bool en)212 static int yellow_carp_system_features_control(struct smu_context *smu, bool en)
213 {
214 struct amdgpu_device *adev = smu->adev;
215 int ret = 0;
216
217 if (!en && !adev->in_s0ix)
218 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
219
220 return ret;
221 }
222
yellow_carp_dpm_set_vcn_enable(struct smu_context * smu,bool enable)223 static int yellow_carp_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
224 {
225 int ret = 0;
226
227 /* vcn dpm on is a prerequisite for vcn power gate messages */
228 if (enable)
229 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
230 0, NULL);
231 else
232 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
233 0, NULL);
234
235 return ret;
236 }
237
yellow_carp_dpm_set_jpeg_enable(struct smu_context * smu,bool enable)238 static int yellow_carp_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
239 {
240 int ret = 0;
241
242 if (enable)
243 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg,
244 0, NULL);
245 else
246 ret = smu_cmn_send_smc_msg_with_param(smu,
247 SMU_MSG_PowerDownJpeg, 0,
248 NULL);
249
250 return ret;
251 }
252
253
yellow_carp_is_dpm_running(struct smu_context * smu)254 static bool yellow_carp_is_dpm_running(struct smu_context *smu)
255 {
256 int ret = 0;
257 uint64_t feature_enabled;
258
259 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
260
261 if (ret)
262 return false;
263
264 return !!(feature_enabled & SMC_DPM_FEATURE);
265 }
266
yellow_carp_post_smu_init(struct smu_context * smu)267 static int yellow_carp_post_smu_init(struct smu_context *smu)
268 {
269 struct amdgpu_device *adev = smu->adev;
270 int ret = 0;
271
272 /* allow message will be sent after enable message on Yellow Carp*/
273 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL);
274 if (ret)
275 dev_err(adev->dev, "Failed to Enable GfxOff!\n");
276 return ret;
277 }
278
yellow_carp_mode_reset(struct smu_context * smu,int type)279 static int yellow_carp_mode_reset(struct smu_context *smu, int type)
280 {
281 int ret = 0;
282
283 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, type, NULL);
284 if (ret)
285 dev_err(smu->adev->dev, "Failed to mode reset!\n");
286
287 return ret;
288 }
289
yellow_carp_mode2_reset(struct smu_context * smu)290 static int yellow_carp_mode2_reset(struct smu_context *smu)
291 {
292 return yellow_carp_mode_reset(smu, SMU_RESET_MODE_2);
293 }
294
295
yellow_carp_get_ss_power_percent(SmuMetrics_t * metrics,uint32_t * apu_percent,uint32_t * dgpu_percent)296 static void yellow_carp_get_ss_power_percent(SmuMetrics_t *metrics,
297 uint32_t *apu_percent, uint32_t *dgpu_percent)
298 {
299 uint32_t apu_boost = 0;
300 uint32_t dgpu_boost = 0;
301 uint16_t apu_limit = 0;
302 uint16_t dgpu_limit = 0;
303 uint16_t apu_power = 0;
304 uint16_t dgpu_power = 0;
305
306 /* APU and dGPU power values are reported in milli Watts
307 * and STAPM power limits are in Watts */
308 apu_power = metrics->ApuPower/1000;
309 apu_limit = metrics->StapmOpnLimit;
310 if (apu_power > apu_limit && apu_limit != 0)
311 apu_boost = ((apu_power - apu_limit) * 100) / apu_limit;
312 apu_boost = (apu_boost > 100) ? 100 : apu_boost;
313
314 dgpu_power = metrics->dGpuPower/1000;
315 if (metrics->StapmCurrentLimit > metrics->StapmOpnLimit)
316 dgpu_limit = metrics->StapmCurrentLimit - metrics->StapmOpnLimit;
317 if (dgpu_power > dgpu_limit && dgpu_limit != 0)
318 dgpu_boost = ((dgpu_power - dgpu_limit) * 100) / dgpu_limit;
319 dgpu_boost = (dgpu_boost > 100) ? 100 : dgpu_boost;
320
321 if (dgpu_boost >= apu_boost)
322 apu_boost = 0;
323 else
324 dgpu_boost = 0;
325
326 *apu_percent = apu_boost;
327 *dgpu_percent = dgpu_boost;
328
329 }
330
yellow_carp_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)331 static int yellow_carp_get_smu_metrics_data(struct smu_context *smu,
332 MetricsMember_t member,
333 uint32_t *value)
334 {
335 struct smu_table_context *smu_table = &smu->smu_table;
336
337 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
338 int ret = 0;
339 uint32_t apu_percent = 0;
340 uint32_t dgpu_percent = 0;
341
342 ret = smu_cmn_get_metrics_table(smu, NULL, false);
343 if (ret)
344 return ret;
345
346 switch (member) {
347 case METRICS_AVERAGE_GFXCLK:
348 *value = metrics->GfxclkFrequency;
349 break;
350 case METRICS_AVERAGE_SOCCLK:
351 *value = metrics->SocclkFrequency;
352 break;
353 case METRICS_AVERAGE_VCLK:
354 *value = metrics->VclkFrequency;
355 break;
356 case METRICS_AVERAGE_DCLK:
357 *value = metrics->DclkFrequency;
358 break;
359 case METRICS_AVERAGE_UCLK:
360 *value = metrics->MemclkFrequency;
361 break;
362 case METRICS_AVERAGE_GFXACTIVITY:
363 *value = metrics->GfxActivity / 100;
364 break;
365 case METRICS_AVERAGE_VCNACTIVITY:
366 *value = metrics->UvdActivity / 100;
367 break;
368 case METRICS_CURR_SOCKETPOWER:
369 *value = (metrics->CurrentSocketPower << 8) / 1000;
370 break;
371 case METRICS_TEMPERATURE_EDGE:
372 *value = metrics->GfxTemperature / 100 *
373 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
374 break;
375 case METRICS_TEMPERATURE_HOTSPOT:
376 *value = metrics->SocTemperature / 100 *
377 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
378 break;
379 case METRICS_THROTTLER_STATUS:
380 *value = metrics->ThrottlerStatus;
381 break;
382 case METRICS_VOLTAGE_VDDGFX:
383 *value = metrics->Voltage[0];
384 break;
385 case METRICS_VOLTAGE_VDDSOC:
386 *value = metrics->Voltage[1];
387 break;
388 case METRICS_SS_APU_SHARE:
389 /* return the percentage of APU power boost
390 * with respect to APU's power limit.
391 */
392 yellow_carp_get_ss_power_percent(metrics, &apu_percent, &dgpu_percent);
393 *value = apu_percent;
394 break;
395 case METRICS_SS_DGPU_SHARE:
396 /* return the percentage of dGPU power boost
397 * with respect to dGPU's power limit.
398 */
399 yellow_carp_get_ss_power_percent(metrics, &apu_percent, &dgpu_percent);
400 *value = dgpu_percent;
401 break;
402 default:
403 *value = UINT_MAX;
404 break;
405 }
406
407 return ret;
408 }
409
yellow_carp_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)410 static int yellow_carp_read_sensor(struct smu_context *smu,
411 enum amd_pp_sensors sensor,
412 void *data, uint32_t *size)
413 {
414 int ret = 0;
415
416 if (!data || !size)
417 return -EINVAL;
418
419 switch (sensor) {
420 case AMDGPU_PP_SENSOR_GPU_LOAD:
421 ret = yellow_carp_get_smu_metrics_data(smu,
422 METRICS_AVERAGE_GFXACTIVITY,
423 (uint32_t *)data);
424 *size = 4;
425 break;
426 case AMDGPU_PP_SENSOR_VCN_LOAD:
427 ret = yellow_carp_get_smu_metrics_data(smu,
428 METRICS_AVERAGE_VCNACTIVITY,
429 (uint32_t *)data);
430 *size = 4;
431 break;
432 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
433 ret = yellow_carp_get_smu_metrics_data(smu,
434 METRICS_CURR_SOCKETPOWER,
435 (uint32_t *)data);
436 *size = 4;
437 break;
438 case AMDGPU_PP_SENSOR_EDGE_TEMP:
439 ret = yellow_carp_get_smu_metrics_data(smu,
440 METRICS_TEMPERATURE_EDGE,
441 (uint32_t *)data);
442 *size = 4;
443 break;
444 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
445 ret = yellow_carp_get_smu_metrics_data(smu,
446 METRICS_TEMPERATURE_HOTSPOT,
447 (uint32_t *)data);
448 *size = 4;
449 break;
450 case AMDGPU_PP_SENSOR_GFX_MCLK:
451 ret = yellow_carp_get_smu_metrics_data(smu,
452 METRICS_AVERAGE_UCLK,
453 (uint32_t *)data);
454 *(uint32_t *)data *= 100;
455 *size = 4;
456 break;
457 case AMDGPU_PP_SENSOR_GFX_SCLK:
458 ret = yellow_carp_get_smu_metrics_data(smu,
459 METRICS_AVERAGE_GFXCLK,
460 (uint32_t *)data);
461 *(uint32_t *)data *= 100;
462 *size = 4;
463 break;
464 case AMDGPU_PP_SENSOR_VDDGFX:
465 ret = yellow_carp_get_smu_metrics_data(smu,
466 METRICS_VOLTAGE_VDDGFX,
467 (uint32_t *)data);
468 *size = 4;
469 break;
470 case AMDGPU_PP_SENSOR_VDDNB:
471 ret = yellow_carp_get_smu_metrics_data(smu,
472 METRICS_VOLTAGE_VDDSOC,
473 (uint32_t *)data);
474 *size = 4;
475 break;
476 case AMDGPU_PP_SENSOR_SS_APU_SHARE:
477 ret = yellow_carp_get_smu_metrics_data(smu,
478 METRICS_SS_APU_SHARE,
479 (uint32_t *)data);
480 *size = 4;
481 break;
482 case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
483 ret = yellow_carp_get_smu_metrics_data(smu,
484 METRICS_SS_DGPU_SHARE,
485 (uint32_t *)data);
486 *size = 4;
487 break;
488 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
489 default:
490 ret = -EOPNOTSUPP;
491 break;
492 }
493
494 return ret;
495 }
496
yellow_carp_set_watermarks_table(struct smu_context * smu,struct pp_smu_wm_range_sets * clock_ranges)497 static int yellow_carp_set_watermarks_table(struct smu_context *smu,
498 struct pp_smu_wm_range_sets *clock_ranges)
499 {
500 int i;
501 int ret = 0;
502 Watermarks_t *table = smu->smu_table.watermarks_table;
503
504 if (!table || !clock_ranges)
505 return -EINVAL;
506
507 if (clock_ranges) {
508 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
509 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
510 return -EINVAL;
511
512 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
513 table->WatermarkRow[WM_DCFCLK][i].MinClock =
514 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
515 table->WatermarkRow[WM_DCFCLK][i].MaxClock =
516 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
517 table->WatermarkRow[WM_DCFCLK][i].MinMclk =
518 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
519 table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
520 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
521
522 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
523 clock_ranges->reader_wm_sets[i].wm_inst;
524 }
525
526 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
527 table->WatermarkRow[WM_SOCCLK][i].MinClock =
528 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
529 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
530 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
531 table->WatermarkRow[WM_SOCCLK][i].MinMclk =
532 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
533 table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
534 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
535
536 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
537 clock_ranges->writer_wm_sets[i].wm_inst;
538 }
539
540 smu->watermarks_bitmap |= WATERMARKS_EXIST;
541 }
542
543 /* pass data to smu controller */
544 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
545 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
546 ret = smu_cmn_write_watermarks_table(smu);
547 if (ret) {
548 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
549 return ret;
550 }
551 smu->watermarks_bitmap |= WATERMARKS_LOADED;
552 }
553
554 return 0;
555 }
556
yellow_carp_get_gpu_metrics(struct smu_context * smu,void ** table)557 static ssize_t yellow_carp_get_gpu_metrics(struct smu_context *smu,
558 void **table)
559 {
560 struct smu_table_context *smu_table = &smu->smu_table;
561 struct gpu_metrics_v2_1 *gpu_metrics =
562 (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table;
563 SmuMetrics_t metrics;
564 int ret = 0;
565
566 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
567 if (ret)
568 return ret;
569
570 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1);
571
572 gpu_metrics->temperature_gfx = metrics.GfxTemperature;
573 gpu_metrics->temperature_soc = metrics.SocTemperature;
574 memcpy(&gpu_metrics->temperature_core[0],
575 &metrics.CoreTemperature[0],
576 sizeof(uint16_t) * 8);
577 gpu_metrics->temperature_l3[0] = metrics.L3Temperature;
578
579 gpu_metrics->average_gfx_activity = metrics.GfxActivity;
580 gpu_metrics->average_mm_activity = metrics.UvdActivity;
581
582 gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
583 gpu_metrics->average_gfx_power = metrics.Power[0];
584 gpu_metrics->average_soc_power = metrics.Power[1];
585 memcpy(&gpu_metrics->average_core_power[0],
586 &metrics.CorePower[0],
587 sizeof(uint16_t) * 8);
588
589 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
590 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
591 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
592 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
593 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
594 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
595
596 memcpy(&gpu_metrics->current_coreclk[0],
597 &metrics.CoreFrequency[0],
598 sizeof(uint16_t) * 8);
599 gpu_metrics->current_l3clk[0] = metrics.L3Frequency;
600
601 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
602
603 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
604
605 *table = (void *)gpu_metrics;
606
607 return sizeof(struct gpu_metrics_v2_1);
608 }
609
610 /**
611 * yellow_carp_get_gfxoff_status - get gfxoff status
612 *
613 * @smu: smu_context pointer
614 *
615 * This function will be used to get gfxoff status
616 *
617 * Returns 0=GFXOFF(default).
618 * Returns 1=Transition out of GFX State.
619 * Returns 2=Not in GFXOFF.
620 * Returns 3=Transition into GFXOFF.
621 */
yellow_carp_get_gfxoff_status(struct smu_context * smu)622 static uint32_t yellow_carp_get_gfxoff_status(struct smu_context *smu)
623 {
624 uint32_t reg;
625 uint32_t gfxoff_status = 0;
626 struct amdgpu_device *adev = smu->adev;
627
628 reg = RREG32_SOC15(SMUIO, 0, regSMUIO_GFX_MISC_CNTL);
629 gfxoff_status = (reg & SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK)
630 >> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT;
631
632 return gfxoff_status;
633 }
634
yellow_carp_set_default_dpm_tables(struct smu_context * smu)635 static int yellow_carp_set_default_dpm_tables(struct smu_context *smu)
636 {
637 struct smu_table_context *smu_table = &smu->smu_table;
638
639 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
640 }
641
yellow_carp_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)642 static int yellow_carp_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
643 long input[], uint32_t size)
644 {
645 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
646 int ret = 0;
647
648 /* Only allowed in manual mode */
649 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
650 return -EINVAL;
651
652 switch (type) {
653 case PP_OD_EDIT_SCLK_VDDC_TABLE:
654 if (size != 2) {
655 dev_err(smu->adev->dev, "Input parameter number not correct\n");
656 return -EINVAL;
657 }
658
659 if (input[0] == 0) {
660 if (input[1] < smu->gfx_default_hard_min_freq) {
661 dev_warn(smu->adev->dev,
662 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
663 input[1], smu->gfx_default_hard_min_freq);
664 return -EINVAL;
665 }
666 smu->gfx_actual_hard_min_freq = input[1];
667 } else if (input[0] == 1) {
668 if (input[1] > smu->gfx_default_soft_max_freq) {
669 dev_warn(smu->adev->dev,
670 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
671 input[1], smu->gfx_default_soft_max_freq);
672 return -EINVAL;
673 }
674 smu->gfx_actual_soft_max_freq = input[1];
675 } else {
676 return -EINVAL;
677 }
678 break;
679 case PP_OD_RESTORE_DEFAULT_TABLE:
680 if (size != 0) {
681 dev_err(smu->adev->dev, "Input parameter number not correct\n");
682 return -EINVAL;
683 } else {
684 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
685 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
686 }
687 break;
688 case PP_OD_COMMIT_DPM_TABLE:
689 if (size != 0) {
690 dev_err(smu->adev->dev, "Input parameter number not correct\n");
691 return -EINVAL;
692 } else {
693 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
694 dev_err(smu->adev->dev,
695 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
696 smu->gfx_actual_hard_min_freq,
697 smu->gfx_actual_soft_max_freq);
698 return -EINVAL;
699 }
700
701 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
702 smu->gfx_actual_hard_min_freq, NULL);
703 if (ret) {
704 dev_err(smu->adev->dev, "Set hard min sclk failed!");
705 return ret;
706 }
707
708 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
709 smu->gfx_actual_soft_max_freq, NULL);
710 if (ret) {
711 dev_err(smu->adev->dev, "Set soft max sclk failed!");
712 return ret;
713 }
714 }
715 break;
716 default:
717 return -ENOSYS;
718 }
719
720 return ret;
721 }
722
yellow_carp_get_current_clk_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)723 static int yellow_carp_get_current_clk_freq(struct smu_context *smu,
724 enum smu_clk_type clk_type,
725 uint32_t *value)
726 {
727 MetricsMember_t member_type;
728
729 switch (clk_type) {
730 case SMU_SOCCLK:
731 member_type = METRICS_AVERAGE_SOCCLK;
732 break;
733 case SMU_VCLK:
734 member_type = METRICS_AVERAGE_VCLK;
735 break;
736 case SMU_DCLK:
737 member_type = METRICS_AVERAGE_DCLK;
738 break;
739 case SMU_MCLK:
740 member_type = METRICS_AVERAGE_UCLK;
741 break;
742 case SMU_FCLK:
743 return smu_cmn_send_smc_msg_with_param(smu,
744 SMU_MSG_GetFclkFrequency, 0, value);
745 case SMU_GFXCLK:
746 case SMU_SCLK:
747 return smu_cmn_send_smc_msg_with_param(smu,
748 SMU_MSG_GetGfxclkFrequency, 0, value);
749 break;
750 default:
751 return -EINVAL;
752 }
753
754 return yellow_carp_get_smu_metrics_data(smu, member_type, value);
755 }
756
yellow_carp_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * count)757 static int yellow_carp_get_dpm_level_count(struct smu_context *smu,
758 enum smu_clk_type clk_type,
759 uint32_t *count)
760 {
761 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
762
763 switch (clk_type) {
764 case SMU_SOCCLK:
765 *count = clk_table->NumSocClkLevelsEnabled;
766 break;
767 case SMU_VCLK:
768 *count = clk_table->VcnClkLevelsEnabled;
769 break;
770 case SMU_DCLK:
771 *count = clk_table->VcnClkLevelsEnabled;
772 break;
773 case SMU_MCLK:
774 *count = clk_table->NumDfPstatesEnabled;
775 break;
776 case SMU_FCLK:
777 *count = clk_table->NumDfPstatesEnabled;
778 break;
779 default:
780 return -EINVAL;
781 }
782
783 return 0;
784 }
785
yellow_carp_get_dpm_freq_by_index(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t dpm_level,uint32_t * freq)786 static int yellow_carp_get_dpm_freq_by_index(struct smu_context *smu,
787 enum smu_clk_type clk_type,
788 uint32_t dpm_level,
789 uint32_t *freq)
790 {
791 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
792
793 if (!clk_table || clk_type >= SMU_CLK_COUNT)
794 return -EINVAL;
795
796 switch (clk_type) {
797 case SMU_SOCCLK:
798 if (dpm_level >= clk_table->NumSocClkLevelsEnabled)
799 return -EINVAL;
800 *freq = clk_table->SocClocks[dpm_level];
801 break;
802 case SMU_VCLK:
803 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
804 return -EINVAL;
805 *freq = clk_table->VClocks[dpm_level];
806 break;
807 case SMU_DCLK:
808 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
809 return -EINVAL;
810 *freq = clk_table->DClocks[dpm_level];
811 break;
812 case SMU_UCLK:
813 case SMU_MCLK:
814 if (dpm_level >= clk_table->NumDfPstatesEnabled)
815 return -EINVAL;
816 *freq = clk_table->DfPstateTable[dpm_level].MemClk;
817 break;
818 case SMU_FCLK:
819 if (dpm_level >= clk_table->NumDfPstatesEnabled)
820 return -EINVAL;
821 *freq = clk_table->DfPstateTable[dpm_level].FClk;
822 break;
823 default:
824 return -EINVAL;
825 }
826
827 return 0;
828 }
829
yellow_carp_clk_dpm_is_enabled(struct smu_context * smu,enum smu_clk_type clk_type)830 static bool yellow_carp_clk_dpm_is_enabled(struct smu_context *smu,
831 enum smu_clk_type clk_type)
832 {
833 enum smu_feature_mask feature_id = 0;
834
835 switch (clk_type) {
836 case SMU_MCLK:
837 case SMU_UCLK:
838 case SMU_FCLK:
839 feature_id = SMU_FEATURE_DPM_FCLK_BIT;
840 break;
841 case SMU_GFXCLK:
842 case SMU_SCLK:
843 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
844 break;
845 case SMU_SOCCLK:
846 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
847 break;
848 case SMU_VCLK:
849 case SMU_DCLK:
850 feature_id = SMU_FEATURE_VCN_DPM_BIT;
851 break;
852 default:
853 return true;
854 }
855
856 return smu_cmn_feature_is_enabled(smu, feature_id);
857 }
858
yellow_carp_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)859 static int yellow_carp_get_dpm_ultimate_freq(struct smu_context *smu,
860 enum smu_clk_type clk_type,
861 uint32_t *min,
862 uint32_t *max)
863 {
864 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
865 uint32_t clock_limit;
866 uint32_t max_dpm_level, min_dpm_level;
867 int ret = 0;
868
869 if (!yellow_carp_clk_dpm_is_enabled(smu, clk_type)) {
870 ret = smu_v13_0_get_boot_freq_by_index(smu, clk_type, &clock_limit);
871 if (ret)
872 return ret;
873
874 /* clock in Mhz unit */
875 if (min)
876 *min = clock_limit / 100;
877 if (max)
878 *max = clock_limit / 100;
879
880 return 0;
881 }
882
883 if (max) {
884 switch (clk_type) {
885 case SMU_GFXCLK:
886 case SMU_SCLK:
887 *max = clk_table->MaxGfxClk;
888 break;
889 case SMU_MCLK:
890 case SMU_UCLK:
891 case SMU_FCLK:
892 max_dpm_level = 0;
893 break;
894 case SMU_SOCCLK:
895 max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
896 break;
897 case SMU_VCLK:
898 case SMU_DCLK:
899 max_dpm_level = clk_table->VcnClkLevelsEnabled - 1;
900 break;
901 default:
902 ret = -EINVAL;
903 goto failed;
904 }
905
906 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
907 ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max);
908 if (ret)
909 goto failed;
910 }
911 }
912
913 if (min) {
914 switch (clk_type) {
915 case SMU_GFXCLK:
916 case SMU_SCLK:
917 *min = clk_table->MinGfxClk;
918 break;
919 case SMU_MCLK:
920 case SMU_UCLK:
921 case SMU_FCLK:
922 min_dpm_level = clk_table->NumDfPstatesEnabled - 1;
923 break;
924 case SMU_SOCCLK:
925 min_dpm_level = 0;
926 break;
927 case SMU_VCLK:
928 case SMU_DCLK:
929 min_dpm_level = 0;
930 break;
931 default:
932 ret = -EINVAL;
933 goto failed;
934 }
935
936 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
937 ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min);
938 if (ret)
939 goto failed;
940 }
941 }
942
943 failed:
944 return ret;
945 }
946
yellow_carp_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)947 static int yellow_carp_set_soft_freq_limited_range(struct smu_context *smu,
948 enum smu_clk_type clk_type,
949 uint32_t min,
950 uint32_t max)
951 {
952 enum smu_message_type msg_set_min, msg_set_max;
953 uint32_t min_clk = min;
954 uint32_t max_clk = max;
955
956 int ret = 0;
957
958 if (!yellow_carp_clk_dpm_is_enabled(smu, clk_type))
959 return -EINVAL;
960
961 switch (clk_type) {
962 case SMU_GFXCLK:
963 case SMU_SCLK:
964 msg_set_min = SMU_MSG_SetHardMinGfxClk;
965 msg_set_max = SMU_MSG_SetSoftMaxGfxClk;
966 break;
967 case SMU_FCLK:
968 msg_set_min = SMU_MSG_SetHardMinFclkByFreq;
969 msg_set_max = SMU_MSG_SetSoftMaxFclkByFreq;
970 break;
971 case SMU_SOCCLK:
972 msg_set_min = SMU_MSG_SetHardMinSocclkByFreq;
973 msg_set_max = SMU_MSG_SetSoftMaxSocclkByFreq;
974 break;
975 case SMU_VCLK:
976 case SMU_DCLK:
977 msg_set_min = SMU_MSG_SetHardMinVcn;
978 msg_set_max = SMU_MSG_SetSoftMaxVcn;
979 break;
980 default:
981 return -EINVAL;
982 }
983
984 if (clk_type == SMU_VCLK) {
985 min_clk = min << SMU_13_VCLK_SHIFT;
986 max_clk = max << SMU_13_VCLK_SHIFT;
987 }
988
989 ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min_clk, NULL);
990
991 if (ret)
992 goto out;
993
994 ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max_clk, NULL);
995 if (ret)
996 goto out;
997
998 out:
999 return ret;
1000 }
1001
yellow_carp_get_umd_pstate_clk_default(struct smu_context * smu,enum smu_clk_type clk_type)1002 static uint32_t yellow_carp_get_umd_pstate_clk_default(struct smu_context *smu,
1003 enum smu_clk_type clk_type)
1004 {
1005 uint32_t clk_limit = 0;
1006 struct amdgpu_device *adev = smu->adev;
1007
1008 switch (clk_type) {
1009 case SMU_GFXCLK:
1010 case SMU_SCLK:
1011 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 8))
1012 clk_limit = SMU_13_0_8_UMD_PSTATE_GFXCLK;
1013 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 1) ||
1014 (amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 3))
1015 clk_limit = SMU_13_0_1_UMD_PSTATE_GFXCLK;
1016 break;
1017 case SMU_SOCCLK:
1018 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 8))
1019 clk_limit = SMU_13_0_8_UMD_PSTATE_SOCCLK;
1020 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 1) ||
1021 (amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 3))
1022 clk_limit = SMU_13_0_1_UMD_PSTATE_SOCCLK;
1023 break;
1024 case SMU_FCLK:
1025 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 8))
1026 clk_limit = SMU_13_0_8_UMD_PSTATE_FCLK;
1027 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 1) ||
1028 (amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 3))
1029 clk_limit = SMU_13_0_1_UMD_PSTATE_FCLK;
1030 break;
1031 default:
1032 break;
1033 }
1034
1035 return clk_limit;
1036 }
1037
yellow_carp_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)1038 static int yellow_carp_print_clk_levels(struct smu_context *smu,
1039 enum smu_clk_type clk_type, char *buf)
1040 {
1041 int i, idx, size = 0, ret = 0;
1042 uint32_t cur_value = 0, value = 0, count = 0;
1043 uint32_t min, max;
1044 uint32_t clk_limit = 0;
1045
1046 smu_cmn_get_sysfs_buf(&buf, &size);
1047
1048 switch (clk_type) {
1049 case SMU_OD_SCLK:
1050 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
1051 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
1052 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
1053 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
1054 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
1055 break;
1056 case SMU_OD_RANGE:
1057 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1058 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1059 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
1060 break;
1061 case SMU_SOCCLK:
1062 case SMU_VCLK:
1063 case SMU_DCLK:
1064 case SMU_MCLK:
1065 case SMU_FCLK:
1066 ret = yellow_carp_get_current_clk_freq(smu, clk_type, &cur_value);
1067 if (ret)
1068 goto print_clk_out;
1069
1070 ret = yellow_carp_get_dpm_level_count(smu, clk_type, &count);
1071 if (ret)
1072 goto print_clk_out;
1073
1074 for (i = 0; i < count; i++) {
1075 idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
1076 ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, idx, &value);
1077 if (ret)
1078 goto print_clk_out;
1079
1080 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
1081 cur_value == value ? "*" : "");
1082 }
1083 break;
1084 case SMU_GFXCLK:
1085 case SMU_SCLK:
1086 clk_limit = yellow_carp_get_umd_pstate_clk_default(smu, clk_type);
1087 ret = yellow_carp_get_current_clk_freq(smu, clk_type, &cur_value);
1088 if (ret)
1089 goto print_clk_out;
1090 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
1091 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
1092 if (cur_value == max)
1093 i = 2;
1094 else if (cur_value == min)
1095 i = 0;
1096 else
1097 i = 1;
1098 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
1099 i == 0 ? "*" : "");
1100 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
1101 i == 1 ? cur_value : clk_limit,
1102 i == 1 ? "*" : "");
1103 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
1104 i == 2 ? "*" : "");
1105 break;
1106 default:
1107 break;
1108 }
1109
1110 print_clk_out:
1111 return size;
1112 }
1113
yellow_carp_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1114 static int yellow_carp_force_clk_levels(struct smu_context *smu,
1115 enum smu_clk_type clk_type, uint32_t mask)
1116 {
1117 uint32_t soft_min_level = 0, soft_max_level = 0;
1118 uint32_t min_freq = 0, max_freq = 0;
1119 int ret = 0;
1120
1121 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1122 soft_max_level = mask ? (fls(mask) - 1) : 0;
1123
1124 switch (clk_type) {
1125 case SMU_SOCCLK:
1126 case SMU_FCLK:
1127 case SMU_VCLK:
1128 case SMU_DCLK:
1129 ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1130 if (ret)
1131 goto force_level_out;
1132
1133 ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1134 if (ret)
1135 goto force_level_out;
1136
1137 ret = yellow_carp_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1138 if (ret)
1139 goto force_level_out;
1140 break;
1141 default:
1142 ret = -EINVAL;
1143 break;
1144 }
1145
1146 force_level_out:
1147 return ret;
1148 }
1149
yellow_carp_get_dpm_profile_freq(struct smu_context * smu,enum amd_dpm_forced_level level,enum smu_clk_type clk_type,uint32_t * min_clk,uint32_t * max_clk)1150 static int yellow_carp_get_dpm_profile_freq(struct smu_context *smu,
1151 enum amd_dpm_forced_level level,
1152 enum smu_clk_type clk_type,
1153 uint32_t *min_clk,
1154 uint32_t *max_clk)
1155 {
1156 int ret = 0;
1157 uint32_t clk_limit = 0;
1158
1159 clk_limit = yellow_carp_get_umd_pstate_clk_default(smu, clk_type);
1160
1161 switch (clk_type) {
1162 case SMU_GFXCLK:
1163 case SMU_SCLK:
1164 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
1165 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &clk_limit);
1166 else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
1167 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, &clk_limit, NULL);
1168 break;
1169 case SMU_SOCCLK:
1170 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
1171 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &clk_limit);
1172 break;
1173 case SMU_FCLK:
1174 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
1175 yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &clk_limit);
1176 else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
1177 yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, &clk_limit, NULL);
1178 break;
1179 case SMU_VCLK:
1180 yellow_carp_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &clk_limit);
1181 break;
1182 case SMU_DCLK:
1183 yellow_carp_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &clk_limit);
1184 break;
1185 default:
1186 ret = -EINVAL;
1187 break;
1188 }
1189 *min_clk = *max_clk = clk_limit;
1190 return ret;
1191 }
1192
yellow_carp_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1193 static int yellow_carp_set_performance_level(struct smu_context *smu,
1194 enum amd_dpm_forced_level level)
1195 {
1196 struct amdgpu_device *adev = smu->adev;
1197 uint32_t sclk_min = 0, sclk_max = 0;
1198 uint32_t fclk_min = 0, fclk_max = 0;
1199 uint32_t socclk_min = 0, socclk_max = 0;
1200 uint32_t vclk_min = 0, vclk_max = 0;
1201 uint32_t dclk_min = 0, dclk_max = 0;
1202
1203 int ret = 0;
1204
1205 switch (level) {
1206 case AMD_DPM_FORCED_LEVEL_HIGH:
1207 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max);
1208 yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_max);
1209 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_max);
1210 yellow_carp_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_max);
1211 yellow_carp_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_max);
1212 sclk_min = sclk_max;
1213 fclk_min = fclk_max;
1214 socclk_min = socclk_max;
1215 vclk_min = vclk_max;
1216 dclk_min = dclk_max;
1217 break;
1218 case AMD_DPM_FORCED_LEVEL_LOW:
1219 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL);
1220 yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, NULL);
1221 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, NULL);
1222 yellow_carp_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, NULL);
1223 yellow_carp_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, NULL);
1224 sclk_max = sclk_min;
1225 fclk_max = fclk_min;
1226 socclk_max = socclk_min;
1227 vclk_max = vclk_min;
1228 dclk_max = dclk_min;
1229 break;
1230 case AMD_DPM_FORCED_LEVEL_AUTO:
1231 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max);
1232 yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, &fclk_max);
1233 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, &socclk_max);
1234 yellow_carp_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, &vclk_max);
1235 yellow_carp_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, &dclk_max);
1236 break;
1237 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1238 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1239 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1240 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1241 yellow_carp_get_dpm_profile_freq(smu, level, SMU_SCLK, &sclk_min, &sclk_max);
1242 yellow_carp_get_dpm_profile_freq(smu, level, SMU_FCLK, &fclk_min, &fclk_max);
1243 yellow_carp_get_dpm_profile_freq(smu, level, SMU_SOCCLK, &socclk_min, &socclk_max);
1244 yellow_carp_get_dpm_profile_freq(smu, level, SMU_VCLK, &vclk_min, &vclk_max);
1245 yellow_carp_get_dpm_profile_freq(smu, level, SMU_DCLK, &dclk_min, &dclk_max);
1246 break;
1247 case AMD_DPM_FORCED_LEVEL_MANUAL:
1248 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1249 return 0;
1250 default:
1251 dev_err(adev->dev, "Invalid performance level %d\n", level);
1252 return -EINVAL;
1253 }
1254
1255 if (sclk_min && sclk_max) {
1256 ret = yellow_carp_set_soft_freq_limited_range(smu,
1257 SMU_SCLK,
1258 sclk_min,
1259 sclk_max);
1260 if (ret)
1261 return ret;
1262
1263 smu->gfx_actual_hard_min_freq = sclk_min;
1264 smu->gfx_actual_soft_max_freq = sclk_max;
1265 }
1266
1267 if (fclk_min && fclk_max) {
1268 ret = yellow_carp_set_soft_freq_limited_range(smu,
1269 SMU_FCLK,
1270 fclk_min,
1271 fclk_max);
1272 if (ret)
1273 return ret;
1274 }
1275
1276 if (socclk_min && socclk_max) {
1277 ret = yellow_carp_set_soft_freq_limited_range(smu,
1278 SMU_SOCCLK,
1279 socclk_min,
1280 socclk_max);
1281 if (ret)
1282 return ret;
1283 }
1284
1285 if (vclk_min && vclk_max) {
1286 ret = yellow_carp_set_soft_freq_limited_range(smu,
1287 SMU_VCLK,
1288 vclk_min,
1289 vclk_max);
1290 if (ret)
1291 return ret;
1292 }
1293
1294 if (dclk_min && dclk_max) {
1295 ret = yellow_carp_set_soft_freq_limited_range(smu,
1296 SMU_DCLK,
1297 dclk_min,
1298 dclk_max);
1299 if (ret)
1300 return ret;
1301 }
1302
1303 return ret;
1304 }
1305
yellow_carp_set_fine_grain_gfx_freq_parameters(struct smu_context * smu)1306 static int yellow_carp_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
1307 {
1308 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
1309
1310 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
1311 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
1312 smu->gfx_actual_hard_min_freq = 0;
1313 smu->gfx_actual_soft_max_freq = 0;
1314
1315 return 0;
1316 }
1317
1318 static const struct pptable_funcs yellow_carp_ppt_funcs = {
1319 .check_fw_status = smu_v13_0_check_fw_status,
1320 .check_fw_version = smu_v13_0_check_fw_version,
1321 .init_smc_tables = yellow_carp_init_smc_tables,
1322 .fini_smc_tables = yellow_carp_fini_smc_tables,
1323 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
1324 .system_features_control = yellow_carp_system_features_control,
1325 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
1326 .send_smc_msg = smu_cmn_send_smc_msg,
1327 .dpm_set_vcn_enable = yellow_carp_dpm_set_vcn_enable,
1328 .dpm_set_jpeg_enable = yellow_carp_dpm_set_jpeg_enable,
1329 .set_default_dpm_table = yellow_carp_set_default_dpm_tables,
1330 .read_sensor = yellow_carp_read_sensor,
1331 .is_dpm_running = yellow_carp_is_dpm_running,
1332 .set_watermarks_table = yellow_carp_set_watermarks_table,
1333 .get_gpu_metrics = yellow_carp_get_gpu_metrics,
1334 .get_enabled_mask = smu_cmn_get_enabled_mask,
1335 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1336 .set_driver_table_location = smu_v13_0_set_driver_table_location,
1337 .gfx_off_control = smu_v13_0_gfx_off_control,
1338 .get_gfx_off_status = yellow_carp_get_gfxoff_status,
1339 .post_init = yellow_carp_post_smu_init,
1340 .mode2_reset = yellow_carp_mode2_reset,
1341 .get_dpm_ultimate_freq = yellow_carp_get_dpm_ultimate_freq,
1342 .od_edit_dpm_table = yellow_carp_od_edit_dpm_table,
1343 .print_clk_levels = yellow_carp_print_clk_levels,
1344 .force_clk_levels = yellow_carp_force_clk_levels,
1345 .set_performance_level = yellow_carp_set_performance_level,
1346 .set_fine_grain_gfx_freq_parameters = yellow_carp_set_fine_grain_gfx_freq_parameters,
1347 };
1348
yellow_carp_set_ppt_funcs(struct smu_context * smu)1349 void yellow_carp_set_ppt_funcs(struct smu_context *smu)
1350 {
1351 smu->ppt_funcs = &yellow_carp_ppt_funcs;
1352 smu->message_map = yellow_carp_message_map;
1353 smu->feature_map = yellow_carp_feature_mask_map;
1354 smu->table_map = yellow_carp_table_map;
1355 smu->is_apu = true;
1356 smu->smc_driver_if_version = SMU13_YELLOW_CARP_DRIVER_IF_VERSION;
1357 smu_v13_0_set_smu_mailbox_registers(smu);
1358 }
1359