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/qemu/target/ppc/translate/ |
H A D | fixedpoint-impl.c.inc | 8f0a4b6a Tue Jun 01 19:35:28 GMT 2021 Matheus Ferst <matheus.ferst@eldorado.org.br> target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree
Additionally, REQUIRE_64BIT when L=1 to match what is specified in The Programming Environments Manual:
"For 32-bit implementations, the L field must be cleared, otherwise the instruction form is invalid."
Some CPUs are known to deviate from this specification by ignoring the L bit [1]. The stricter behavior, however, can help users that test software with qemu, making it more likely to detect bugs that would otherwise be silent.
If deemed necessary, a future patch can adapt this behavior based on the specific CPU model.
[1] The 601 manual is the only one I've found that explicitly states that the L bit is ignored, but we also observe this behavior in a 7447A v1.2.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-15-matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [dwg: Corrected whitespace error] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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/qemu/target/ppc/ |
H A D | insn32.decode | 8f0a4b6a Tue Jun 01 19:35:28 GMT 2021 Matheus Ferst <matheus.ferst@eldorado.org.br> target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree
Additionally, REQUIRE_64BIT when L=1 to match what is specified in The Programming Environments Manual:
"For 32-bit implementations, the L field must be cleared, otherwise the instruction form is invalid."
Some CPUs are known to deviate from this specification by ignoring the L bit [1]. The stricter behavior, however, can help users that test software with qemu, making it more likely to detect bugs that would otherwise be silent.
If deemed necessary, a future patch can adapt this behavior based on the specific CPU model.
[1] The 601 manual is the only one I've found that explicitly states that the L bit is ignored, but we also observe this behavior in a 7447A v1.2.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-15-matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [dwg: Corrected whitespace error] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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H A D | translate.c | 8f0a4b6a Tue Jun 01 19:35:28 GMT 2021 Matheus Ferst <matheus.ferst@eldorado.org.br> target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree
Additionally, REQUIRE_64BIT when L=1 to match what is specified in The Programming Environments Manual:
"For 32-bit implementations, the L field must be cleared, otherwise the instruction form is invalid."
Some CPUs are known to deviate from this specification by ignoring the L bit [1]. The stricter behavior, however, can help users that test software with qemu, making it more likely to detect bugs that would otherwise be silent.
If deemed necessary, a future patch can adapt this behavior based on the specific CPU model.
[1] The 601 manual is the only one I've found that explicitly states that the L bit is ignored, but we also observe this behavior in a 7447A v1.2.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210601193528.2533031-15-matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [dwg: Corrected whitespace error] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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