/freebsd/sys/amd64/vmm/amd/ |
H A D | npt.h | a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com)
|
H A D | npt.c | a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com)
|
H A D | svm_softc.h | a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com)
|
H A D | vmcb.h | a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com)
|
H A D | amdv.c | a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com)
|
H A D | vmcb.c | a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com)
|
H A D | svm.c | a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com)
|
/freebsd/sys/amd64/vmm/ |
H A D | vmm_instruction_emul.c | a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com)
|
H A D | vmm.c | a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com) a0b78f09 Wed Dec 18 23:39:42 GMT 2013 Peter Grehan <grehan@FreeBSD.org> Enable memory overcommit for AMD processors.
- No emulation of A/D bits is required since AMD-V RVI supports A/D bits. - Enable pmap PT_RVI support(w/o PAT) which is required for memory over-commit support. - Other minor fixes: * Make use of VMCB EXITINTINFO field. If a #VMEXIT happens while delivering an interrupt, EXITINTINFO has all the details that bhyve needs to inject the same interrupt. * SVM h/w decode assist code was incomplete - removed for now. * Some minor code clean-up (more coming).
Submitted by: Anish Gupta (akgupt3@gmail.com)
|