Searched hist:b8cb0864 (Results 1 – 4 of 4) sorted by relevance
/freebsd/sys/arm64/qoriq/clk/ |
H A D | qoriq_clkgen.h | b8cb0864 Mon May 25 14:31:32 GMT 2020 Marcin Wojtas <mw@FreeBSD.org> Add QorIQ platform clockgen driver.
This patch adds classes and functions that can be used with various NXP QorIQ Layerscape SoCs.
As for the clock topology - there is single platform PLL, which supplies clocks for the peripheral bus and additional PLLs for CPU cores. There can be multiple core PLLs (For example - LS1046A has two PLLs - CGAPLL1 and CGAPLL2). Each PLL has fixed dividers on output. The core PLLs are not accessible from dts.
This is a preparation patch for NXP LS1046A SoC support.
Submitted by: Dawid Gorecki <dgr@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D24351 b8cb0864 Mon May 25 14:31:32 GMT 2020 Marcin Wojtas <mw@FreeBSD.org> Add QorIQ platform clockgen driver.
This patch adds classes and functions that can be used with various NXP QorIQ Layerscape SoCs.
As for the clock topology - there is single platform PLL, which supplies clocks for the peripheral bus and additional PLLs for CPU cores. There can be multiple core PLLs (For example - LS1046A has two PLLs - CGAPLL1 and CGAPLL2). Each PLL has fixed dividers on output. The core PLLs are not accessible from dts.
This is a preparation patch for NXP LS1046A SoC support.
Submitted by: Dawid Gorecki <dgr@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D24351 b8cb0864 Mon May 25 14:31:32 GMT 2020 Marcin Wojtas <mw@FreeBSD.org> Add QorIQ platform clockgen driver.
This patch adds classes and functions that can be used with various NXP QorIQ Layerscape SoCs.
As for the clock topology - there is single platform PLL, which supplies clocks for the peripheral bus and additional PLLs for CPU cores. There can be multiple core PLLs (For example - LS1046A has two PLLs - CGAPLL1 and CGAPLL2). Each PLL has fixed dividers on output. The core PLLs are not accessible from dts.
This is a preparation patch for NXP LS1046A SoC support.
Submitted by: Dawid Gorecki <dgr@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D24351 b8cb0864 Mon May 25 14:31:32 GMT 2020 Marcin Wojtas <mw@FreeBSD.org> Add QorIQ platform clockgen driver.
This patch adds classes and functions that can be used with various NXP QorIQ Layerscape SoCs.
As for the clock topology - there is single platform PLL, which supplies clocks for the peripheral bus and additional PLLs for CPU cores. There can be multiple core PLLs (For example - LS1046A has two PLLs - CGAPLL1 and CGAPLL2). Each PLL has fixed dividers on output. The core PLLs are not accessible from dts.
This is a preparation patch for NXP LS1046A SoC support.
Submitted by: Dawid Gorecki <dgr@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D24351 b8cb0864 Mon May 25 14:31:32 GMT 2020 Marcin Wojtas <mw@FreeBSD.org> Add QorIQ platform clockgen driver.
This patch adds classes and functions that can be used with various NXP QorIQ Layerscape SoCs.
As for the clock topology - there is single platform PLL, which supplies clocks for the peripheral bus and additional PLLs for CPU cores. There can be multiple core PLLs (For example - LS1046A has two PLLs - CGAPLL1 and CGAPLL2). Each PLL has fixed dividers on output. The core PLLs are not accessible from dts.
This is a preparation patch for NXP LS1046A SoC support.
Submitted by: Dawid Gorecki <dgr@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D24351 b8cb0864 Mon May 25 14:31:32 GMT 2020 Marcin Wojtas <mw@FreeBSD.org> Add QorIQ platform clockgen driver.
This patch adds classes and functions that can be used with various NXP QorIQ Layerscape SoCs.
As for the clock topology - there is single platform PLL, which supplies clocks for the peripheral bus and additional PLLs for CPU cores. There can be multiple core PLLs (For example - LS1046A has two PLLs - CGAPLL1 and CGAPLL2). Each PLL has fixed dividers on output. The core PLLs are not accessible from dts.
This is a preparation patch for NXP LS1046A SoC support.
Submitted by: Dawid Gorecki <dgr@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D24351 b8cb0864 Mon May 25 14:31:32 GMT 2020 Marcin Wojtas <mw@FreeBSD.org> Add QorIQ platform clockgen driver.
This patch adds classes and functions that can be used with various NXP QorIQ Layerscape SoCs.
As for the clock topology - there is single platform PLL, which supplies clocks for the peripheral bus and additional PLLs for CPU cores. There can be multiple core PLLs (For example - LS1046A has two PLLs - CGAPLL1 and CGAPLL2). Each PLL has fixed dividers on output. The core PLLs are not accessible from dts.
This is a preparation patch for NXP LS1046A SoC support.
Submitted by: Dawid Gorecki <dgr@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D24351
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H A D | qoriq_clk_pll.h | b8cb0864 Mon May 25 14:31:32 GMT 2020 Marcin Wojtas <mw@FreeBSD.org> Add QorIQ platform clockgen driver.
This patch adds classes and functions that can be used with various NXP QorIQ Layerscape SoCs.
As for the clock topology - there is single platform PLL, which supplies clocks for the peripheral bus and additional PLLs for CPU cores. There can be multiple core PLLs (For example - LS1046A has two PLLs - CGAPLL1 and CGAPLL2). Each PLL has fixed dividers on output. The core PLLs are not accessible from dts.
This is a preparation patch for NXP LS1046A SoC support.
Submitted by: Dawid Gorecki <dgr@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D24351 b8cb0864 Mon May 25 14:31:32 GMT 2020 Marcin Wojtas <mw@FreeBSD.org> Add QorIQ platform clockgen driver.
This patch adds classes and functions that can be used with various NXP QorIQ Layerscape SoCs.
As for the clock topology - there is single platform PLL, which supplies clocks for the peripheral bus and additional PLLs for CPU cores. There can be multiple core PLLs (For example - LS1046A has two PLLs - CGAPLL1 and CGAPLL2). Each PLL has fixed dividers on output. The core PLLs are not accessible from dts.
This is a preparation patch for NXP LS1046A SoC support.
Submitted by: Dawid Gorecki <dgr@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D24351 b8cb0864 Mon May 25 14:31:32 GMT 2020 Marcin Wojtas <mw@FreeBSD.org> Add QorIQ platform clockgen driver.
This patch adds classes and functions that can be used with various NXP QorIQ Layerscape SoCs.
As for the clock topology - there is single platform PLL, which supplies clocks for the peripheral bus and additional PLLs for CPU cores. There can be multiple core PLLs (For example - LS1046A has two PLLs - CGAPLL1 and CGAPLL2). Each PLL has fixed dividers on output. The core PLLs are not accessible from dts.
This is a preparation patch for NXP LS1046A SoC support.
Submitted by: Dawid Gorecki <dgr@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D24351 b8cb0864 Mon May 25 14:31:32 GMT 2020 Marcin Wojtas <mw@FreeBSD.org> Add QorIQ platform clockgen driver.
This patch adds classes and functions that can be used with various NXP QorIQ Layerscape SoCs.
As for the clock topology - there is single platform PLL, which supplies clocks for the peripheral bus and additional PLLs for CPU cores. There can be multiple core PLLs (For example - LS1046A has two PLLs - CGAPLL1 and CGAPLL2). Each PLL has fixed dividers on output. The core PLLs are not accessible from dts.
This is a preparation patch for NXP LS1046A SoC support.
Submitted by: Dawid Gorecki <dgr@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D24351 b8cb0864 Mon May 25 14:31:32 GMT 2020 Marcin Wojtas <mw@FreeBSD.org> Add QorIQ platform clockgen driver.
This patch adds classes and functions that can be used with various NXP QorIQ Layerscape SoCs.
As for the clock topology - there is single platform PLL, which supplies clocks for the peripheral bus and additional PLLs for CPU cores. There can be multiple core PLLs (For example - LS1046A has two PLLs - CGAPLL1 and CGAPLL2). Each PLL has fixed dividers on output. The core PLLs are not accessible from dts.
This is a preparation patch for NXP LS1046A SoC support.
Submitted by: Dawid Gorecki <dgr@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D24351 b8cb0864 Mon May 25 14:31:32 GMT 2020 Marcin Wojtas <mw@FreeBSD.org> Add QorIQ platform clockgen driver.
This patch adds classes and functions that can be used with various NXP QorIQ Layerscape SoCs.
As for the clock topology - there is single platform PLL, which supplies clocks for the peripheral bus and additional PLLs for CPU cores. There can be multiple core PLLs (For example - LS1046A has two PLLs - CGAPLL1 and CGAPLL2). Each PLL has fixed dividers on output. The core PLLs are not accessible from dts.
This is a preparation patch for NXP LS1046A SoC support.
Submitted by: Dawid Gorecki <dgr@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D24351 b8cb0864 Mon May 25 14:31:32 GMT 2020 Marcin Wojtas <mw@FreeBSD.org> Add QorIQ platform clockgen driver.
This patch adds classes and functions that can be used with various NXP QorIQ Layerscape SoCs.
As for the clock topology - there is single platform PLL, which supplies clocks for the peripheral bus and additional PLLs for CPU cores. There can be multiple core PLLs (For example - LS1046A has two PLLs - CGAPLL1 and CGAPLL2). Each PLL has fixed dividers on output. The core PLLs are not accessible from dts.
This is a preparation patch for NXP LS1046A SoC support.
Submitted by: Dawid Gorecki <dgr@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D24351
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H A D | qoriq_clk_pll.c | b8cb0864 Mon May 25 14:31:32 GMT 2020 Marcin Wojtas <mw@FreeBSD.org> Add QorIQ platform clockgen driver.
This patch adds classes and functions that can be used with various NXP QorIQ Layerscape SoCs.
As for the clock topology - there is single platform PLL, which supplies clocks for the peripheral bus and additional PLLs for CPU cores. There can be multiple core PLLs (For example - LS1046A has two PLLs - CGAPLL1 and CGAPLL2). Each PLL has fixed dividers on output. The core PLLs are not accessible from dts.
This is a preparation patch for NXP LS1046A SoC support.
Submitted by: Dawid Gorecki <dgr@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D24351 b8cb0864 Mon May 25 14:31:32 GMT 2020 Marcin Wojtas <mw@FreeBSD.org> Add QorIQ platform clockgen driver.
This patch adds classes and functions that can be used with various NXP QorIQ Layerscape SoCs.
As for the clock topology - there is single platform PLL, which supplies clocks for the peripheral bus and additional PLLs for CPU cores. There can be multiple core PLLs (For example - LS1046A has two PLLs - CGAPLL1 and CGAPLL2). Each PLL has fixed dividers on output. The core PLLs are not accessible from dts.
This is a preparation patch for NXP LS1046A SoC support.
Submitted by: Dawid Gorecki <dgr@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D24351 b8cb0864 Mon May 25 14:31:32 GMT 2020 Marcin Wojtas <mw@FreeBSD.org> Add QorIQ platform clockgen driver.
This patch adds classes and functions that can be used with various NXP QorIQ Layerscape SoCs.
As for the clock topology - there is single platform PLL, which supplies clocks for the peripheral bus and additional PLLs for CPU cores. There can be multiple core PLLs (For example - LS1046A has two PLLs - CGAPLL1 and CGAPLL2). Each PLL has fixed dividers on output. The core PLLs are not accessible from dts.
This is a preparation patch for NXP LS1046A SoC support.
Submitted by: Dawid Gorecki <dgr@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D24351 b8cb0864 Mon May 25 14:31:32 GMT 2020 Marcin Wojtas <mw@FreeBSD.org> Add QorIQ platform clockgen driver.
This patch adds classes and functions that can be used with various NXP QorIQ Layerscape SoCs.
As for the clock topology - there is single platform PLL, which supplies clocks for the peripheral bus and additional PLLs for CPU cores. There can be multiple core PLLs (For example - LS1046A has two PLLs - CGAPLL1 and CGAPLL2). Each PLL has fixed dividers on output. The core PLLs are not accessible from dts.
This is a preparation patch for NXP LS1046A SoC support.
Submitted by: Dawid Gorecki <dgr@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D24351 b8cb0864 Mon May 25 14:31:32 GMT 2020 Marcin Wojtas <mw@FreeBSD.org> Add QorIQ platform clockgen driver.
This patch adds classes and functions that can be used with various NXP QorIQ Layerscape SoCs.
As for the clock topology - there is single platform PLL, which supplies clocks for the peripheral bus and additional PLLs for CPU cores. There can be multiple core PLLs (For example - LS1046A has two PLLs - CGAPLL1 and CGAPLL2). Each PLL has fixed dividers on output. The core PLLs are not accessible from dts.
This is a preparation patch for NXP LS1046A SoC support.
Submitted by: Dawid Gorecki <dgr@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D24351 b8cb0864 Mon May 25 14:31:32 GMT 2020 Marcin Wojtas <mw@FreeBSD.org> Add QorIQ platform clockgen driver.
This patch adds classes and functions that can be used with various NXP QorIQ Layerscape SoCs.
As for the clock topology - there is single platform PLL, which supplies clocks for the peripheral bus and additional PLLs for CPU cores. There can be multiple core PLLs (For example - LS1046A has two PLLs - CGAPLL1 and CGAPLL2). Each PLL has fixed dividers on output. The core PLLs are not accessible from dts.
This is a preparation patch for NXP LS1046A SoC support.
Submitted by: Dawid Gorecki <dgr@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D24351 b8cb0864 Mon May 25 14:31:32 GMT 2020 Marcin Wojtas <mw@FreeBSD.org> Add QorIQ platform clockgen driver.
This patch adds classes and functions that can be used with various NXP QorIQ Layerscape SoCs.
As for the clock topology - there is single platform PLL, which supplies clocks for the peripheral bus and additional PLLs for CPU cores. There can be multiple core PLLs (For example - LS1046A has two PLLs - CGAPLL1 and CGAPLL2). Each PLL has fixed dividers on output. The core PLLs are not accessible from dts.
This is a preparation patch for NXP LS1046A SoC support.
Submitted by: Dawid Gorecki <dgr@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D24351
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H A D | qoriq_clkgen.c | b8cb0864 Mon May 25 14:31:32 GMT 2020 Marcin Wojtas <mw@FreeBSD.org> Add QorIQ platform clockgen driver.
This patch adds classes and functions that can be used with various NXP QorIQ Layerscape SoCs.
As for the clock topology - there is single platform PLL, which supplies clocks for the peripheral bus and additional PLLs for CPU cores. There can be multiple core PLLs (For example - LS1046A has two PLLs - CGAPLL1 and CGAPLL2). Each PLL has fixed dividers on output. The core PLLs are not accessible from dts.
This is a preparation patch for NXP LS1046A SoC support.
Submitted by: Dawid Gorecki <dgr@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D24351 b8cb0864 Mon May 25 14:31:32 GMT 2020 Marcin Wojtas <mw@FreeBSD.org> Add QorIQ platform clockgen driver.
This patch adds classes and functions that can be used with various NXP QorIQ Layerscape SoCs.
As for the clock topology - there is single platform PLL, which supplies clocks for the peripheral bus and additional PLLs for CPU cores. There can be multiple core PLLs (For example - LS1046A has two PLLs - CGAPLL1 and CGAPLL2). Each PLL has fixed dividers on output. The core PLLs are not accessible from dts.
This is a preparation patch for NXP LS1046A SoC support.
Submitted by: Dawid Gorecki <dgr@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D24351 b8cb0864 Mon May 25 14:31:32 GMT 2020 Marcin Wojtas <mw@FreeBSD.org> Add QorIQ platform clockgen driver.
This patch adds classes and functions that can be used with various NXP QorIQ Layerscape SoCs.
As for the clock topology - there is single platform PLL, which supplies clocks for the peripheral bus and additional PLLs for CPU cores. There can be multiple core PLLs (For example - LS1046A has two PLLs - CGAPLL1 and CGAPLL2). Each PLL has fixed dividers on output. The core PLLs are not accessible from dts.
This is a preparation patch for NXP LS1046A SoC support.
Submitted by: Dawid Gorecki <dgr@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D24351 b8cb0864 Mon May 25 14:31:32 GMT 2020 Marcin Wojtas <mw@FreeBSD.org> Add QorIQ platform clockgen driver.
This patch adds classes and functions that can be used with various NXP QorIQ Layerscape SoCs.
As for the clock topology - there is single platform PLL, which supplies clocks for the peripheral bus and additional PLLs for CPU cores. There can be multiple core PLLs (For example - LS1046A has two PLLs - CGAPLL1 and CGAPLL2). Each PLL has fixed dividers on output. The core PLLs are not accessible from dts.
This is a preparation patch for NXP LS1046A SoC support.
Submitted by: Dawid Gorecki <dgr@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D24351 b8cb0864 Mon May 25 14:31:32 GMT 2020 Marcin Wojtas <mw@FreeBSD.org> Add QorIQ platform clockgen driver.
This patch adds classes and functions that can be used with various NXP QorIQ Layerscape SoCs.
As for the clock topology - there is single platform PLL, which supplies clocks for the peripheral bus and additional PLLs for CPU cores. There can be multiple core PLLs (For example - LS1046A has two PLLs - CGAPLL1 and CGAPLL2). Each PLL has fixed dividers on output. The core PLLs are not accessible from dts.
This is a preparation patch for NXP LS1046A SoC support.
Submitted by: Dawid Gorecki <dgr@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D24351 b8cb0864 Mon May 25 14:31:32 GMT 2020 Marcin Wojtas <mw@FreeBSD.org> Add QorIQ platform clockgen driver.
This patch adds classes and functions that can be used with various NXP QorIQ Layerscape SoCs.
As for the clock topology - there is single platform PLL, which supplies clocks for the peripheral bus and additional PLLs for CPU cores. There can be multiple core PLLs (For example - LS1046A has two PLLs - CGAPLL1 and CGAPLL2). Each PLL has fixed dividers on output. The core PLLs are not accessible from dts.
This is a preparation patch for NXP LS1046A SoC support.
Submitted by: Dawid Gorecki <dgr@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D24351 b8cb0864 Mon May 25 14:31:32 GMT 2020 Marcin Wojtas <mw@FreeBSD.org> Add QorIQ platform clockgen driver.
This patch adds classes and functions that can be used with various NXP QorIQ Layerscape SoCs.
As for the clock topology - there is single platform PLL, which supplies clocks for the peripheral bus and additional PLLs for CPU cores. There can be multiple core PLLs (For example - LS1046A has two PLLs - CGAPLL1 and CGAPLL2). Each PLL has fixed dividers on output. The core PLLs are not accessible from dts.
This is a preparation patch for NXP LS1046A SoC support.
Submitted by: Dawid Gorecki <dgr@semihalf.com> Reviewed by: mmel Obtained from: Semihalf Sponsored by: Alstom Group Differential Revision: https://reviews.freebsd.org/D24351
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