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/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h17 #ifndef BIT
18 #define BIT(nr) (1 << (nr)) macro
642 #define MISC_INT_DMA BIT(7)
643 #define MISC_INT_OHCI BIT(6)
644 #define MISC_INT_PERFC BIT(5)
645 #define MISC_INT_WDOG BIT(4)
646 #define MISC_INT_UART BIT(3)
647 #define MISC_INT_GPIO BIT(2)
648 #define MISC_INT_ERROR BIT(1)
649 #define MISC_INT_TIMER BIT(0)
[all …]
/dports/sysutils/u-boot-sifive-fu540/u-boot-2021.07/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h17 #ifndef BIT
18 #define BIT(nr) (1 << (nr)) macro
642 #define MISC_INT_DMA BIT(7)
643 #define MISC_INT_OHCI BIT(6)
644 #define MISC_INT_PERFC BIT(5)
645 #define MISC_INT_WDOG BIT(4)
646 #define MISC_INT_UART BIT(3)
647 #define MISC_INT_GPIO BIT(2)
648 #define MISC_INT_ERROR BIT(1)
649 #define MISC_INT_TIMER BIT(0)
[all …]
/dports/sysutils/u-boot-rpi4/u-boot-2021.07/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h17 #ifndef BIT
18 #define BIT(nr) (1 << (nr)) macro
642 #define MISC_INT_DMA BIT(7)
643 #define MISC_INT_OHCI BIT(6)
644 #define MISC_INT_PERFC BIT(5)
645 #define MISC_INT_WDOG BIT(4)
646 #define MISC_INT_UART BIT(3)
647 #define MISC_INT_GPIO BIT(2)
648 #define MISC_INT_ERROR BIT(1)
649 #define MISC_INT_TIMER BIT(0)
[all …]
/dports/sysutils/u-boot-rpi3-32/u-boot-2021.07/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h17 #ifndef BIT
18 #define BIT(nr) (1 << (nr)) macro
642 #define MISC_INT_DMA BIT(7)
643 #define MISC_INT_OHCI BIT(6)
644 #define MISC_INT_PERFC BIT(5)
645 #define MISC_INT_WDOG BIT(4)
646 #define MISC_INT_UART BIT(3)
647 #define MISC_INT_GPIO BIT(2)
648 #define MISC_INT_ERROR BIT(1)
649 #define MISC_INT_TIMER BIT(0)
[all …]
/dports/sysutils/u-boot-rockpro64/u-boot-2021.07/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h17 #ifndef BIT
18 #define BIT(nr) (1 << (nr)) macro
642 #define MISC_INT_DMA BIT(7)
643 #define MISC_INT_OHCI BIT(6)
644 #define MISC_INT_PERFC BIT(5)
645 #define MISC_INT_WDOG BIT(4)
646 #define MISC_INT_UART BIT(3)
647 #define MISC_INT_GPIO BIT(2)
648 #define MISC_INT_ERROR BIT(1)
649 #define MISC_INT_TIMER BIT(0)
[all …]
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h17 #ifndef BIT
18 #define BIT(nr) (1 << (nr)) macro
642 #define MISC_INT_DMA BIT(7)
643 #define MISC_INT_OHCI BIT(6)
644 #define MISC_INT_PERFC BIT(5)
645 #define MISC_INT_WDOG BIT(4)
646 #define MISC_INT_UART BIT(3)
647 #define MISC_INT_GPIO BIT(2)
648 #define MISC_INT_ERROR BIT(1)
649 #define MISC_INT_TIMER BIT(0)
[all …]
/dports/sysutils/u-boot-qemu-riscv64/u-boot-2021.07/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h17 #ifndef BIT
18 #define BIT(nr) (1 << (nr)) macro
642 #define MISC_INT_DMA BIT(7)
643 #define MISC_INT_OHCI BIT(6)
644 #define MISC_INT_PERFC BIT(5)
645 #define MISC_INT_WDOG BIT(4)
646 #define MISC_INT_UART BIT(3)
647 #define MISC_INT_GPIO BIT(2)
648 #define MISC_INT_ERROR BIT(1)
649 #define MISC_INT_TIMER BIT(0)
[all …]
/dports/sysutils/u-boot-qemu-arm/u-boot-2021.07/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h17 #ifndef BIT
18 #define BIT(nr) (1 << (nr)) macro
642 #define MISC_INT_DMA BIT(7)
643 #define MISC_INT_OHCI BIT(6)
644 #define MISC_INT_PERFC BIT(5)
645 #define MISC_INT_WDOG BIT(4)
646 #define MISC_INT_UART BIT(3)
647 #define MISC_INT_GPIO BIT(2)
648 #define MISC_INT_ERROR BIT(1)
649 #define MISC_INT_TIMER BIT(0)
[all …]
/dports/sysutils/u-boot-rpi/u-boot-2021.07/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h17 #ifndef BIT
18 #define BIT(nr) (1 << (nr)) macro
642 #define MISC_INT_DMA BIT(7)
643 #define MISC_INT_OHCI BIT(6)
644 #define MISC_INT_PERFC BIT(5)
645 #define MISC_INT_WDOG BIT(4)
646 #define MISC_INT_UART BIT(3)
647 #define MISC_INT_GPIO BIT(2)
648 #define MISC_INT_ERROR BIT(1)
649 #define MISC_INT_TIMER BIT(0)
[all …]
/dports/sysutils/u-boot-rpi-arm64/u-boot-2021.07/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h17 #ifndef BIT
18 #define BIT(nr) (1 << (nr)) macro
642 #define MISC_INT_DMA BIT(7)
643 #define MISC_INT_OHCI BIT(6)
644 #define MISC_INT_PERFC BIT(5)
645 #define MISC_INT_WDOG BIT(4)
646 #define MISC_INT_UART BIT(3)
647 #define MISC_INT_GPIO BIT(2)
648 #define MISC_INT_ERROR BIT(1)
649 #define MISC_INT_TIMER BIT(0)
[all …]
/dports/sysutils/u-boot-rpi2/u-boot-2021.07/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h17 #ifndef BIT
18 #define BIT(nr) (1 << (nr)) macro
642 #define MISC_INT_DMA BIT(7)
643 #define MISC_INT_OHCI BIT(6)
644 #define MISC_INT_PERFC BIT(5)
645 #define MISC_INT_WDOG BIT(4)
646 #define MISC_INT_UART BIT(3)
647 #define MISC_INT_GPIO BIT(2)
648 #define MISC_INT_ERROR BIT(1)
649 #define MISC_INT_TIMER BIT(0)
[all …]
/dports/sysutils/u-boot-riotboard/u-boot-2021.07/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h17 #ifndef BIT
18 #define BIT(nr) (1 << (nr)) macro
642 #define MISC_INT_DMA BIT(7)
643 #define MISC_INT_OHCI BIT(6)
644 #define MISC_INT_PERFC BIT(5)
645 #define MISC_INT_WDOG BIT(4)
646 #define MISC_INT_UART BIT(3)
647 #define MISC_INT_GPIO BIT(2)
648 #define MISC_INT_ERROR BIT(1)
649 #define MISC_INT_TIMER BIT(0)
[all …]
/dports/sysutils/u-boot-rpi3/u-boot-2021.07/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h17 #ifndef BIT
18 #define BIT(nr) (1 << (nr)) macro
642 #define MISC_INT_DMA BIT(7)
643 #define MISC_INT_OHCI BIT(6)
644 #define MISC_INT_PERFC BIT(5)
645 #define MISC_INT_WDOG BIT(4)
646 #define MISC_INT_UART BIT(3)
647 #define MISC_INT_GPIO BIT(2)
648 #define MISC_INT_ERROR BIT(1)
649 #define MISC_INT_TIMER BIT(0)
[all …]
/dports/sysutils/u-boot-rock-pi-4/u-boot-2021.07/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h17 #ifndef BIT
18 #define BIT(nr) (1 << (nr)) macro
642 #define MISC_INT_DMA BIT(7)
643 #define MISC_INT_OHCI BIT(6)
644 #define MISC_INT_PERFC BIT(5)
645 #define MISC_INT_WDOG BIT(4)
646 #define MISC_INT_UART BIT(3)
647 #define MISC_INT_GPIO BIT(2)
648 #define MISC_INT_ERROR BIT(1)
649 #define MISC_INT_TIMER BIT(0)
[all …]
/dports/sysutils/u-boot-rock64/u-boot-2021.07/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h17 #ifndef BIT
18 #define BIT(nr) (1 << (nr)) macro
642 #define MISC_INT_DMA BIT(7)
643 #define MISC_INT_OHCI BIT(6)
644 #define MISC_INT_PERFC BIT(5)
645 #define MISC_INT_WDOG BIT(4)
646 #define MISC_INT_UART BIT(3)
647 #define MISC_INT_GPIO BIT(2)
648 #define MISC_INT_ERROR BIT(1)
649 #define MISC_INT_TIMER BIT(0)
[all …]
/dports/emulators/qemu/qemu-6.2.0/include/hw/usb/
H A Ddwc2-regs.h59 #define GOTGCTL_HNPREQ BIT(9)
61 #define GOTGCTL_SESREQ BIT(1)
169 #define GINTSTS_SOF BIT(3)
217 #define GI2CCTL_RW BIT(30)
222 #define GI2CCTL_ACK BIT(24)
742 #define HPRT0_PWR BIT(12)
745 #define HPRT0_RST BIT(8)
746 #define HPRT0_SUSP BIT(7)
747 #define HPRT0_RES BIT(6)
751 #define HPRT0_ENA BIT(2)
[all …]
/dports/emulators/qemu60/qemu-6.0.0/include/hw/usb/
H A Ddwc2-regs.h59 #define GOTGCTL_HNPREQ BIT(9)
61 #define GOTGCTL_SESREQ BIT(1)
169 #define GINTSTS_SOF BIT(3)
217 #define GI2CCTL_RW BIT(30)
222 #define GI2CCTL_ACK BIT(24)
742 #define HPRT0_PWR BIT(12)
745 #define HPRT0_RST BIT(8)
746 #define HPRT0_SUSP BIT(7)
747 #define HPRT0_RES BIT(6)
751 #define HPRT0_ENA BIT(2)
[all …]
/dports/emulators/qemu5/qemu-5.2.0/include/hw/usb/
H A Ddwc2-regs.h59 #define GOTGCTL_HNPREQ BIT(9)
61 #define GOTGCTL_SESREQ BIT(1)
169 #define GINTSTS_SOF BIT(3)
217 #define GI2CCTL_RW BIT(30)
222 #define GI2CCTL_ACK BIT(24)
742 #define HPRT0_PWR BIT(12)
745 #define HPRT0_RST BIT(8)
746 #define HPRT0_SUSP BIT(7)
747 #define HPRT0_RES BIT(6)
751 #define HPRT0_ENA BIT(2)
[all …]
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/include/hw/usb/
H A Ddwc2-regs.h59 #define GOTGCTL_HNPREQ BIT(9)
61 #define GOTGCTL_SESREQ BIT(1)
169 #define GINTSTS_SOF BIT(3)
217 #define GI2CCTL_RW BIT(30)
222 #define GI2CCTL_ACK BIT(24)
742 #define HPRT0_PWR BIT(12)
745 #define HPRT0_RST BIT(8)
746 #define HPRT0_SUSP BIT(7)
747 #define HPRT0_RES BIT(6)
751 #define HPRT0_ENA BIT(2)
[all …]
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/net/dsa/microchip/
H A Dksz9477_reg.h44 #define PME_ENABLE BIT(1)
45 #define PME_POLARITY BIT(0)
51 #define SW_AVB_ABLE BIT(4)
69 #define SW_QW_ABLE BIT(5)
75 #define LUE_INT BIT(31)
76 #define TRIG_TS_INT BIT(30)
168 #define SW_RESET BIT(1)
169 #define SW_START BIT(0)
605 #define GPIO_IN BIT(7)
606 #define GPIO_OUT BIT(6)
[all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/net/dsa/microchip/
H A Dksz9477_reg.h44 #define PME_ENABLE BIT(1)
45 #define PME_POLARITY BIT(0)
51 #define SW_AVB_ABLE BIT(4)
69 #define SW_QW_ABLE BIT(5)
75 #define LUE_INT BIT(31)
76 #define TRIG_TS_INT BIT(30)
168 #define SW_RESET BIT(1)
169 #define SW_START BIT(0)
605 #define GPIO_IN BIT(7)
606 #define GPIO_OUT BIT(6)
[all …]
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/net/dsa/microchip/
H A Dksz9477_reg.h44 #define PME_ENABLE BIT(1)
45 #define PME_POLARITY BIT(0)
51 #define SW_AVB_ABLE BIT(4)
69 #define SW_QW_ABLE BIT(5)
75 #define LUE_INT BIT(31)
76 #define TRIG_TS_INT BIT(30)
168 #define SW_RESET BIT(1)
169 #define SW_START BIT(0)
605 #define GPIO_IN BIT(7)
606 #define GPIO_OUT BIT(6)
[all …]
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h17 #ifndef BIT
18 #define BIT(nr) (1 << (nr)) macro
616 #define MISC_INT_DMA BIT(7)
617 #define MISC_INT_OHCI BIT(6)
618 #define MISC_INT_PERFC BIT(5)
619 #define MISC_INT_WDOG BIT(4)
620 #define MISC_INT_UART BIT(3)
621 #define MISC_INT_GPIO BIT(2)
622 #define MISC_INT_ERROR BIT(1)
623 #define MISC_INT_TIMER BIT(0)
[all …]
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h17 #ifndef BIT
18 #define BIT(nr) (1 << (nr)) macro
616 #define MISC_INT_DMA BIT(7)
617 #define MISC_INT_OHCI BIT(6)
618 #define MISC_INT_PERFC BIT(5)
619 #define MISC_INT_WDOG BIT(4)
620 #define MISC_INT_UART BIT(3)
621 #define MISC_INT_GPIO BIT(2)
622 #define MISC_INT_ERROR BIT(1)
623 #define MISC_INT_TIMER BIT(0)
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h17 #ifndef BIT
18 #define BIT(nr) (1 << (nr)) macro
616 #define MISC_INT_DMA BIT(7)
617 #define MISC_INT_OHCI BIT(6)
618 #define MISC_INT_PERFC BIT(5)
619 #define MISC_INT_WDOG BIT(4)
620 #define MISC_INT_UART BIT(3)
621 #define MISC_INT_GPIO BIT(2)
622 #define MISC_INT_ERROR BIT(1)
623 #define MISC_INT_TIMER BIT(0)
[all …]

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