| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/mips/mach-ath79/include/mach/ |
| H A D | ar71xx_regs.h | 17 #ifndef BIT
18 #define BIT(nr) (1 << (nr)) macro
616 #define MISC_INT_DMA BIT(7)
617 #define MISC_INT_OHCI BIT(6)
618 #define MISC_INT_PERFC BIT(5)
619 #define MISC_INT_WDOG BIT(4)
620 #define MISC_INT_UART BIT(3)
621 #define MISC_INT_GPIO BIT(2)
622 #define MISC_INT_ERROR BIT(1)
623 #define MISC_INT_TIMER BIT(0)
[all …]
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| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/arch/mips/mach-ath79/include/mach/ |
| H A D | ar71xx_regs.h | 17 #ifndef BIT
18 #define BIT(nr) (1 << (nr)) macro
616 #define MISC_INT_DMA BIT(7)
617 #define MISC_INT_OHCI BIT(6)
618 #define MISC_INT_PERFC BIT(5)
619 #define MISC_INT_WDOG BIT(4)
620 #define MISC_INT_UART BIT(3)
621 #define MISC_INT_GPIO BIT(2)
622 #define MISC_INT_ERROR BIT(1)
623 #define MISC_INT_TIMER BIT(0)
[all …]
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| /dports/multimedia/libv4l/linux-5.13-rc2/drivers/comedi/drivers/ |
| H A D | ni_stc.h | 26 #define NISTC_INTA_ACK_G0_TC BIT(14)
27 #define NISTC_INTA_ACK_AI_ERR BIT(13)
144 #define NISTC_DIO_SDIN BIT(4)
145 #define NISTC_DIO_SDOUT BIT(0)
256 #define NISTC_RTSI_TRIG_DIR(_c, _m) ((_m) ? BIT(8 + (_c)) : BIT(7 + (_c)))
360 #define NISTC_RESET_G1 BIT(3)
361 #define NISTC_RESET_G0 BIT(2)
362 #define NISTC_RESET_AO BIT(1)
363 #define NISTC_RESET_AI BIT(0)
671 #define CS5529_CMD_CB BIT(7)
[all …]
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| /dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/comedi/drivers/ |
| H A D | ni_stc.h | 26 #define NISTC_INTA_ACK_G0_TC BIT(14)
27 #define NISTC_INTA_ACK_AI_ERR BIT(13)
144 #define NISTC_DIO_SDIN BIT(4)
145 #define NISTC_DIO_SDOUT BIT(0)
256 #define NISTC_RTSI_TRIG_DIR(_c, _m) ((_m) ? BIT(8 + (_c)) : BIT(7 + (_c)))
360 #define NISTC_RESET_G1 BIT(3)
361 #define NISTC_RESET_G0 BIT(2)
362 #define NISTC_RESET_AO BIT(1)
363 #define NISTC_RESET_AI BIT(0)
671 #define CS5529_CMD_CB BIT(7)
[all …]
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| /dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/comedi/drivers/ |
| H A D | ni_stc.h | 26 #define NISTC_INTA_ACK_G0_TC BIT(14)
27 #define NISTC_INTA_ACK_AI_ERR BIT(13)
144 #define NISTC_DIO_SDIN BIT(4)
145 #define NISTC_DIO_SDOUT BIT(0)
256 #define NISTC_RTSI_TRIG_DIR(_c, _m) ((_m) ? BIT(8 + (_c)) : BIT(7 + (_c)))
360 #define NISTC_RESET_G1 BIT(3)
361 #define NISTC_RESET_G0 BIT(2)
362 #define NISTC_RESET_AO BIT(1)
363 #define NISTC_RESET_AI BIT(0)
671 #define CS5529_CMD_CB BIT(7)
[all …]
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| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/mips/mach-jz47xx/jz4780/ |
| H A D | timer.c | 40 #define TCU_TCSR_PWM_SD BIT(9)
42 #define TCU_TCSR_PWM_EN BIT(7)
55 #define TCU_TER_TCEN5 BIT(5)
56 #define TCU_TER_TCEN4 BIT(4)
57 #define TCU_TER_TCEN3 BIT(3)
58 #define TCU_TER_TCEN2 BIT(2)
59 #define TCU_TER_TCEN1 BIT(1)
60 #define TCU_TER_TCEN0 BIT(0)
62 #define TCU_TESR_TCST5 BIT(5)
178 #define TER_OSTEN BIT(15)
[all …]
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| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/mips/mach-jz47xx/jz4780/ |
| H A D | timer.c | 40 #define TCU_TCSR_PWM_SD BIT(9)
42 #define TCU_TCSR_PWM_EN BIT(7)
55 #define TCU_TER_TCEN5 BIT(5)
56 #define TCU_TER_TCEN4 BIT(4)
57 #define TCU_TER_TCEN3 BIT(3)
58 #define TCU_TER_TCEN2 BIT(2)
59 #define TCU_TER_TCEN1 BIT(1)
60 #define TCU_TER_TCEN0 BIT(0)
62 #define TCU_TESR_TCST5 BIT(5)
178 #define TER_OSTEN BIT(15)
[all …]
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| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
| H A D | timer.c | 45 #define TCU_TCSR_PWM_SD BIT(9)
60 #define TCU_TER_TCEN5 BIT(5)
61 #define TCU_TER_TCEN4 BIT(4)
62 #define TCU_TER_TCEN3 BIT(3)
63 #define TCU_TER_TCEN2 BIT(2)
64 #define TCU_TER_TCEN1 BIT(1)
65 #define TCU_TER_TCEN0 BIT(0)
67 #define TCU_TESR_TCST5 BIT(5)
68 #define TCU_TESR_TCST4 BIT(4)
183 #define TER_OSTEN BIT(15)
[all …]
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| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
| H A D | timer.c | 45 #define TCU_TCSR_PWM_SD BIT(9)
60 #define TCU_TER_TCEN5 BIT(5)
61 #define TCU_TER_TCEN4 BIT(4)
62 #define TCU_TER_TCEN3 BIT(3)
63 #define TCU_TER_TCEN2 BIT(2)
64 #define TCU_TER_TCEN1 BIT(1)
65 #define TCU_TER_TCEN0 BIT(0)
67 #define TCU_TESR_TCST5 BIT(5)
68 #define TCU_TESR_TCST4 BIT(4)
183 #define TER_OSTEN BIT(15)
[all …]
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| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
| H A D | timer.c | 45 #define TCU_TCSR_PWM_SD BIT(9)
60 #define TCU_TER_TCEN5 BIT(5)
61 #define TCU_TER_TCEN4 BIT(4)
62 #define TCU_TER_TCEN3 BIT(3)
63 #define TCU_TER_TCEN2 BIT(2)
64 #define TCU_TER_TCEN1 BIT(1)
65 #define TCU_TER_TCEN0 BIT(0)
67 #define TCU_TESR_TCST5 BIT(5)
68 #define TCU_TESR_TCST4 BIT(4)
183 #define TER_OSTEN BIT(15)
[all …]
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| /dports/sysutils/u-boot-chip/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
| H A D | timer.c | 45 #define TCU_TCSR_PWM_SD BIT(9)
60 #define TCU_TER_TCEN5 BIT(5)
61 #define TCU_TER_TCEN4 BIT(4)
62 #define TCU_TER_TCEN3 BIT(3)
63 #define TCU_TER_TCEN2 BIT(2)
64 #define TCU_TER_TCEN1 BIT(1)
65 #define TCU_TER_TCEN0 BIT(0)
67 #define TCU_TESR_TCST5 BIT(5)
68 #define TCU_TESR_TCST4 BIT(4)
183 #define TER_OSTEN BIT(15)
[all …]
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| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/mips/mach-jz47xx/jz4780/ |
| H A D | timer.c | 40 #define TCU_TCSR_PWM_SD BIT(9)
42 #define TCU_TCSR_PWM_EN BIT(7)
55 #define TCU_TER_TCEN5 BIT(5)
56 #define TCU_TER_TCEN4 BIT(4)
57 #define TCU_TER_TCEN3 BIT(3)
58 #define TCU_TER_TCEN2 BIT(2)
59 #define TCU_TER_TCEN1 BIT(1)
60 #define TCU_TER_TCEN0 BIT(0)
62 #define TCU_TESR_TCST5 BIT(5)
178 #define TER_OSTEN BIT(15)
[all …]
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| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
| H A D | timer.c | 45 #define TCU_TCSR_PWM_SD BIT(9)
60 #define TCU_TER_TCEN5 BIT(5)
61 #define TCU_TER_TCEN4 BIT(4)
62 #define TCU_TER_TCEN3 BIT(3)
63 #define TCU_TER_TCEN2 BIT(2)
64 #define TCU_TER_TCEN1 BIT(1)
65 #define TCU_TER_TCEN0 BIT(0)
67 #define TCU_TESR_TCST5 BIT(5)
68 #define TCU_TESR_TCST4 BIT(4)
183 #define TER_OSTEN BIT(15)
[all …]
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| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
| H A D | timer.c | 45 #define TCU_TCSR_PWM_SD BIT(9)
60 #define TCU_TER_TCEN5 BIT(5)
61 #define TCU_TER_TCEN4 BIT(4)
62 #define TCU_TER_TCEN3 BIT(3)
63 #define TCU_TER_TCEN2 BIT(2)
64 #define TCU_TER_TCEN1 BIT(1)
65 #define TCU_TER_TCEN0 BIT(0)
67 #define TCU_TESR_TCST5 BIT(5)
68 #define TCU_TESR_TCST4 BIT(4)
183 #define TER_OSTEN BIT(15)
[all …]
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| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
| H A D | timer.c | 45 #define TCU_TCSR_PWM_SD BIT(9)
60 #define TCU_TER_TCEN5 BIT(5)
61 #define TCU_TER_TCEN4 BIT(4)
62 #define TCU_TER_TCEN3 BIT(3)
63 #define TCU_TER_TCEN2 BIT(2)
64 #define TCU_TER_TCEN1 BIT(1)
65 #define TCU_TER_TCEN0 BIT(0)
67 #define TCU_TESR_TCST5 BIT(5)
68 #define TCU_TESR_TCST4 BIT(4)
183 #define TER_OSTEN BIT(15)
[all …]
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| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
| H A D | timer.c | 45 #define TCU_TCSR_PWM_SD BIT(9)
60 #define TCU_TER_TCEN5 BIT(5)
61 #define TCU_TER_TCEN4 BIT(4)
62 #define TCU_TER_TCEN3 BIT(3)
63 #define TCU_TER_TCEN2 BIT(2)
64 #define TCU_TER_TCEN1 BIT(1)
65 #define TCU_TER_TCEN0 BIT(0)
67 #define TCU_TESR_TCST5 BIT(5)
68 #define TCU_TESR_TCST4 BIT(4)
183 #define TER_OSTEN BIT(15)
[all …]
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| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
| H A D | timer.c | 45 #define TCU_TCSR_PWM_SD BIT(9)
60 #define TCU_TER_TCEN5 BIT(5)
61 #define TCU_TER_TCEN4 BIT(4)
62 #define TCU_TER_TCEN3 BIT(3)
63 #define TCU_TER_TCEN2 BIT(2)
64 #define TCU_TER_TCEN1 BIT(1)
65 #define TCU_TER_TCEN0 BIT(0)
67 #define TCU_TESR_TCST5 BIT(5)
68 #define TCU_TESR_TCST4 BIT(4)
183 #define TER_OSTEN BIT(15)
[all …]
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| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
| H A D | timer.c | 45 #define TCU_TCSR_PWM_SD BIT(9)
60 #define TCU_TER_TCEN5 BIT(5)
61 #define TCU_TER_TCEN4 BIT(4)
62 #define TCU_TER_TCEN3 BIT(3)
63 #define TCU_TER_TCEN2 BIT(2)
64 #define TCU_TER_TCEN1 BIT(1)
65 #define TCU_TER_TCEN0 BIT(0)
67 #define TCU_TESR_TCST5 BIT(5)
68 #define TCU_TESR_TCST4 BIT(4)
183 #define TER_OSTEN BIT(15)
[all …]
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| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
| H A D | timer.c | 45 #define TCU_TCSR_PWM_SD BIT(9)
60 #define TCU_TER_TCEN5 BIT(5)
61 #define TCU_TER_TCEN4 BIT(4)
62 #define TCU_TER_TCEN3 BIT(3)
63 #define TCU_TER_TCEN2 BIT(2)
64 #define TCU_TER_TCEN1 BIT(1)
65 #define TCU_TER_TCEN0 BIT(0)
67 #define TCU_TESR_TCST5 BIT(5)
68 #define TCU_TESR_TCST4 BIT(4)
183 #define TER_OSTEN BIT(15)
[all …]
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| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
| H A D | timer.c | 45 #define TCU_TCSR_PWM_SD BIT(9)
60 #define TCU_TER_TCEN5 BIT(5)
61 #define TCU_TER_TCEN4 BIT(4)
62 #define TCU_TER_TCEN3 BIT(3)
63 #define TCU_TER_TCEN2 BIT(2)
64 #define TCU_TER_TCEN1 BIT(1)
65 #define TCU_TER_TCEN0 BIT(0)
67 #define TCU_TESR_TCST5 BIT(5)
68 #define TCU_TESR_TCST4 BIT(4)
183 #define TER_OSTEN BIT(15)
[all …]
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| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
| H A D | timer.c | 45 #define TCU_TCSR_PWM_SD BIT(9)
60 #define TCU_TER_TCEN5 BIT(5)
61 #define TCU_TER_TCEN4 BIT(4)
62 #define TCU_TER_TCEN3 BIT(3)
63 #define TCU_TER_TCEN2 BIT(2)
64 #define TCU_TER_TCEN1 BIT(1)
65 #define TCU_TER_TCEN0 BIT(0)
67 #define TCU_TESR_TCST5 BIT(5)
68 #define TCU_TESR_TCST4 BIT(4)
183 #define TER_OSTEN BIT(15)
[all …]
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| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/mips/mach-jz47xx/jz4780/ |
| H A D | timer.c | 40 #define TCU_TCSR_PWM_SD BIT(9)
42 #define TCU_TCSR_PWM_EN BIT(7)
55 #define TCU_TER_TCEN5 BIT(5)
56 #define TCU_TER_TCEN4 BIT(4)
57 #define TCU_TER_TCEN3 BIT(3)
58 #define TCU_TER_TCEN2 BIT(2)
59 #define TCU_TER_TCEN1 BIT(1)
60 #define TCU_TER_TCEN0 BIT(0)
62 #define TCU_TESR_TCST5 BIT(5)
178 #define TER_OSTEN BIT(15)
[all …]
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| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
| H A D | timer.c | 45 #define TCU_TCSR_PWM_SD BIT(9)
60 #define TCU_TER_TCEN5 BIT(5)
61 #define TCU_TER_TCEN4 BIT(4)
62 #define TCU_TER_TCEN3 BIT(3)
63 #define TCU_TER_TCEN2 BIT(2)
64 #define TCU_TER_TCEN1 BIT(1)
65 #define TCU_TER_TCEN0 BIT(0)
67 #define TCU_TESR_TCST5 BIT(5)
68 #define TCU_TESR_TCST4 BIT(4)
183 #define TER_OSTEN BIT(15)
[all …]
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| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
| H A D | timer.c | 45 #define TCU_TCSR_PWM_SD BIT(9)
60 #define TCU_TER_TCEN5 BIT(5)
61 #define TCU_TER_TCEN4 BIT(4)
62 #define TCU_TER_TCEN3 BIT(3)
63 #define TCU_TER_TCEN2 BIT(2)
64 #define TCU_TER_TCEN1 BIT(1)
65 #define TCU_TER_TCEN0 BIT(0)
67 #define TCU_TESR_TCST5 BIT(5)
68 #define TCU_TESR_TCST4 BIT(4)
183 #define TER_OSTEN BIT(15)
[all …]
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| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/mips/mach-jz47xx/jz4780/ |
| H A D | timer.c | 45 #define TCU_TCSR_PWM_SD BIT(9)
60 #define TCU_TER_TCEN5 BIT(5)
61 #define TCU_TER_TCEN4 BIT(4)
62 #define TCU_TER_TCEN3 BIT(3)
63 #define TCU_TER_TCEN2 BIT(2)
64 #define TCU_TER_TCEN1 BIT(1)
65 #define TCU_TER_TCEN0 BIT(0)
67 #define TCU_TESR_TCST5 BIT(5)
68 #define TCU_TESR_TCST4 BIT(4)
183 #define TER_OSTEN BIT(15)
[all …]
|