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/dports/devel/avr-gcc/gcc-10.2.0/gcc/testsuite/gcc.target/sh/
H A Dsh2a-band.c17 unsigned char BIT4:1; member
61 USRSTR.ICR0.BIT.BIT3 = USRSTR.ICR0.BIT.BIT4 & USRSTR.ICR0.BIT.BIT1; in main()
63 USRSTR.ICR0.BIT.BIT4 = USRSTR.ICR0.BIT.BIT2 & USRSTR.ICR0.BIT.BIT4; in main()
82 PORT.BIT.IOR14 &= USRSTR.ICR0.BIT.BIT4; in main()
86 a = a & USRSTR.ICR0.BIT.BIT4; in main()
H A Dsh2a-bor.c17 unsigned char BIT4:1; member
61 USRSTR.ICR0.BIT.BIT3 = USRSTR.ICR0.BIT.BIT4 | USRSTR.ICR0.BIT.BIT1; in main()
63 USRSTR.ICR0.BIT.BIT4 = USRSTR.ICR0.BIT.BIT2 | USRSTR.ICR0.BIT.BIT4; in main()
82 PORT.BIT.IOR14 |= USRSTR.ICR0.BIT.BIT4; in main()
86 a = a & USRSTR.ICR0.BIT.BIT4; in main()
/dports/lang/gcc11/gcc-11.2.0/gcc/testsuite/gcc.target/sh/
H A Dsh2a-bxor.c17 unsigned char BIT4:1; member
61 USRSTR.ICR0.BIT.BIT3 = USRSTR.ICR0.BIT.BIT4 ^ USRSTR.ICR0.BIT.BIT1; in main()
63 USRSTR.ICR0.BIT.BIT4 = USRSTR.ICR0.BIT.BIT2 ^ USRSTR.ICR0.BIT.BIT4; in main()
82 PORT.BIT.IOR14 ^= USRSTR.ICR0.BIT.BIT4; in main()
86 a = a ^ USRSTR.ICR0.BIT.BIT4; in main()
H A Dsh2a-band.c17 unsigned char BIT4:1; member
61 USRSTR.ICR0.BIT.BIT3 = USRSTR.ICR0.BIT.BIT4 & USRSTR.ICR0.BIT.BIT1; in main()
63 USRSTR.ICR0.BIT.BIT4 = USRSTR.ICR0.BIT.BIT2 & USRSTR.ICR0.BIT.BIT4; in main()
82 PORT.BIT.IOR14 &= USRSTR.ICR0.BIT.BIT4; in main()
86 a = a & USRSTR.ICR0.BIT.BIT4; in main()
H A Dsh2a-bor.c17 unsigned char BIT4:1; member
61 USRSTR.ICR0.BIT.BIT3 = USRSTR.ICR0.BIT.BIT4 | USRSTR.ICR0.BIT.BIT1; in main()
63 USRSTR.ICR0.BIT.BIT4 = USRSTR.ICR0.BIT.BIT2 | USRSTR.ICR0.BIT.BIT4; in main()
82 PORT.BIT.IOR14 |= USRSTR.ICR0.BIT.BIT4; in main()
86 a = a & USRSTR.ICR0.BIT.BIT4; in main()
/dports/lang/gcc9/gcc-9.4.0/gcc/testsuite/gcc.target/sh/
H A Dsh2a-band.c17 unsigned char BIT4:1; member
61 USRSTR.ICR0.BIT.BIT3 = USRSTR.ICR0.BIT.BIT4 & USRSTR.ICR0.BIT.BIT1; in main()
63 USRSTR.ICR0.BIT.BIT4 = USRSTR.ICR0.BIT.BIT2 & USRSTR.ICR0.BIT.BIT4; in main()
82 PORT.BIT.IOR14 &= USRSTR.ICR0.BIT.BIT4; in main()
86 a = a & USRSTR.ICR0.BIT.BIT4; in main()
H A Dsh2a-bxor.c17 unsigned char BIT4:1; member
61 USRSTR.ICR0.BIT.BIT3 = USRSTR.ICR0.BIT.BIT4 ^ USRSTR.ICR0.BIT.BIT1; in main()
63 USRSTR.ICR0.BIT.BIT4 = USRSTR.ICR0.BIT.BIT2 ^ USRSTR.ICR0.BIT.BIT4; in main()
82 PORT.BIT.IOR14 ^= USRSTR.ICR0.BIT.BIT4; in main()
86 a = a ^ USRSTR.ICR0.BIT.BIT4; in main()
H A Dsh2a-bor.c17 unsigned char BIT4:1; member
61 USRSTR.ICR0.BIT.BIT3 = USRSTR.ICR0.BIT.BIT4 | USRSTR.ICR0.BIT.BIT1; in main()
63 USRSTR.ICR0.BIT.BIT4 = USRSTR.ICR0.BIT.BIT2 | USRSTR.ICR0.BIT.BIT4; in main()
82 PORT.BIT.IOR14 |= USRSTR.ICR0.BIT.BIT4; in main()
86 a = a & USRSTR.ICR0.BIT.BIT4; in main()
/dports/lang/gcc10-devel/gcc-10-20211008/gcc/testsuite/gcc.target/sh/
H A Dsh2a-bxor.c17 unsigned char BIT4:1; member
61 USRSTR.ICR0.BIT.BIT3 = USRSTR.ICR0.BIT.BIT4 ^ USRSTR.ICR0.BIT.BIT1; in main()
63 USRSTR.ICR0.BIT.BIT4 = USRSTR.ICR0.BIT.BIT2 ^ USRSTR.ICR0.BIT.BIT4; in main()
82 PORT.BIT.IOR14 ^= USRSTR.ICR0.BIT.BIT4; in main()
86 a = a ^ USRSTR.ICR0.BIT.BIT4; in main()
H A Dsh2a-band.c17 unsigned char BIT4:1; member
61 USRSTR.ICR0.BIT.BIT3 = USRSTR.ICR0.BIT.BIT4 & USRSTR.ICR0.BIT.BIT1; in main()
63 USRSTR.ICR0.BIT.BIT4 = USRSTR.ICR0.BIT.BIT2 & USRSTR.ICR0.BIT.BIT4; in main()
82 PORT.BIT.IOR14 &= USRSTR.ICR0.BIT.BIT4; in main()
86 a = a & USRSTR.ICR0.BIT.BIT4; in main()
H A Dsh2a-bor.c17 unsigned char BIT4:1; member
61 USRSTR.ICR0.BIT.BIT3 = USRSTR.ICR0.BIT.BIT4 | USRSTR.ICR0.BIT.BIT1; in main()
63 USRSTR.ICR0.BIT.BIT4 = USRSTR.ICR0.BIT.BIT2 | USRSTR.ICR0.BIT.BIT4; in main()
82 PORT.BIT.IOR14 |= USRSTR.ICR0.BIT.BIT4; in main()
86 a = a & USRSTR.ICR0.BIT.BIT4; in main()
/dports/devel/mingw32-gcc/gcc-4.8.1/gcc/testsuite/gcc.target/sh/
H A Dsh2a-bxor.c18 unsigned char BIT4:1; member
62 USRSTR.ICR0.BIT.BIT3 = USRSTR.ICR0.BIT.BIT4 ^ USRSTR.ICR0.BIT.BIT1; in main()
64 USRSTR.ICR0.BIT.BIT4 = USRSTR.ICR0.BIT.BIT2 ^ USRSTR.ICR0.BIT.BIT4; in main()
83 PORT.BIT.IOR14 ^= USRSTR.ICR0.BIT.BIT4; in main()
87 a = a ^ USRSTR.ICR0.BIT.BIT4; in main()
H A Dsh2a-bor.c18 unsigned char BIT4:1; member
62 USRSTR.ICR0.BIT.BIT3 = USRSTR.ICR0.BIT.BIT4 | USRSTR.ICR0.BIT.BIT1; in main()
64 USRSTR.ICR0.BIT.BIT4 = USRSTR.ICR0.BIT.BIT2 | USRSTR.ICR0.BIT.BIT4; in main()
83 PORT.BIT.IOR14 |= USRSTR.ICR0.BIT.BIT4; in main()
87 a = a & USRSTR.ICR0.BIT.BIT4; in main()
H A Dsh2a-band.c18 unsigned char BIT4:1; member
62 USRSTR.ICR0.BIT.BIT3 = USRSTR.ICR0.BIT.BIT4 & USRSTR.ICR0.BIT.BIT1; in main()
64 USRSTR.ICR0.BIT.BIT4 = USRSTR.ICR0.BIT.BIT2 & USRSTR.ICR0.BIT.BIT4; in main()
83 PORT.BIT.IOR14 &= USRSTR.ICR0.BIT.BIT4; in main()
87 a = a & USRSTR.ICR0.BIT.BIT4; in main()
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/
H A DPchRegsLpc.h55 #define B_LPC_CFG_SERIRQ_CNT_SIRQSZ (BIT5 | BIT4 | BIT3 | BIT2)
73 #define B_LPC_CFG_IOD_COMB (BIT6 | BIT5 |BIT4)
120 #define B_LPC_CFG_ULKMC_USBSMIEN BIT4
202 #define B_LPC_CFG_BC_TS BIT4 ///< Top Swap
232 #define B_PCH_IO_NMI_SC_REF_TOGGLE BIT4
283 #define B_RTC_PCR_CONF_UCMOS_LOCK BIT4 ///< Upper 128 Byte Lock
287 #define B_RTC_PCR_BUC_DSO BIT4 ///< Daylight Savings Override
344 #define B_ESPI_PCR_XERR_XFES BIT4 ///< Fatal Error Status
H A DPchRegsPcie.h119 #define B_PCH_PCIE_CFG_CCFG_UNRS (BIT6 | BIT5 | BIT4)
127 #define B_PCH_PCIE_CFG_MPC2_ASPMCOEN BIT4
168 #define B_PCH_PCIE_CFG_RPDCGEN_BBCLKREQEN BIT4
187 #define B_PCH_PCIE_CFG_PHYCTL2_TXCFGCHGWAIT (BIT5 | BIT4)
210 #define B_PCH_PCIE_CFG_STRPFUSECFG_LTCGDIS BIT4
251 #define B_PCH_PCIE_CFG_EX_LECTL_DPTPH (BIT6 | BIT5 | BIT4)
281 #define B_PCH_PCIE_CFG_PCIEDBG_LR BIT4
337 #define B_PCH_PCIE_CFG_PCIEPMECTL2_L1SCPGE BIT4
451 #define B_SPX_PCR_PCD_RP2FN (BIT6 | BIT5 | BIT4) ///< Port 2 Function Number
468 #define B_SPX_PCR_PCIEHBP_PCIERIL0O BIT4 ///< PCIe receiver-in-L0 over…
H A DPchRegsSata.h159 #define B_SATA_CFG_MAP_PORT4_PCD BIT4
176 #define B_SATA_CFG_PCS_P4E BIT4
188 #define B_SATA_CFG_SATAGC_MSS (BIT4 | BIT3)
268 #define B_SATA_CFG_BFCS_BIST_FIS_L BIT4
338 #define B_SATA_MEM_AHCI_IS_PORT4 BIT4
348 #define B_SATA_MEM_PORT4_IMPLEMENTED BIT4
372 #define B_SATA_MEM_AHCI_CAP2_SADM BIT4
386 #define B_SATA_MEM_AHCI_SFM_RSTE BIT4
448 #define B_SATA_MEM_AHCI_PXIS_UFS BIT4
473 #define B_SATA_MEM_AHCI_PXIE_UFIE BIT4
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/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Register/
H A DPchRegsUsb.h68 #define B_PCH_XHCI_XHCC1_UDAGCNP (BIT5 | BIT4)
78 #define B_PCH_XHCI_XHCC2_L1FP2CGWC (BIT5 | BIT4 | BIT3)
94 #define B_PCH_XHCI_XHCLKGTEN_XHCBLCGE BIT4
138 #define B_PCH_XHCI_FUS_SSPRTCNT (BIT4 | BIT3)
141 #define V_PCH_XHCI_FUS_SSPRTCNT_10B (BIT4)
142 #define V_PCH_XHCI_FUS_SSPRTCNT_11B (BIT4 | BIT3)
273 #define B_PCH_XHCI_PORTSCXUSB2_PR BIT4 ///< Port Reset
293 #define B_PCH_XHCI_PORTSCXUSB3_PR BIT4 ///< Port Reset
356 #define B_PCH_XHCI_USBLEGCTLSTS_SMIHSEE BIT4 ///< SMI on Host System Error Enable
H A DPchRegsSata.h178 #define B_PCH_H_SATA_MAP_PORT4_PCD BIT4
196 #define B_PCH_H_SATA_PCS_P4E BIT4
209 #define B_PCH_SATA_SATAGC_MSS (BIT4 | BIT3)
289 #define B_PCH_SATA_BFCS_BIST_FIS_L BIT4
360 #define B_PCH_SATA_AHCI_IS_PORT4 BIT4
371 #define B_PCH_SATA_PORT4_IMPLEMENTED BIT4
395 #define B_PCH_SATA_AHCI_CAP2_SADM BIT4
410 #define B_PCH_SATA_AHCI_RSTF_RSTE BIT4
472 #define B_PCH_SATA_AHCI_PXIS_UFS BIT4
497 #define B_PCH_SATA_AHCI_PXIE_UFIE BIT4
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/dports/emulators/qemu60/qemu-6.0.0/roms/edk2/OvmfPkg/Include/IndustryStandard/
H A DLsiScsi.h37 #define LSI_DSTAT_ABRT BIT4
49 #define LSI_ISTAT0_SEM BIT4
61 #define LSI_SIST0_RSL BIT4
73 #define LSI_SIST1_SBMC BIT4
/dports/emulators/qemu/qemu-6.2.0/roms/edk2/OvmfPkg/Include/IndustryStandard/
H A DLsiScsi.h37 #define LSI_DSTAT_ABRT BIT4
49 #define LSI_ISTAT0_SEM BIT4
61 #define LSI_SIST0_RSL BIT4
73 #define LSI_SIST1_SBMC BIT4
/dports/emulators/qemu5/qemu-5.2.0/roms/edk2/OvmfPkg/Include/IndustryStandard/
H A DLsiScsi.h37 #define LSI_DSTAT_ABRT BIT4
49 #define LSI_ISTAT0_SEM BIT4
61 #define LSI_SIST0_RSL BIT4
73 #define LSI_SIST1_SBMC BIT4
/dports/sysutils/uefi-edk2-bhyve/edk2-edk2-stable202102/OvmfPkg/Include/IndustryStandard/
H A DLsiScsi.h37 #define LSI_DSTAT_ABRT BIT4
49 #define LSI_ISTAT0_SEM BIT4
61 #define LSI_SIST0_RSL BIT4
73 #define LSI_SIST1_SBMC BIT4
/dports/sysutils/edk2/edk2-edk2-stable202102/OvmfPkg/Include/IndustryStandard/
H A DLsiScsi.h37 #define LSI_DSTAT_ABRT BIT4
49 #define LSI_ISTAT0_SEM BIT4
61 #define LSI_SIST0_RSL BIT4
73 #define LSI_SIST1_SBMC BIT4
/dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/KabylakeSiliconPkg/Include/
H A DPcieRegs.h69 #define B_PCIE_XCAP_DT (BIT7 | BIT6 | BIT5 | BIT4) ///< Device/Port Type
90 #define B_PCIE_DSTS_APD BIT4 ///< AUX Power Detected
117 #define B_PCIE_LCTL_LD BIT4 ///< Link Disable
175 #define B_PCIE_DCTL2_CTD BIT4 ///< Completion Timeout Disable
192 #define B_PCIE_LSTS2_EQP3S BIT4 ///< Equalization Phase 3 Successful
282 #define B_PCIE_EX_L1SCAP_L1PSS BIT4 ///< L1 PM substates supported

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