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Searched refs:CLK_DIV_ISP0_VAL (Results 51 – 75 of 126) sorted by relevance

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/dports/sysutils/u-boot-rpi4/u-boot-2021.07/arch/arm/mach-exynos/
H A Dexynos5_setup.h483 #define CLK_DIV_ISP0_VAL 0x31 macro
750 #define CLK_DIV_ISP0_VAL 0x13131300 macro
/dports/sysutils/u-boot-rockpro64/u-boot-2021.07/arch/arm/mach-exynos/
H A Dexynos5_setup.h483 #define CLK_DIV_ISP0_VAL 0x31 macro
750 #define CLK_DIV_ISP0_VAL 0x13131300 macro
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/arch/arm/mach-exynos/
H A Dexynos5_setup.h483 #define CLK_DIV_ISP0_VAL 0x31 macro
750 #define CLK_DIV_ISP0_VAL 0x13131300 macro
/dports/sysutils/u-boot-qemu-riscv64/u-boot-2021.07/arch/arm/mach-exynos/
H A Dexynos5_setup.h483 #define CLK_DIV_ISP0_VAL 0x31 macro
750 #define CLK_DIV_ISP0_VAL 0x13131300 macro
/dports/sysutils/u-boot-qemu-arm/u-boot-2021.07/arch/arm/mach-exynos/
H A Dexynos5_setup.h483 #define CLK_DIV_ISP0_VAL 0x31 macro
750 #define CLK_DIV_ISP0_VAL 0x13131300 macro
/dports/sysutils/u-boot-rpi/u-boot-2021.07/arch/arm/mach-exynos/
H A Dexynos5_setup.h483 #define CLK_DIV_ISP0_VAL 0x31 macro
750 #define CLK_DIV_ISP0_VAL 0x13131300 macro
/dports/sysutils/u-boot-rpi-arm64/u-boot-2021.07/arch/arm/mach-exynos/
H A Dexynos5_setup.h483 #define CLK_DIV_ISP0_VAL 0x31 macro
750 #define CLK_DIV_ISP0_VAL 0x13131300 macro
/dports/sysutils/u-boot-rock-pi-4/u-boot-2021.07/arch/arm/mach-exynos/
H A Dexynos5_setup.h483 #define CLK_DIV_ISP0_VAL 0x31 macro
750 #define CLK_DIV_ISP0_VAL 0x13131300 macro
/dports/sysutils/u-boot-rpi2/u-boot-2021.07/arch/arm/mach-exynos/
H A Dexynos5_setup.h483 #define CLK_DIV_ISP0_VAL 0x31 macro
750 #define CLK_DIV_ISP0_VAL 0x13131300 macro
/dports/sysutils/u-boot-riotboard/u-boot-2021.07/arch/arm/mach-exynos/
H A Dexynos5_setup.h483 #define CLK_DIV_ISP0_VAL 0x31 macro
750 #define CLK_DIV_ISP0_VAL 0x13131300 macro
/dports/sysutils/u-boot-rpi3/u-boot-2021.07/arch/arm/mach-exynos/
H A Dexynos5_setup.h483 #define CLK_DIV_ISP0_VAL 0x31 macro
750 #define CLK_DIV_ISP0_VAL 0x13131300 macro
/dports/sysutils/u-boot-rpi3-32/u-boot-2021.07/arch/arm/mach-exynos/
H A Dexynos5_setup.h483 #define CLK_DIV_ISP0_VAL 0x31 macro
750 #define CLK_DIV_ISP0_VAL 0x13131300 macro
/dports/sysutils/u-boot-rock64/u-boot-2021.07/arch/arm/mach-exynos/
H A Dexynos5_setup.h483 #define CLK_DIV_ISP0_VAL 0x31 macro
750 #define CLK_DIV_ISP0_VAL 0x13131300 macro
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/mach-exynos/
H A Dclock_init_exynos5.c768 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); in exynos5250_system_clock_init()
946 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); in exynos5420_system_clock_init()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-exynos/
H A Dclock_init_exynos5.c768 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); in exynos5250_system_clock_init()
946 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); in exynos5420_system_clock_init()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-exynos/
H A Dclock_init_exynos5.c768 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); in exynos5250_system_clock_init()
946 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); in exynos5420_system_clock_init()
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/mach-exynos/
H A Dclock_init_exynos5.c768 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); in exynos5250_system_clock_init()
946 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); in exynos5420_system_clock_init()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-exynos/
H A Dclock_init_exynos5.c768 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); in exynos5250_system_clock_init()
946 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); in exynos5420_system_clock_init()
/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/mach-exynos/
H A Dclock_init_exynos5.c768 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); in exynos5250_system_clock_init()
946 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); in exynos5420_system_clock_init()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-exynos/
H A Dclock_init_exynos5.c768 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); in exynos5250_system_clock_init()
946 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); in exynos5420_system_clock_init()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/mach-exynos/
H A Dclock_init_exynos5.c768 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); in exynos5250_system_clock_init()
946 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); in exynos5420_system_clock_init()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-exynos/
H A Dclock_init_exynos5.c768 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); in exynos5250_system_clock_init()
946 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); in exynos5420_system_clock_init()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-exynos/
H A Dclock_init_exynos5.c768 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); in exynos5250_system_clock_init()
946 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); in exynos5420_system_clock_init()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-exynos/
H A Dclock_init_exynos5.c768 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); in exynos5250_system_clock_init()
946 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); in exynos5420_system_clock_init()
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-exynos/
H A Dclock_init_exynos5.c768 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); in exynos5250_system_clock_init()
946 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); in exynos5420_system_clock_init()

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