| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/clk/sunxi/ |
| H A D | clk_a10s.c | 35 [CLK_SPI2] = GATE(0x0a8, BIT(31)),
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/include/dt-bindings/clock/ |
| H A D | sun9i-a80-ccu.h | 75 #define CLK_SPI2 49 macro
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/include/dt-bindings/clock/ |
| H A D | sun9i-a80-ccu.h | 75 #define CLK_SPI2 49 macro
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/include/dt-bindings/clock/ |
| H A D | sun9i-a80-ccu.h | 75 #define CLK_SPI2 49 macro
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/clk/sunxi/ |
| H A D | clk_a10s.c | 35 [CLK_SPI2] = GATE(0x0a8, BIT(31)),
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/include/dt-bindings/clock/ |
| H A D | sun9i-a80-ccu.h | 75 #define CLK_SPI2 49 macro
|
| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/include/dt-bindings/clock/ |
| H A D | sun9i-a80-ccu.h | 75 #define CLK_SPI2 49 macro
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/clk/sunxi/ |
| H A D | clk_a10s.c | 35 [CLK_SPI2] = GATE(0x0a8, BIT(31)),
|
| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/include/dt-bindings/clock/ |
| H A D | sun9i-a80-ccu.h | 75 #define CLK_SPI2 49 macro
|
| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/include/dt-bindings/clock/ |
| H A D | sun9i-a80-ccu.h | 75 #define CLK_SPI2 49 macro
|
| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/clk/sunxi/ |
| H A D | clk_a10s.c | 35 [CLK_SPI2] = GATE(0x0a8, BIT(31)),
|
| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/clk/sunxi/ |
| H A D | clk_a10s.c | 35 [CLK_SPI2] = GATE(0x0a8, BIT(31)),
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/include/dt-bindings/clock/ |
| H A D | sun9i-a80-ccu.h | 75 #define CLK_SPI2 49 macro
|
| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/drivers/clk/sunxi/ |
| H A D | clk_a10s.c | 35 [CLK_SPI2] = GATE(0x0a8, BIT(31)),
|
| /dports/sysutils/u-boot-pine-h64/u-boot-2021.07/include/dt-bindings/clock/ |
| H A D | sun9i-a80-ccu.h | 75 #define CLK_SPI2 49 macro
|
| /dports/sysutils/u-boot-pine64/u-boot-2021.07/drivers/clk/sunxi/ |
| H A D | clk_a10s.c | 35 [CLK_SPI2] = GATE(0x0a8, BIT(31)),
|
| /dports/sysutils/u-boot-pine64/u-boot-2021.07/include/dt-bindings/clock/ |
| H A D | sun9i-a80-ccu.h | 75 #define CLK_SPI2 49 macro
|
| /dports/sysutils/u-boot-pcduino3/u-boot-2021.07/include/dt-bindings/clock/ |
| H A D | sun9i-a80-ccu.h | 75 #define CLK_SPI2 49 macro
|
| /dports/sysutils/u-boot-pine-h64/u-boot-2021.07/drivers/clk/sunxi/ |
| H A D | clk_a10s.c | 35 [CLK_SPI2] = GATE(0x0a8, BIT(31)),
|
| /dports/sysutils/u-boot-pcduino3/u-boot-2021.07/drivers/clk/sunxi/ |
| H A D | clk_a10s.c | 35 [CLK_SPI2] = GATE(0x0a8, BIT(31)),
|
| /dports/sysutils/u-boot-pine64-lts/u-boot-2021.07/include/dt-bindings/clock/ |
| H A D | sun9i-a80-ccu.h | 75 #define CLK_SPI2 49 macro
|
| /dports/sysutils/u-boot-pinebook/u-boot-2021.07/drivers/clk/sunxi/ |
| H A D | clk_a10s.c | 35 [CLK_SPI2] = GATE(0x0a8, BIT(31)),
|
| /dports/sysutils/u-boot-pinebookpro/u-boot-2021.07/drivers/clk/sunxi/ |
| H A D | clk_a10s.c | 35 [CLK_SPI2] = GATE(0x0a8, BIT(31)),
|
| /dports/sysutils/u-boot-pine64-lts/u-boot-2021.07/drivers/clk/sunxi/ |
| H A D | clk_a10s.c | 35 [CLK_SPI2] = GATE(0x0a8, BIT(31)),
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/include/dt-bindings/clock/ |
| H A D | sun9i-a80-ccu.h | 75 #define CLK_SPI2 49 macro
|