| /dports/sysutils/u-boot-sifive-fu540/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | clock_init_exynos4.c | 49 writel(CLK_SRC_TOP1_VAL, &clk->src_top1); in system_clock_init()
|
| /dports/sysutils/u-boot-rpi4/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | clock_init_exynos4.c | 49 writel(CLK_SRC_TOP1_VAL, &clk->src_top1); in system_clock_init()
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/arch/arm/mach-exynos/ |
| H A D | clock_init_exynos4.c | 49 writel(CLK_SRC_TOP1_VAL, &clk->src_top1); in system_clock_init()
|
| /dports/sysutils/u-boot-qemu-riscv64/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | clock_init_exynos4.c | 49 writel(CLK_SRC_TOP1_VAL, &clk->src_top1); in system_clock_init()
|
| /dports/sysutils/u-boot-qemu-arm/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | clock_init_exynos4.c | 49 writel(CLK_SRC_TOP1_VAL, &clk->src_top1); in system_clock_init()
|
| /dports/sysutils/u-boot-rpi/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | clock_init_exynos4.c | 49 writel(CLK_SRC_TOP1_VAL, &clk->src_top1); in system_clock_init()
|
| /dports/sysutils/u-boot-rpi-arm64/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | clock_init_exynos4.c | 49 writel(CLK_SRC_TOP1_VAL, &clk->src_top1); in system_clock_init()
|
| /dports/sysutils/u-boot-rpi2/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | clock_init_exynos4.c | 49 writel(CLK_SRC_TOP1_VAL, &clk->src_top1); in system_clock_init()
|
| /dports/sysutils/u-boot-riotboard/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | clock_init_exynos4.c | 49 writel(CLK_SRC_TOP1_VAL, &clk->src_top1); in system_clock_init()
|
| /dports/sysutils/u-boot-rock-pi-4/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | clock_init_exynos4.c | 49 writel(CLK_SRC_TOP1_VAL, &clk->src_top1); in system_clock_init()
|
| /dports/sysutils/u-boot-rpi3/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | clock_init_exynos4.c | 49 writel(CLK_SRC_TOP1_VAL, &clk->src_top1); in system_clock_init()
|
| /dports/sysutils/u-boot-rock64/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | clock_init_exynos4.c | 49 writel(CLK_SRC_TOP1_VAL, &clk->src_top1); in system_clock_init()
|
| /dports/sysutils/u-boot-rpi3-32/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | clock_init_exynos4.c | 49 writel(CLK_SRC_TOP1_VAL, &clk->src_top1); in system_clock_init()
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-exynos/ |
| H A D | exynos5_setup.h | 551 #define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \ macro
784 #define CLK_SRC_TOP1_VAL 0x00100200 macro
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | exynos5_setup.h | 551 #define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \ macro
784 #define CLK_SRC_TOP1_VAL 0x00100200 macro
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | exynos5_setup.h | 551 #define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \ macro
784 #define CLK_SRC_TOP1_VAL 0x00100200 macro
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | exynos5_setup.h | 551 #define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \ macro
784 #define CLK_SRC_TOP1_VAL 0x00100200 macro
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | exynos5_setup.h | 551 #define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \ macro
784 #define CLK_SRC_TOP1_VAL 0x00100200 macro
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | exynos5_setup.h | 551 #define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \ macro
784 #define CLK_SRC_TOP1_VAL 0x00100200 macro
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/mach-exynos/ |
| H A D | exynos5_setup.h | 551 #define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \ macro
784 #define CLK_SRC_TOP1_VAL 0x00100200 macro
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | exynos5_setup.h | 551 #define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \ macro
784 #define CLK_SRC_TOP1_VAL 0x00100200 macro
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | exynos5_setup.h | 551 #define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \ macro
784 #define CLK_SRC_TOP1_VAL 0x00100200 macro
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | exynos5_setup.h | 551 #define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \ macro
784 #define CLK_SRC_TOP1_VAL 0x00100200 macro
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | exynos5_setup.h | 551 #define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \ macro
784 #define CLK_SRC_TOP1_VAL 0x00100200 macro
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/mach-exynos/ |
| H A D | exynos5_setup.h | 551 #define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \ macro
784 #define CLK_SRC_TOP1_VAL 0x00100200 macro
|