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Searched refs:CONFIG_SYS_DDR_TIMING_3_800 (Results 26 – 50 of 231) sorted by relevance

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/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c36 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 macro
87 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
119 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c36 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 macro
87 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
119 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/sysutils/u-boot-pine64/u-boot-2021.07/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c36 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 in FI()
87 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, in FI()
119 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/sysutils/u-boot-pine-h64/u-boot-2021.07/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c36 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 macro
87 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
119 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/sysutils/u-boot-pcduino3/u-boot-2021.07/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c36 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 macro
87 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
119 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/sysutils/u-boot-pine64-lts/u-boot-2021.07/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c36 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 macro
87 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
119 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/sysutils/u-boot-pinebook/u-boot-2021.07/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c36 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 macro
87 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
119 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c36 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 macro
87 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
119 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c36 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 macro
87 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
119 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c36 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 macro
87 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
119 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c36 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 macro
87 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
119 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c36 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 macro
87 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
119 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/sysutils/u-boot-orangepi-plus-2e/u-boot-2021.07/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c36 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 macro
87 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
119 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/sysutils/u-boot-orangepi-pc2/u-boot-2021.07/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c36 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 macro
87 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
119 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/sysutils/u-boot-orangepi-pc/u-boot-2021.07/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c36 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 macro
87 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
119 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/sysutils/u-boot-orangepi-one/u-boot-2021.07/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c36 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 macro
87 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
119 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/sysutils/u-boot-orangepi-pc-plus/u-boot-2021.07/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c36 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 macro
87 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
119 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/sysutils/u-boot-beaglebone/u-boot-2021.07/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c36 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 macro
87 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
119 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/sysutils/u-boot-tools/u-boot-2020.07/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c36 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 macro
87 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
119 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/sysutils/u-boot-bananapim2/u-boot-2021.07/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c36 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 macro
87 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
119 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c36 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 macro
87 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
119 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/sysutils/u-boot-utilite/u-boot-2015.07/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c39 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 macro
90 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
122 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c36 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 macro
87 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
119 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/sysutils/u-boot-sifive-fu540/u-boot-2021.07/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c36 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 macro
87 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
119 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/sysutils/u-boot-rpi4/u-boot-2021.07/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c36 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 macro
87 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
119 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,

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