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Searched refs:CONFIG_SYS_DDR_TIMING_3_800 (Results 76 – 100 of 231) sorted by relevance

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/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/board/freescale/bsc9132qds/
H A Dspl_minimal.c28 __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); in sdram_init()
H A Dddr.c21 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/board/freescale/bsc9131rdb/
H A Dddr.c22 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/board/freescale/bsc9132qds/
H A Dspl_minimal.c28 __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); in sdram_init()
H A Dddr.c21 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/sysutils/u-boot-utilite/u-boot-2015.07/board/freescale/bsc9132qds/
H A Dspl_minimal.c29 __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); in sdram_init()
H A Dddr.c24 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/sysutils/u-boot-tools/u-boot-2020.07/board/freescale/bsc9131rdb/
H A Dddr.c24 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/sysutils/u-boot-tools/u-boot-2020.07/board/freescale/bsc9132qds/
H A Dspl_minimal.c30 __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); in sdram_init()
H A Dddr.c22 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/sysutils/u-boot-tools/u-boot-2020.07/include/configs/
H A DBSC9131RDB.h95 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 macro
/dports/sysutils/u-boot-utilite/u-boot-2015.07/board/freescale/bsc9131rdb/
H A Dddr.c25 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/board/freescale/bsc9132qds/
H A Dspl_minimal.c28 __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); in sdram_init()
H A Dddr.c21 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/board/freescale/bsc9131rdb/
H A Dddr.c22 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/include/configs/
H A DBSC9131RDB.h101 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 macro
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/include/configs/
H A DBSC9131RDB.h101 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 macro
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/include/configs/
H A DBSC9131RDB.h101 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/include/configs/
H A DBSC9131RDB.h101 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 macro
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/include/configs/
H A DBSC9131RDB.h101 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 macro
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/board/freescale/bsc9132qds/
H A Dddr.c21 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/board/freescale/bsc9132qds/
H A Dddr.c21 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/board/freescale/p1010rdb/
H A Dddr.c26 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/board/freescale/p1010rdb/
H A Dddr.c26 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/board/freescale/p1010rdb/
H A Dddr.c26 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,

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