| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/board/freescale/p2041rdb/ |
| H A D | p2041rdb.c | 79 #define CPLD_LANE_D_SEL 0x8 macro
96 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
107 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
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| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/board/freescale/p2041rdb/ |
| H A D | p2041rdb.c | 79 #define CPLD_LANE_D_SEL 0x8 macro
96 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
107 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
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| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/board/freescale/p2041rdb/ |
| H A D | p2041rdb.c | 79 #define CPLD_LANE_D_SEL 0x8 macro
96 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
107 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
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| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/board/freescale/p2041rdb/ |
| H A D | p2041rdb.c | 79 #define CPLD_LANE_D_SEL 0x8 macro
96 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
107 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
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| /dports/sysutils/u-boot-pine64/u-boot-2021.07/board/freescale/p2041rdb/ |
| H A D | p2041rdb.c | 79 #define CPLD_LANE_D_SEL 0x8 macro
96 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
107 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
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| /dports/sysutils/u-boot-pine-h64/u-boot-2021.07/board/freescale/p2041rdb/ |
| H A D | p2041rdb.c | 79 #define CPLD_LANE_D_SEL 0x8
96 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
107 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
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| /dports/sysutils/u-boot-pcduino3/u-boot-2021.07/board/freescale/p2041rdb/ |
| H A D | p2041rdb.c | 79 #define CPLD_LANE_D_SEL 0x8 macro
96 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
107 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
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| /dports/sysutils/u-boot-pinebook/u-boot-2021.07/board/freescale/p2041rdb/ |
| H A D | p2041rdb.c | 79 #define CPLD_LANE_D_SEL 0x8 macro
96 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
107 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
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| /dports/sysutils/u-boot-pine64-lts/u-boot-2021.07/board/freescale/p2041rdb/ |
| H A D | p2041rdb.c | 79 #define CPLD_LANE_D_SEL 0x8 macro
96 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
107 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
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| /dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/board/freescale/p2041rdb/ |
| H A D | p2041rdb.c | 79 #define CPLD_LANE_D_SEL 0x8 macro
96 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
107 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
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| /dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/board/freescale/p2041rdb/ |
| H A D | p2041rdb.c | 79 #define CPLD_LANE_D_SEL 0x8 macro
96 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
107 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
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| /dports/emulators/qemu/qemu-6.2.0/roms/u-boot/board/freescale/p2041rdb/ |
| H A D | p2041rdb.c | 79 #define CPLD_LANE_D_SEL 0x8 macro
96 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
107 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
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| /dports/sysutils/u-boot-orangepi-pc2/u-boot-2021.07/board/freescale/p2041rdb/ |
| H A D | p2041rdb.c | 79 #define CPLD_LANE_D_SEL 0x8 macro
96 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
107 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
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| /dports/sysutils/u-boot-orangepi-plus-2e/u-boot-2021.07/board/freescale/p2041rdb/ |
| H A D | p2041rdb.c | 79 #define CPLD_LANE_D_SEL 0x8 macro
96 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
107 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
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| /dports/sysutils/u-boot-orangepi-one/u-boot-2021.07/board/freescale/p2041rdb/ |
| H A D | p2041rdb.c | 79 #define CPLD_LANE_D_SEL 0x8 macro
96 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
107 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
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| /dports/sysutils/u-boot-orangepi-pc/u-boot-2021.07/board/freescale/p2041rdb/ |
| H A D | p2041rdb.c | 79 #define CPLD_LANE_D_SEL 0x8 macro
96 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
107 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
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| /dports/sysutils/u-boot-orangepi-pc-plus/u-boot-2021.07/board/freescale/p2041rdb/ |
| H A D | p2041rdb.c | 79 #define CPLD_LANE_D_SEL 0x8 macro
96 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
107 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
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| /dports/sysutils/u-boot-beaglebone/u-boot-2021.07/board/freescale/p2041rdb/ |
| H A D | p2041rdb.c | 79 #define CPLD_LANE_D_SEL 0x8 macro
96 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
107 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
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| /dports/sysutils/u-boot-bananapim2/u-boot-2021.07/board/freescale/p2041rdb/ |
| H A D | p2041rdb.c | 79 #define CPLD_LANE_D_SEL 0x8 macro
96 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
107 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
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| /dports/sysutils/u-boot-tools/u-boot-2020.07/board/freescale/p2041rdb/ |
| H A D | p2041rdb.c | 78 #define CPLD_LANE_D_SEL 0x8 macro
95 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
106 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
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| /dports/sysutils/u-boot-bananapi/u-boot-2021.07/board/freescale/p2041rdb/ |
| H A D | p2041rdb.c | 79 #define CPLD_LANE_D_SEL 0x8 macro
96 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
107 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
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| /dports/sysutils/u-boot-utilite/u-boot-2015.07/board/freescale/p2041rdb/ |
| H A D | p2041rdb.c | 76 #define CPLD_LANE_D_SEL 0x8 macro
93 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
104 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
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| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/board/freescale/p2041rdb/ |
| H A D | p2041rdb.c | 79 #define CPLD_LANE_D_SEL 0x8 macro
96 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
107 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
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| /dports/sysutils/u-boot-rock64/u-boot-2021.07/board/freescale/p2041rdb/ |
| H A D | p2041rdb.c | 79 #define CPLD_LANE_D_SEL 0x8 macro
96 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
107 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
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| /dports/sysutils/u-boot-rpi3-32/u-boot-2021.07/board/freescale/p2041rdb/ |
| H A D | p2041rdb.c | 79 #define CPLD_LANE_D_SEL 0x8 macro
96 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
107 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL; in board_config_lanes_mux()
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