Home
last modified time | relevance | path

Searched refs:DDRC_PCFGQOS0_0 (Results 251 – 275 of 300) sorted by relevance

1...<<1112

/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dddr.h521 #define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) macro
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h521 #define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) macro
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dddr.h521 #define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) macro
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dddr.h521 #define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) macro
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dddr.h521 #define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) macro
/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dddr.h521 #define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) macro
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h521 #define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h521 #define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) macro
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dddr.h521 #define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) macro
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dddr.h521 #define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) macro
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dddr.h521 #define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) macro
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dddr.h521 #define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) macro
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dddr.h521 #define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) macro
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dddr.h521 #define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) macro
/dports/sysutils/u-boot-pine64-lts/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dddr.h521 #define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) macro
/dports/sysutils/u-boot-pine-h64/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dddr.h521 #define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494)
/dports/sysutils/u-boot-pcduino3/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dddr.h521 #define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) macro
/dports/sysutils/u-boot-pine64/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dddr.h521 #define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) macro
/dports/sysutils/u-boot-pinebookpro/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dddr.h521 #define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) macro
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dddr.h521 #define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) macro
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dddr.h521 #define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) macro
/dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dddr.h521 #define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) macro
/dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dddr.h521 #define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) macro
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h521 #define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) macro
/dports/sysutils/u-boot-orangepi-pc2/u-boot-2021.07/arch/arm/include/asm/arch-imx8m/
H A Dddr.h521 #define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) macro

1...<<1112