| /dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.h | 550 return MI.getDesc().TSFlags & SIInstrFlags::DPP; in isDPP()
554 return get(Opcode).TSFlags & SIInstrFlags::DPP; in isDPP()
|
| /dports/biology/emboss/EMBOSS-6.6.0/test/data/hmm/ |
| H A D | fn3.slx | 33 CPSF_CHICK/630-716 P.DPP.QSVRVTSV..GEDWAVLSWEAPPf..dGGMPITGYLMER...KK
86 PTP1_DROME/123-205 P.DPP.SNLSVQVR..SGKNAIILWSPPT.....QGSYTAFKIKV...LG
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.td | 1617 // Return type of input modifiers operand specified input operand for DPP
1900 // Outs for DPP
2089 // Function that checks if instruction supports DPP and SDWA
2093 0, // NumSrcArgs == 3 - No DPP or SDWA for VOP3
2095 0, // 64-bit dst - No DPP or SDWA for 64-bit operands
2159 // HasModifiers affects the normal and DPP encodings. We take note of EnableF32SrcMods, which
2445 // Maps ordinary instructions to their DPP counterparts
2451 let ValueCols = [["DPP"]];
|
| H A D | SIInstrInfo.h | 578 return MI.getDesc().TSFlags & SIInstrFlags::DPP; in isDPP()
582 return get(Opcode).TSFlags & SIInstrFlags::DPP; in isDPP()
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.td | 1614 // Return type of input modifiers operand specified input operand for DPP
1897 // Outs for DPP and SDWA
2086 // Function that checks if instruction supports DPP and SDWA
2090 0, // NumSrcArgs == 3 - No DPP or SDWA for VOP3
2092 0, // 64-bit dst - No DPP or SDWA for 64-bit operands
2164 // HasModifiers affects the normal and DPP encodings. We take note of EnableF32SrcMods, which
2452 // Maps ordinary instructions to their DPP counterparts
2458 let ValueCols = [["DPP"]];
|
| H A D | SIInstrInfo.h | 565 return MI.getDesc().TSFlags & SIInstrFlags::DPP; in isDPP()
569 return get(Opcode).TSFlags & SIInstrFlags::DPP; in isDPP()
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.td | 1578 // Return type of input modifiers operand specified input operand for DPP
1861 // Outs for DPP and SDWA
2050 // Function that checks if instruction supports DPP and SDWA
2054 0, // NumSrcArgs == 3 - No DPP or SDWA for VOP3
2056 0, // 64-bit dst - No DPP or SDWA for 64-bit operands
2128 // HasModifiers affects the normal and DPP encodings. We take note of EnableF32SrcMods, which
2415 // Maps ordinary instructions to their DPP counterparts
2421 let ValueCols = [["DPP"]];
|
| H A D | SIInstrInfo.h | 559 return MI.getDesc().TSFlags & SIInstrFlags::DPP; in isDPP()
563 return get(Opcode).TSFlags & SIInstrFlags::DPP; in isDPP()
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.td | 1614 // Return type of input modifiers operand specified input operand for DPP
1897 // Outs for DPP and SDWA
2086 // Function that checks if instruction supports DPP and SDWA
2090 0, // NumSrcArgs == 3 - No DPP or SDWA for VOP3
2092 0, // 64-bit dst - No DPP or SDWA for 64-bit operands
2164 // HasModifiers affects the normal and DPP encodings. We take note of EnableF32SrcMods, which
2452 // Maps ordinary instructions to their DPP counterparts
2458 let ValueCols = [["DPP"]];
|
| H A D | SIInstrInfo.h | 565 return MI.getDesc().TSFlags & SIInstrFlags::DPP; in isDPP()
569 return get(Opcode).TSFlags & SIInstrFlags::DPP; in isDPP()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.td | 1578 // Return type of input modifiers operand specified input operand for DPP
1861 // Outs for DPP and SDWA
2050 // Function that checks if instruction supports DPP and SDWA
2054 0, // NumSrcArgs == 3 - No DPP or SDWA for VOP3
2056 0, // 64-bit dst - No DPP or SDWA for 64-bit operands
2128 // HasModifiers affects the normal and DPP encodings. We take note of EnableF32SrcMods, which
2415 // Maps ordinary instructions to their DPP counterparts
2421 let ValueCols = [["DPP"]];
|
| H A D | SIInstrInfo.h | 559 return MI.getDesc().TSFlags & SIInstrFlags::DPP; in isDPP()
563 return get(Opcode).TSFlags & SIInstrFlags::DPP; in isDPP()
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.td | 1578 // Return type of input modifiers operand specified input operand for DPP
1861 // Outs for DPP and SDWA
2050 // Function that checks if instruction supports DPP and SDWA
2054 0, // NumSrcArgs == 3 - No DPP or SDWA for VOP3
2056 0, // 64-bit dst - No DPP or SDWA for 64-bit operands
2128 // HasModifiers affects the normal and DPP encodings. We take note of EnableF32SrcMods, which
2415 // Maps ordinary instructions to their DPP counterparts
2421 let ValueCols = [["DPP"]];
|
| H A D | SIInstrInfo.h | 559 return MI.getDesc().TSFlags & SIInstrFlags::DPP; in isDPP()
563 return get(Opcode).TSFlags & SIInstrFlags::DPP; in isDPP()
|
| /dports/multimedia/libmediainfo/MediaInfo_CLI_GNU_FromSource/MediaInfo/Contrib/TranslationToolkit/ |
| H A D | Data_Notes.csv | 30 …or not. Ref: http://dpp-assets.s3.amazonaws.com/wp-content/uploads/2014/05/DPP-Metadata-Applicatio…
|
| /dports/multimedia/mediainfo/MediaInfo_CLI_GNU_FromSource/MediaInfo/Contrib/TranslationToolkit/ |
| H A D | Data_Notes.csv | 30 …or not. Ref: http://dpp-assets.s3.amazonaws.com/wp-content/uploads/2014/05/DPP-Metadata-Applicatio…
|
| /dports/multimedia/libzen/MediaInfo_CLI_GNU_FromSource/MediaInfo/Contrib/TranslationToolkit/ |
| H A D | Data_Notes.csv | 30 …or not. Ref: http://dpp-assets.s3.amazonaws.com/wp-content/uploads/2014/05/DPP-Metadata-Applicatio…
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.td | 1566 // Return type of input modifiers operand specified input operand for DPP
1796 // Outs for DPP
1976 // Function that checks if instruction supports DPP and SDWA
1980 0, // NumSrcArgs == 3 - No DPP or SDWA for VOP3
1982 0, // 64-bit dst - No DPP or SDWA for 64-bit operands
2332 // Maps ordinary instructions to their DPP counterparts
2338 let ValueCols = [["DPP"]];
|
| H A D | SIInstrInfo.h | 574 return MI.getDesc().TSFlags & SIInstrFlags::DPP; in isDPP()
578 return get(Opcode).TSFlags & SIInstrFlags::DPP; in isDPP()
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.td | 1566 // Return type of input modifiers operand specified input operand for DPP
1796 // Outs for DPP
1976 // Function that checks if instruction supports DPP and SDWA
1980 0, // NumSrcArgs == 3 - No DPP or SDWA for VOP3
1982 0, // 64-bit dst - No DPP or SDWA for 64-bit operands
2332 // Maps ordinary instructions to their DPP counterparts
2338 let ValueCols = [["DPP"]];
|
| /dports/emulators/qemu42/qemu-4.2.1/hw/ssi/ |
| H A D | aspeed_smc.c | 747 DPP = 0xa2, enumerator
756 case DPP: in aspeed_smc_num_dummies()
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.h | 608 return MI.getDesc().TSFlags & SIInstrFlags::DPP; in isDPP()
612 return get(Opcode).TSFlags & SIInstrFlags::DPP; in isDPP()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.h | 608 return MI.getDesc().TSFlags & SIInstrFlags::DPP; in isDPP()
612 return get(Opcode).TSFlags & SIInstrFlags::DPP; in isDPP()
|
| /dports/emulators/qemu-utils/qemu-4.2.1/hw/ssi/ |
| H A D | aspeed_smc.c | 747 DPP = 0xa2, enumerator
756 case DPP: in aspeed_smc_num_dummies()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.h | 608 return MI.getDesc().TSFlags & SIInstrFlags::DPP; in isDPP()
612 return get(Opcode).TSFlags & SIInstrFlags::DPP; in isDPP()
|