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Searched refs:FRS1 (Results 51 – 75 of 110) sorted by relevance

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/dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/riscv/insns/
H A Dfmin_h.h3 WRITE_FRD(f16_min(f16(FRS1), f16(FRS2)));
H A Dfcvt_h_s.h4 WRITE_FRD(f32_to_f16(f32(FRS1)));
H A Dflt_h.h3 WRITE_RD(f16_lt(f16(FRS1), f16(FRS2)));
H A Dfmax_h.h3 WRITE_FRD(f16_max(f16(FRS1), f16(FRS2)));
H A Dfeq_h.h3 WRITE_RD(f16_eq(f16(FRS1), f16(FRS2)));
H A Dfsub_d.h4 WRITE_FRD(f64_sub(f64(FRS1), f64(FRS2)));
H A Dfsub_s.h4 WRITE_FRD(f32_sub(f32(FRS1), f32(FRS2)));
H A Dfadd_d.h4 WRITE_FRD(f64_add(f64(FRS1), f64(FRS2)));
H A Dfadd_s.h4 WRITE_FRD(f32_add(f32(FRS1), f32(FRS2)));
H A Dfcvt_h_d.h5 WRITE_FRD(f64_to_f16(f64(FRS1)));
H A Dfcvt_l_q.h5 WRITE_RD(f128_to_i64(f128(FRS1), RM, true));
H A Dfdiv_s.h4 WRITE_FRD(f32_div(f32(FRS1), f32(FRS2)));
H A Dfcvt_d_h.h5 WRITE_FRD(f16_to_f64(f16(FRS1)));
H A Dfcvt_h_q.h5 WRITE_FRD(f128_to_f16(f128(FRS1)));
H A Dfcvt_l_s.h5 WRITE_RD(f32_to_i64(f32(FRS1), RM, true));
H A Dfcvt_lu_d.h5 WRITE_RD(f64_to_ui64(f64(FRS1), RM, true));
H A Dfcvt_lu_q.h5 WRITE_RD(f128_to_ui64(f128(FRS1), RM, true));
H A Dfcvt_q_h.h5 WRITE_FRD(f16_to_f128(f16(FRS1)));
H A Dfcvt_wu_d.h4 WRITE_RD(sext32(f64_to_ui32(f64(FRS1), RM, true)));
H A Dfcvt_wu_s.h4 WRITE_RD(sext32(f32_to_ui32(f32(FRS1), RM, true)));
H A Dfdiv_q.h4 WRITE_FRD(f128_div(f128(FRS1), f128(FRS2)));
H A Dfmul_d.h4 WRITE_FRD(f64_mul(f64(FRS1), f64(FRS2)));
H A Dfmul_q.h4 WRITE_FRD(f128_mul(f128(FRS1), f128(FRS2)));
H A Dfmul_s.h4 WRITE_FRD(f32_mul(f32(FRS1), f32(FRS2)));
H A Dfsub_q.h4 WRITE_FRD(f128_sub(f128(FRS1), f128(FRS2)));

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