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Searched refs:FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT (Results 26 – 50 of 181) sorted by relevance

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/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dfirewall.h120 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0x98 macro
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/ddr/altera/
H A Dsdram_agilex.c126 FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT); in sdram_mmr_init_full()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dfirewall.h120 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0x98 macro
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/ddr/altera/
H A Dsdram_agilex.c126 FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT); in sdram_mmr_init_full()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/ddr/altera/
H A Dsdram_agilex.c126 FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT); in sdram_mmr_init_full()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dfirewall.h120 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0x98 macro
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dfirewall.h120 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0x98 macro
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/drivers/ddr/altera/
H A Dsdram_agilex.c126 FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT); in sdram_mmr_init_full()
/dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/ddr/altera/
H A Dsdram_agilex.c126 FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT); in sdram_mmr_init_full()
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/ddr/altera/
H A Dsdram_agilex.c126 FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT); in sdram_mmr_init_full()
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dfirewall.h120 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0x98 macro
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dfirewall_s10.h111 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0x98 macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dfirewall_s10.h111 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0x98 macro
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/ddr/altera/
H A Dsdram_agilex.c126 FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT); in sdram_mmr_init_full()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dfirewall.h120 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0x98 macro
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dfirewall.h120 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0x98 macro
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dfirewall.h120 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0x98 macro
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/ddr/altera/
H A Dsdram_agilex.c126 FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT); in sdram_mmr_init_full()
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/ddr/altera/
H A Dsdram_agilex.c126 FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT); in sdram_mmr_init_full()
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dfirewall.h120 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0x98 macro
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/ddr/altera/
H A Dsdram_agilex.c126 FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT); in sdram_mmr_init_full()
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/arm/mach-socfpga/include/mach/
H A Dfirewall.h120 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0x98 macro
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/ddr/altera/
H A Dsdram_agilex.c126 FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT); in sdram_mmr_init_full()
/dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/drivers/ddr/altera/
H A Dsdram_agilex.c126 FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT); in sdram_mmr_init_full()
/dports/sysutils/u-boot-pine64/u-boot-2021.07/drivers/ddr/altera/
H A Dsdram_agilex.c126 FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT); in sdram_mmr_init_full()

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