Home
last modified time | relevance | path

Searched refs:GPC_SLOT0_CFG (Results 51 – 62 of 62) sorted by relevance

123

/dports/sysutils/u-boot-rockpro64/u-boot-2021.07/arch/arm/mach-imx/mx7/
H A Dpsci-mx7.c24 #define GPC_SLOT0_CFG 0xb0 macro
426 writel(readl(GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4) | in imx_gpcv2_set_slot_ack()
428 GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4); in imx_gpcv2_set_slot_ack()
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/arch/arm/mach-imx/mx7/
H A Dpsci-mx7.c22 #define GPC_SLOT0_CFG 0xb0 macro
424 writel(readl(GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4) | in imx_gpcv2_set_slot_ack()
426 GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4); in imx_gpcv2_set_slot_ack()
/dports/sysutils/u-boot-qemu-riscv64/u-boot-2021.07/arch/arm/mach-imx/mx7/
H A Dpsci-mx7.c24 #define GPC_SLOT0_CFG 0xb0 macro
426 writel(readl(GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4) | in imx_gpcv2_set_slot_ack()
428 GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4); in imx_gpcv2_set_slot_ack()
/dports/sysutils/u-boot-qemu-arm/u-boot-2021.07/arch/arm/mach-imx/mx7/
H A Dpsci-mx7.c24 #define GPC_SLOT0_CFG 0xb0 macro
426 writel(readl(GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4) | in imx_gpcv2_set_slot_ack()
428 GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4); in imx_gpcv2_set_slot_ack()
/dports/sysutils/u-boot-rpi/u-boot-2021.07/arch/arm/mach-imx/mx7/
H A Dpsci-mx7.c24 #define GPC_SLOT0_CFG 0xb0 macro
426 writel(readl(GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4) | in imx_gpcv2_set_slot_ack()
428 GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4); in imx_gpcv2_set_slot_ack()
/dports/sysutils/u-boot-rpi-arm64/u-boot-2021.07/arch/arm/mach-imx/mx7/
H A Dpsci-mx7.c24 #define GPC_SLOT0_CFG 0xb0 macro
426 writel(readl(GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4) | in imx_gpcv2_set_slot_ack()
428 GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4); in imx_gpcv2_set_slot_ack()
/dports/sysutils/u-boot-rpi2/u-boot-2021.07/arch/arm/mach-imx/mx7/
H A Dpsci-mx7.c24 #define GPC_SLOT0_CFG 0xb0 macro
426 writel(readl(GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4) | in imx_gpcv2_set_slot_ack()
428 GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4); in imx_gpcv2_set_slot_ack()
/dports/sysutils/u-boot-riotboard/u-boot-2021.07/arch/arm/mach-imx/mx7/
H A Dpsci-mx7.c24 #define GPC_SLOT0_CFG 0xb0 macro
426 writel(readl(GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4) | in imx_gpcv2_set_slot_ack()
428 GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4); in imx_gpcv2_set_slot_ack()
/dports/sysutils/u-boot-rpi3/u-boot-2021.07/arch/arm/mach-imx/mx7/
H A Dpsci-mx7.c24 #define GPC_SLOT0_CFG 0xb0 macro
426 writel(readl(GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4) | in imx_gpcv2_set_slot_ack()
428 GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4); in imx_gpcv2_set_slot_ack()
/dports/sysutils/u-boot-rock-pi-4/u-boot-2021.07/arch/arm/mach-imx/mx7/
H A Dpsci-mx7.c24 #define GPC_SLOT0_CFG 0xb0 macro
426 writel(readl(GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4) | in imx_gpcv2_set_slot_ack()
428 GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4); in imx_gpcv2_set_slot_ack()
/dports/sysutils/u-boot-rock64/u-boot-2021.07/arch/arm/mach-imx/mx7/
H A Dpsci-mx7.c24 #define GPC_SLOT0_CFG 0xb0 macro
426 writel(readl(GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4) | in imx_gpcv2_set_slot_ack()
428 GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4); in imx_gpcv2_set_slot_ack()
/dports/sysutils/u-boot-rpi3-32/u-boot-2021.07/arch/arm/mach-imx/mx7/
H A Dpsci-mx7.c24 #define GPC_SLOT0_CFG 0xb0 macro
426 writel(readl(GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4) | in imx_gpcv2_set_slot_ack()
428 GPC_IPS_BASE_ADDR + GPC_SLOT0_CFG + index * 4); in imx_gpcv2_set_slot_ack()

123