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Searched refs:INVALID_REG (Results 76 – 100 of 261) sorted by relevance

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/dports/graphics/mesa-libs/mesa-21.3.6/src/freedreno/ir3/
H A Dir3_ra.c1330 ir3_dst_create(pcopy, INVALID_REG, in insert_parallel_copy_instr()
1340 ir3_src_create(pcopy, INVALID_REG, in insert_parallel_copy_instr()
1520 if (instr->dsts[0]->num == INVALID_REG) in handle_precolored_input()
1533 if (instr->dsts[0]->num != INVALID_REG) in handle_input()
1549 if (instr->dsts[0]->num == INVALID_REG) { in assign_input()
1613 assert(src->num != INVALID_REG); in handle_chmask()
1778 ir3_dst_create(pcopy, INVALID_REG, reg->flags & ~IR3_REG_SSA); in insert_liveout_copy()
1788 ir3_src_create(pcopy, INVALID_REG, reg->flags & ~IR3_REG_SSA); in insert_liveout_copy()
2131 if (dst->num != INVALID_REG) { in calc_min_limit_pressure()
H A Dir3_context.c594 src->array.base = INVALID_REG; in ir3_create_array_load()
629 dst->array.base = INVALID_REG; in ir3_create_array_store()
659 dst->array.base = INVALID_REG; in ir3_create_array_store()
H A Dir3_print.c222 if (reg->num != INVALID_REG && !(reg->flags & IR3_REG_ARRAY)) in print_ssa_name()
270 if (reg->array.base != INVALID_REG) in print_reg_name()
/dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/freedreno/ir3/
H A Dir3_ra.c1330 ir3_dst_create(pcopy, INVALID_REG, in insert_parallel_copy_instr()
1340 ir3_src_create(pcopy, INVALID_REG, in insert_parallel_copy_instr()
1520 if (instr->dsts[0]->num == INVALID_REG) in handle_precolored_input()
1533 if (instr->dsts[0]->num != INVALID_REG) in handle_input()
1549 if (instr->dsts[0]->num == INVALID_REG) { in assign_input()
1613 assert(src->num != INVALID_REG); in handle_chmask()
1778 ir3_dst_create(pcopy, INVALID_REG, reg->flags & ~IR3_REG_SSA); in insert_liveout_copy()
1788 ir3_src_create(pcopy, INVALID_REG, reg->flags & ~IR3_REG_SSA); in insert_liveout_copy()
2131 if (dst->num != INVALID_REG) { in calc_min_limit_pressure()
H A Dir3_context.c594 src->array.base = INVALID_REG; in ir3_create_array_load()
629 dst->array.base = INVALID_REG; in ir3_create_array_store()
659 dst->array.base = INVALID_REG; in ir3_create_array_store()
/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/freedreno/ir3/
H A Dir3_ra.c1330 ir3_dst_create(pcopy, INVALID_REG, in insert_parallel_copy_instr()
1340 ir3_src_create(pcopy, INVALID_REG, in insert_parallel_copy_instr()
1520 if (instr->dsts[0]->num == INVALID_REG) in handle_precolored_input()
1533 if (instr->dsts[0]->num != INVALID_REG) in handle_input()
1549 if (instr->dsts[0]->num == INVALID_REG) { in assign_input()
1613 assert(src->num != INVALID_REG); in handle_chmask()
1778 ir3_dst_create(pcopy, INVALID_REG, reg->flags & ~IR3_REG_SSA); in insert_liveout_copy()
1788 ir3_src_create(pcopy, INVALID_REG, reg->flags & ~IR3_REG_SSA); in insert_liveout_copy()
2131 if (dst->num != INVALID_REG) { in calc_min_limit_pressure()
H A Dir3_context.c594 src->array.base = INVALID_REG; in ir3_create_array_load()
629 dst->array.base = INVALID_REG; in ir3_create_array_store()
659 dst->array.base = INVALID_REG; in ir3_create_array_store()
/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/freedreno/ir3/
H A Dir3_ra.c1330 ir3_dst_create(pcopy, INVALID_REG, in insert_parallel_copy_instr()
1340 ir3_src_create(pcopy, INVALID_REG, in insert_parallel_copy_instr()
1520 if (instr->dsts[0]->num == INVALID_REG) in handle_precolored_input()
1533 if (instr->dsts[0]->num != INVALID_REG) in handle_input()
1549 if (instr->dsts[0]->num == INVALID_REG) { in assign_input()
1613 assert(src->num != INVALID_REG); in handle_chmask()
1778 ir3_dst_create(pcopy, INVALID_REG, reg->flags & ~IR3_REG_SSA); in insert_liveout_copy()
1788 ir3_src_create(pcopy, INVALID_REG, reg->flags & ~IR3_REG_SSA); in insert_liveout_copy()
2131 if (dst->num != INVALID_REG) { in calc_min_limit_pressure()
H A Dir3_context.c594 src->array.base = INVALID_REG; in ir3_create_array_load()
629 dst->array.base = INVALID_REG; in ir3_create_array_store()
659 dst->array.base = INVALID_REG; in ir3_create_array_store()
/dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/freedreno/ir3/
H A Dir3_ra.c1330 ir3_dst_create(pcopy, INVALID_REG, in insert_parallel_copy_instr()
1340 ir3_src_create(pcopy, INVALID_REG, in insert_parallel_copy_instr()
1520 if (instr->dsts[0]->num == INVALID_REG) in handle_precolored_input()
1533 if (instr->dsts[0]->num != INVALID_REG) in handle_input()
1549 if (instr->dsts[0]->num == INVALID_REG) { in assign_input()
1613 assert(src->num != INVALID_REG); in handle_chmask()
1778 ir3_dst_create(pcopy, INVALID_REG, reg->flags & ~IR3_REG_SSA); in insert_liveout_copy()
1788 ir3_src_create(pcopy, INVALID_REG, reg->flags & ~IR3_REG_SSA); in insert_liveout_copy()
2131 if (dst->num != INVALID_REG) { in calc_min_limit_pressure()
H A Dir3_context.c594 src->array.base = INVALID_REG; in ir3_create_array_load()
629 dst->array.base = INVALID_REG; in ir3_create_array_store()
659 dst->array.base = INVALID_REG; in ir3_create_array_store()
/dports/graphics/mesa-dri/mesa-21.3.6/src/freedreno/ir3/
H A Dir3_ra.c1330 ir3_dst_create(pcopy, INVALID_REG, in insert_parallel_copy_instr()
1340 ir3_src_create(pcopy, INVALID_REG, in insert_parallel_copy_instr()
1520 if (instr->dsts[0]->num == INVALID_REG) in handle_precolored_input()
1533 if (instr->dsts[0]->num != INVALID_REG) in handle_input()
1549 if (instr->dsts[0]->num == INVALID_REG) { in assign_input()
1613 assert(src->num != INVALID_REG); in handle_chmask()
1778 ir3_dst_create(pcopy, INVALID_REG, reg->flags & ~IR3_REG_SSA); in insert_liveout_copy()
1788 ir3_src_create(pcopy, INVALID_REG, reg->flags & ~IR3_REG_SSA); in insert_liveout_copy()
2131 if (dst->num != INVALID_REG) { in calc_min_limit_pressure()
H A Dir3_context.c594 src->array.base = INVALID_REG; in ir3_create_array_load()
629 dst->array.base = INVALID_REG; in ir3_create_array_store()
659 dst->array.base = INVALID_REG; in ir3_create_array_store()
/dports/lang/clover/mesa-21.3.6/src/freedreno/ir3/
H A Dir3_ra.c1330 ir3_dst_create(pcopy, INVALID_REG, in insert_parallel_copy_instr()
1340 ir3_src_create(pcopy, INVALID_REG, in insert_parallel_copy_instr()
1520 if (instr->dsts[0]->num == INVALID_REG) in handle_precolored_input()
1533 if (instr->dsts[0]->num != INVALID_REG) in handle_input()
1549 if (instr->dsts[0]->num == INVALID_REG) { in assign_input()
1613 assert(src->num != INVALID_REG); in handle_chmask()
1778 ir3_dst_create(pcopy, INVALID_REG, reg->flags & ~IR3_REG_SSA); in insert_liveout_copy()
1788 ir3_src_create(pcopy, INVALID_REG, reg->flags & ~IR3_REG_SSA); in insert_liveout_copy()
2131 if (dst->num != INVALID_REG) { in calc_min_limit_pressure()
H A Dir3_context.c594 src->array.base = INVALID_REG; in ir3_create_array_load()
629 dst->array.base = INVALID_REG; in ir3_create_array_store()
659 dst->array.base = INVALID_REG; in ir3_create_array_store()
/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/freedreno/ir3/
H A Dir3_context.c594 src->array.base = INVALID_REG; in ir3_create_array_load()
629 dst->array.base = INVALID_REG; in ir3_create_array_store()
659 dst->array.base = INVALID_REG; in ir3_create_array_store()
H A Dir3_print.c222 if (reg->num != INVALID_REG && !(reg->flags & IR3_REG_ARRAY)) in print_ssa_name()
270 if (reg->array.base != INVALID_REG) in print_reg_name()
/dports/emulators/dolphin-emu/dolphin-3152428/Source/Core/Core/PowerPC/Jit64/RegCache/
H A DJitRegCache.cpp565 X64Reg best_xreg = INVALID_REG; in GetFreeXReg()
582 if (best_xreg != INVALID_REG) in GetFreeXReg()
590 return INVALID_REG; in GetFreeXReg()
/dports/graphics/libosmesa/mesa-21.3.6/src/freedreno/ir3/
H A Dir3_context.c594 src->array.base = INVALID_REG; in ir3_create_array_load()
629 dst->array.base = INVALID_REG; in ir3_create_array_store()
659 dst->array.base = INVALID_REG; in ir3_create_array_store()
/dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/freedreno/ir3/
H A Dir3_context.c594 src->array.base = INVALID_REG; in ir3_create_array_load()
629 dst->array.base = INVALID_REG; in ir3_create_array_store()
659 dst->array.base = INVALID_REG; in ir3_create_array_store()
H A Dir3_ra.c1600 ir3_dst_create(pcopy, INVALID_REG, in insert_parallel_copy_instr()
1611 ir3_src_create(pcopy, INVALID_REG, in insert_parallel_copy_instr()
1797 if (instr->dsts[0]->num == INVALID_REG) in handle_precolored_input()
1810 if (instr->dsts[0]->num != INVALID_REG) in handle_input()
1826 if (instr->dsts[0]->num == INVALID_REG) { in assign_input()
1890 assert(src->num != INVALID_REG); in handle_chmask()
2056 struct ir3_register *dst_reg = ir3_dst_create(pcopy, INVALID_REG, flags); in insert_liveout_copy()
2065 struct ir3_register *src_reg = ir3_src_create(pcopy, INVALID_REG, flags); in insert_liveout_copy()
2408 if (dst->num != INVALID_REG) { in calc_min_limit_pressure()
H A Dinstr-a3xx.h494 #define INVALID_REG regid(63, 0) macro
495 #define VALIDREG(r) ((r) != INVALID_REG)
/dports/emulators/ppsspp/ppsspp-1.12.3/unittest/
H A DTestArm64Emitter.cpp280 emitter.ORRI2R(X1, X3, 0x3F, INVALID_REG); in TestArm64Emitter()
282 emitter.EORI2R(X1, X3, 0x3F0000003F0, INVALID_REG); in TestArm64Emitter()
/dports/emulators/libretro-ppsspp/ppsspp-1.12.3/unittest/
H A DTestArm64Emitter.cpp280 emitter.ORRI2R(X1, X3, 0x3F, INVALID_REG); in TestArm64Emitter()
282 emitter.EORI2R(X1, X3, 0x3F0000003F0, INVALID_REG); in TestArm64Emitter()
/dports/emulators/ppsspp-qt5/ppsspp-1.12.3/unittest/
H A DTestArm64Emitter.cpp280 emitter.ORRI2R(X1, X3, 0x3F, INVALID_REG); in TestArm64Emitter()
282 emitter.EORI2R(X1, X3, 0x3F0000003F0, INVALID_REG); in TestArm64Emitter()

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