/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/ |
H A D | start.S | 171 mtspr L1CSR1,r0 /* invalidate i-cache */ 1320 mfspr r0,L1CSR1 1324 mtspr L1CSR1,r0 1344 mfspr r4,L1CSR1 1347 mtspr L1CSR1,r4 1353 mfspr r0,L1CSR1 1357 mtspr L1CSR1,r0 1363 mfspr r3,L1CSR1
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/dports/sysutils/u-boot-beaglebone/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/ |
H A D | start.S | 171 mtspr L1CSR1,r0 /* invalidate i-cache */ 1320 mfspr r0,L1CSR1 1324 mtspr L1CSR1,r0 1344 mfspr r4,L1CSR1 1347 mtspr L1CSR1,r4 1353 mfspr r0,L1CSR1 1357 mtspr L1CSR1,r0 1363 mfspr r3,L1CSR1
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/dports/sysutils/u-boot-tools/u-boot-2020.07/arch/powerpc/cpu/mpc85xx/ |
H A D | start.S | 171 mtspr L1CSR1,r0 /* invalidate i-cache */ 1353 mfspr r0,L1CSR1 1357 mtspr L1CSR1,r0 1377 mfspr r4,L1CSR1 1380 mtspr L1CSR1,r4 1386 mfspr r0,L1CSR1 1390 mtspr L1CSR1,r0 1396 mfspr r3,L1CSR1
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/dports/sysutils/u-boot-bananapim2/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/ |
H A D | start.S | 171 mtspr L1CSR1,r0 /* invalidate i-cache */ 1320 mfspr r0,L1CSR1 1324 mtspr L1CSR1,r0 1344 mfspr r4,L1CSR1 1347 mtspr L1CSR1,r4 1353 mfspr r0,L1CSR1 1357 mtspr L1CSR1,r0 1363 mfspr r3,L1CSR1
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/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/ |
H A D | start.S | 171 mtspr L1CSR1,r0 /* invalidate i-cache */ 1320 mfspr r0,L1CSR1 1324 mtspr L1CSR1,r0 1344 mfspr r4,L1CSR1 1347 mtspr L1CSR1,r4 1353 mfspr r0,L1CSR1 1357 mtspr L1CSR1,r0 1363 mfspr r3,L1CSR1
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/dports/sysutils/u-boot-rockpro64/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/ |
H A D | start.S | 171 mtspr L1CSR1,r0 /* invalidate i-cache */ 1320 mfspr r0,L1CSR1 1324 mtspr L1CSR1,r0 1344 mfspr r4,L1CSR1 1347 mtspr L1CSR1,r4 1353 mfspr r0,L1CSR1 1357 mtspr L1CSR1,r0 1363 mfspr r3,L1CSR1
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/dports/sysutils/u-boot-sifive-fu540/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/ |
H A D | start.S | 171 mtspr L1CSR1,r0 /* invalidate i-cache */ 1320 mfspr r0,L1CSR1 1324 mtspr L1CSR1,r0 1344 mfspr r4,L1CSR1 1347 mtspr L1CSR1,r4 1353 mfspr r0,L1CSR1 1357 mtspr L1CSR1,r0 1363 mfspr r3,L1CSR1
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/dports/sysutils/u-boot-rpi3-32/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/ |
H A D | start.S | 171 mtspr L1CSR1,r0 /* invalidate i-cache */ 1320 mfspr r0,L1CSR1 1324 mtspr L1CSR1,r0 1344 mfspr r4,L1CSR1 1347 mtspr L1CSR1,r4 1353 mfspr r0,L1CSR1 1357 mtspr L1CSR1,r0 1363 mfspr r3,L1CSR1
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/dports/sysutils/u-boot-rpi4/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/ |
H A D | start.S | 171 mtspr L1CSR1,r0 /* invalidate i-cache */ 1320 mfspr r0,L1CSR1 1324 mtspr L1CSR1,r0 1344 mfspr r4,L1CSR1 1347 mtspr L1CSR1,r4 1353 mfspr r0,L1CSR1 1357 mtspr L1CSR1,r0 1363 mfspr r3,L1CSR1
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/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/arch/powerpc/cpu/mpc85xx/ |
H A D | start.S | 171 mtspr L1CSR1,r0 /* invalidate i-cache */ 1350 mfspr r0,L1CSR1 1354 mtspr L1CSR1,r0 1374 mfspr r4,L1CSR1 1377 mtspr L1CSR1,r4 1383 mfspr r0,L1CSR1 1387 mtspr L1CSR1,r0 1393 mfspr r3,L1CSR1
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/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/ |
H A D | start.S | 171 mtspr L1CSR1,r0 /* invalidate i-cache */ 1320 mfspr r0,L1CSR1 1324 mtspr L1CSR1,r0 1344 mfspr r4,L1CSR1 1347 mtspr L1CSR1,r4 1353 mfspr r0,L1CSR1 1357 mtspr L1CSR1,r0 1363 mfspr r3,L1CSR1
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/dports/sysutils/u-boot-qemu-riscv64/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/ |
H A D | start.S | 171 mtspr L1CSR1,r0 /* invalidate i-cache */ 1320 mfspr r0,L1CSR1 1324 mtspr L1CSR1,r0 1344 mfspr r4,L1CSR1 1347 mtspr L1CSR1,r4 1353 mfspr r0,L1CSR1 1357 mtspr L1CSR1,r0 1363 mfspr r3,L1CSR1
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/dports/sysutils/u-boot-qemu-arm/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/ |
H A D | start.S | 171 mtspr L1CSR1,r0 /* invalidate i-cache */ 1320 mfspr r0,L1CSR1 1324 mtspr L1CSR1,r0 1344 mfspr r4,L1CSR1 1347 mtspr L1CSR1,r4 1353 mfspr r0,L1CSR1 1357 mtspr L1CSR1,r0 1363 mfspr r3,L1CSR1
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/dports/sysutils/u-boot-rpi/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/ |
H A D | start.S | 171 mtspr L1CSR1,r0 /* invalidate i-cache */ 1320 mfspr r0,L1CSR1 1324 mtspr L1CSR1,r0 1344 mfspr r4,L1CSR1 1347 mtspr L1CSR1,r4 1353 mfspr r0,L1CSR1 1357 mtspr L1CSR1,r0 1363 mfspr r3,L1CSR1
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/dports/sysutils/u-boot-rpi-arm64/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/ |
H A D | start.S | 171 mtspr L1CSR1,r0 /* invalidate i-cache */ 1320 mfspr r0,L1CSR1 1324 mtspr L1CSR1,r0 1344 mfspr r4,L1CSR1 1347 mtspr L1CSR1,r4 1353 mfspr r0,L1CSR1 1357 mtspr L1CSR1,r0 1363 mfspr r3,L1CSR1
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/dports/sysutils/u-boot-rpi2/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/ |
H A D | start.S | 171 mtspr L1CSR1,r0 /* invalidate i-cache */ 1320 mfspr r0,L1CSR1 1324 mtspr L1CSR1,r0 1344 mfspr r4,L1CSR1 1347 mtspr L1CSR1,r4 1353 mfspr r0,L1CSR1 1357 mtspr L1CSR1,r0 1363 mfspr r3,L1CSR1
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/dports/sysutils/u-boot-riotboard/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/ |
H A D | start.S | 171 mtspr L1CSR1,r0 /* invalidate i-cache */ 1320 mfspr r0,L1CSR1 1324 mtspr L1CSR1,r0 1344 mfspr r4,L1CSR1 1347 mtspr L1CSR1,r4 1353 mfspr r0,L1CSR1 1357 mtspr L1CSR1,r0 1363 mfspr r3,L1CSR1
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/dports/sysutils/u-boot-rpi3/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/ |
H A D | start.S | 171 mtspr L1CSR1,r0 /* invalidate i-cache */ 1320 mfspr r0,L1CSR1 1324 mtspr L1CSR1,r0 1344 mfspr r4,L1CSR1 1347 mtspr L1CSR1,r4 1353 mfspr r0,L1CSR1 1357 mtspr L1CSR1,r0 1363 mfspr r3,L1CSR1
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/dports/sysutils/u-boot-rock-pi-4/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/ |
H A D | start.S | 171 mtspr L1CSR1,r0 /* invalidate i-cache */ 1320 mfspr r0,L1CSR1 1324 mtspr L1CSR1,r0 1344 mfspr r4,L1CSR1 1347 mtspr L1CSR1,r4 1353 mfspr r0,L1CSR1 1357 mtspr L1CSR1,r0 1363 mfspr r3,L1CSR1
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/dports/sysutils/u-boot-rock64/u-boot-2021.07/arch/powerpc/cpu/mpc85xx/ |
H A D | start.S | 171 mtspr L1CSR1,r0 /* invalidate i-cache */ 1320 mfspr r0,L1CSR1 1324 mtspr L1CSR1,r0 1344 mfspr r4,L1CSR1 1347 mtspr L1CSR1,r4 1353 mfspr r0,L1CSR1 1357 mtspr L1CSR1,r0 1363 mfspr r3,L1CSR1
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/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/powerpc/include/asm/ |
H A D | processor.h | 734 #define L1CSR1 SPRN_L1CSR1 macro
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/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/powerpc/include/asm/ |
H A D | processor.h | 734 #define L1CSR1 SPRN_L1CSR1 macro
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/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/powerpc/include/asm/ |
H A D | processor.h | 734 #define L1CSR1 SPRN_L1CSR1 macro
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/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/powerpc/include/asm/ |
H A D | processor.h | 734 #define L1CSR1 SPRN_L1CSR1 macro
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/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/powerpc/include/asm/ |
H A D | processor.h | 734 #define L1CSR1 SPRN_L1CSR1 macro
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