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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/Transforms/SLPVectorizer/AMDGPU/
H A Dreduction.ll278 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], i16 [[ELT3]], i16 [[MIN2]]
279 ; VI-NEXT: ret i16 [[MIN3]]
318 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
319 ; VI-NEXT: [[CMP3:%.*]] = icmp ult i16 [[ELT4]], [[MIN3]]
320 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
388 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
389 ; VI-NEXT: [[CMP3:%.*]] = icmp slt i16 [[ELT4]], [[MIN3]]
390 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
594 ; GCN-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], half [[ELT3]], half [[MIN2]]
595 ; GCN-NEXT: ret half [[MIN3]]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/Transforms/SLPVectorizer/AMDGPU/
H A Dreduction.ll278 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], i16 [[ELT3]], i16 [[MIN2]]
279 ; VI-NEXT: ret i16 [[MIN3]]
318 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
319 ; VI-NEXT: [[CMP3:%.*]] = icmp ult i16 [[ELT4]], [[MIN3]]
320 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
388 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
389 ; VI-NEXT: [[CMP3:%.*]] = icmp slt i16 [[ELT4]], [[MIN3]]
390 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
594 ; GCN-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], half [[ELT3]], half [[MIN2]]
595 ; GCN-NEXT: ret half [[MIN3]]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/Transforms/SLPVectorizer/AMDGPU/
H A Dreduction.ll278 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], i16 [[ELT3]], i16 [[MIN2]]
279 ; VI-NEXT: ret i16 [[MIN3]]
318 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
319 ; VI-NEXT: [[CMP3:%.*]] = icmp ult i16 [[ELT4]], [[MIN3]]
320 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
388 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
389 ; VI-NEXT: [[CMP3:%.*]] = icmp slt i16 [[ELT4]], [[MIN3]]
390 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
594 ; GCN-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], half [[ELT3]], half [[MIN2]]
595 ; GCN-NEXT: ret half [[MIN3]]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/Transforms/SLPVectorizer/AMDGPU/
H A Dreduction.ll278 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], i16 [[ELT3]], i16 [[MIN2]]
279 ; VI-NEXT: ret i16 [[MIN3]]
318 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
319 ; VI-NEXT: [[CMP3:%.*]] = icmp ult i16 [[ELT4]], [[MIN3]]
320 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
388 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
389 ; VI-NEXT: [[CMP3:%.*]] = icmp slt i16 [[ELT4]], [[MIN3]]
390 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
594 ; GCN-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], half [[ELT3]], half [[MIN2]]
595 ; GCN-NEXT: ret half [[MIN3]]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/Transforms/SLPVectorizer/AMDGPU/
H A Dreduction.ll278 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], i16 [[ELT3]], i16 [[MIN2]]
279 ; VI-NEXT: ret i16 [[MIN3]]
318 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
319 ; VI-NEXT: [[CMP3:%.*]] = icmp ult i16 [[ELT4]], [[MIN3]]
320 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
388 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
389 ; VI-NEXT: [[CMP3:%.*]] = icmp slt i16 [[ELT4]], [[MIN3]]
390 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
594 ; GCN-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], half [[ELT3]], half [[MIN2]]
595 ; GCN-NEXT: ret half [[MIN3]]
/dports/math/gap/gap-4.11.0/pkg/digraphs-1.1.1/extern/edge-addition-planarity-suite-Version_3.0.0.5/c/
H A DgraphIsolator.c174 theGraph->functions.fpMarkDFSPath(theGraph, MIN3(IC->ux,IC->uy,IC->uz), in _IsolateMinorB()
266 theGraph->functions.fpMarkDFSPath(theGraph, MIN3(IC->ux, IC->uy, IC->uz), IC->r) != OK || in _IsolateMinorE()
354 if (theGraph->functions.fpMarkDFSPath(theGraph, MIN3(IC->ux, IC->uy, IC->uz), IC->r) != OK || in _IsolateMinorE3()
386 if (theGraph->functions.fpMarkDFSPath(theGraph, MIN3(IC->ux, IC->uy, IC->uz), in _IsolateMinorE4()
/dports/math/planarity/edge-addition-planarity-suite-Version_3.0.1.1/c/
H A DgraphIsolator.c174 theGraph->functions.fpMarkDFSPath(theGraph, MIN3(IC->ux,IC->uy,IC->uz), in _IsolateMinorB()
266 theGraph->functions.fpMarkDFSPath(theGraph, MIN3(IC->ux, IC->uy, IC->uz), IC->r) != OK || in _IsolateMinorE()
354 if (theGraph->functions.fpMarkDFSPath(theGraph, MIN3(IC->ux, IC->uy, IC->uz), IC->r) != OK || in _IsolateMinorE3()
386 if (theGraph->functions.fpMarkDFSPath(theGraph, MIN3(IC->ux, IC->uy, IC->uz), in _IsolateMinorE4()
/dports/graphics/gegl/gegl-0.4.34/operations/common-gpl3+/
H A Dlens-distortion.c70 #define MIN3(x,y,z) (MIN (MIN ((x),(y)),(z)))
191 area.x = floor (MIN3 (x1, x3, x5)) - 1;
209 area.y = floor (MIN3 (y1, y2, y5)) - 1;
/dports/security/yersinia/yersinia-8c0d7c5/src/
H A Dparser.h31 #define MIN3(a,b,c) ((a)<(b)?(MIN2(a,c)):(MIN2(b,c))) macro
/dports/graphics/photoflow/PhotoFlow-8472024f/src/operations/
H A Ddesaturate_lightness.hh53 … static_cast< typename FormatInfo<T>::PROMOTED >(MIN3(pp[x], pp[x+1], pp[x+2])) )/2 ); in process()
/dports/science/hdf5-18/hdf5-1.8.21/tools/misc/
H A Dh5repart.c41 #ifndef MIN3
42 # define MIN3(X,Y,Z) MIN(MIN(X,Y),Z) macro
/dports/cad/sumo/sumo-1.2.0/src/utils/common/
H A DStdDefs.h84 MIN3(T a, T b, T c) { in MIN3() function
/dports/cad/sumo/sumo-1.2.0/src/microsim/cfmodels/
H A DMSCFModel_Daniel1.cpp60 … const double vMax = MIN3(veh->getLane()->getVehicleMaxSpeed(veh), maxNextSpeed(oldV, veh), vSafe); in finalizeSpeed()
H A DMSCFModel_Kerner.cpp86 double va = MAX2((double) 0, MIN3(vfree, vsafe, vcond)) + vars->rand; in _v()
/dports/devel/ode/ode-0.13/GIMPACT/include/GIMPACT/
H A Dgim_math.h106 #define MIN3(a,b,c) MIN(a,MIN(b,c)) macro
/dports/multimedia/ccextractor/ccextractor-0.85/src/lib_ccx/
H A Dutility.c152 #define MIN3(a, b, c) ((a) < (b) ? ((a) < (c) ? (a) : (c)) : ((b) < (c) ? (b) : (c))) macro
166 column[y] = MIN3(column[y] + 1, column[y-1] + 1, lastdiag + (s1[y-1] == s2[x-1] ? 0 : 1)); in levenshtein_dist()
187 column[y] = MIN3(column[y] + 1, column[y-1] + 1, lastdiag + (s1[y-1] == s2[x-1] ? 0 : 1)); in levenshtein_dist_char()
/dports/biology/viennarna/ViennaRNA-2.4.18/src/ViennaRNA/utils/
H A Dbasic.h116 #define MIN3(A, B, C) (MIN2((MIN2((A), (B))), (C))) macro
/dports/graphics/mypaint/mypaint-2.0.1/lib/
H A Dhelpers2.hpp13 #define MIN3(a, b, c) ((a)<(b)?MIN((a),(c)):MIN((b),(c))) macro
/dports/science/InsightToolkit/ITK-5.0.1/Modules/ThirdParty/MINC/src/libminc/volume_io/Include/volume_io/
H A Dbasic.h105 #define MIN3( x, y, z ) ( ((x) <= (y)) ? MIN( x, z ) : MIN( y, z ) ) macro
/dports/graphics/gimp-app/gimp-2.10.30/libgimp/
H A Dgimpdrawablepreview.c582 #define MIN3(a, b, c) (MIN (MIN ((a), (b)), (c))) macro
611 *xmax = MIN3 (x2 + SELECTION_BORDER, width, width + offset_x); in _gimp_drawable_preview_get_bounds()
612 *ymax = MIN3 (y2 + SELECTION_BORDER, height, height + offset_y); in _gimp_drawable_preview_get_bounds()
/dports/audio/vorbis-tools/vorbis-tools-1.4.2/ogg123/
H A Dbuffer.c37 #define MIN3(x,y,z) MIN(x,MIN(y,z))
191 return MIN3(buf->curfill, (long)request_size, buf->size - buf->start);
332 write_size = MIN3(size, buf->size - buf->curfill,
/dports/math/grace/grace-5.1.25/src/
H A Dutils.h39 #define MIN3(a, b, c) (((a) < (b)) ? MIN2(a, c) : MIN2(b, c)) macro
/dports/emulators/qemu/qemu-6.2.0/target/hexagon/imported/mmvec/
H A Dencode_ext.def67 …fine LDST_ENC(TAG,MAJ3,MID3,RREG,TINY6,MIN3,VREG) DEF_ENC(TAG, ICLASS_NCJ "1" #MAJ3 #MID3 #RREG "P…
69 #define LDST_BO(TAGPRE,MID3,PRED,MIN3,VREG) LDST_ENC(TAGPRE##_ai, 000,MID3,ttttt,i PRED iii,MIN3,VR…
70 #define LDST_PI(TAGPRE,MID3,PRED,MIN3,VREG) LDST_ENC(TAGPRE##_pi, 001,MID3,xxxxx,- PRED iii,MIN3,VR…
71 #define LDST_PM(TAGPRE,MID3,PRED,MIN3,VREG) LDST_ENC(TAGPRE##_ppu,011,MID3,xxxxx,u PRED ---,MIN3,VR…
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/Transforms/SLPVectorizer/AMDGPU/
H A Dreduction.ll312 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], i16 [[ELT3]], i16 [[MIN2]]
313 ; VI-NEXT: ret i16 [[MIN3]]
361 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
362 ; VI-NEXT: [[CMP3:%.*]] = icmp ult i16 [[ELT4]], [[MIN3]]
363 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
443 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
444 ; VI-NEXT: [[CMP3:%.*]] = icmp slt i16 [[ELT4]], [[MIN3]]
445 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
679 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], half [[ELT3]], half [[MIN2]]
680 ; VI-NEXT: ret half [[MIN3]]
/dports/devel/llvm11/llvm-11.0.1.src/test/Transforms/SLPVectorizer/AMDGPU/
H A Dreduction.ll312 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], i16 [[ELT3]], i16 [[MIN2]]
313 ; VI-NEXT: ret i16 [[MIN3]]
361 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
362 ; VI-NEXT: [[CMP3:%.*]] = icmp ult i16 [[ELT4]], [[MIN3]]
363 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
443 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
444 ; VI-NEXT: [[CMP3:%.*]] = icmp slt i16 [[ELT4]], [[MIN3]]
445 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
679 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], half [[ELT3]], half [[MIN2]]
680 ; VI-NEXT: ret half [[MIN3]]

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