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/dports/devel/llvm10/llvm-10.0.1.src/test/Transforms/SLPVectorizer/AMDGPU/
H A Dreduction.ll312 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], i16 [[ELT3]], i16 [[MIN2]]
313 ; VI-NEXT: ret i16 [[MIN3]]
361 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
362 ; VI-NEXT: [[CMP3:%.*]] = icmp ult i16 [[ELT4]], [[MIN3]]
363 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
443 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
444 ; VI-NEXT: [[CMP3:%.*]] = icmp slt i16 [[ELT4]], [[MIN3]]
445 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
679 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], half [[ELT3]], half [[MIN2]]
680 ; VI-NEXT: ret half [[MIN3]]
/dports/devel/llvm90/llvm-9.0.1.src/test/Transforms/SLPVectorizer/AMDGPU/
H A Dreduction.ll312 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], i16 [[ELT3]], i16 [[MIN2]]
313 ; VI-NEXT: ret i16 [[MIN3]]
361 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
362 ; VI-NEXT: [[CMP3:%.*]] = icmp ult i16 [[ELT4]], [[MIN3]]
363 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
443 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
444 ; VI-NEXT: [[CMP3:%.*]] = icmp slt i16 [[ELT4]], [[MIN3]]
445 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
679 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], half [[ELT3]], half [[MIN2]]
680 ; VI-NEXT: ret half [[MIN3]]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/Transforms/SLPVectorizer/AMDGPU/
H A Dreduction.ll312 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], i16 [[ELT3]], i16 [[MIN2]]
313 ; VI-NEXT: ret i16 [[MIN3]]
361 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
362 ; VI-NEXT: [[CMP3:%.*]] = icmp ult i16 [[ELT4]], [[MIN3]]
363 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
443 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
444 ; VI-NEXT: [[CMP3:%.*]] = icmp slt i16 [[ELT4]], [[MIN3]]
445 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
661 ; GCN-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], half [[ELT3]], half [[MIN2]]
662 ; GCN-NEXT: ret half [[MIN3]]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/Transforms/SLPVectorizer/AMDGPU/
H A Dreduction.ll312 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], i16 [[ELT3]], i16 [[MIN2]]
313 ; VI-NEXT: ret i16 [[MIN3]]
361 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
362 ; VI-NEXT: [[CMP3:%.*]] = icmp ult i16 [[ELT4]], [[MIN3]]
363 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
443 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
444 ; VI-NEXT: [[CMP3:%.*]] = icmp slt i16 [[ELT4]], [[MIN3]]
445 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
679 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], half [[ELT3]], half [[MIN2]]
680 ; VI-NEXT: ret half [[MIN3]]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/Transforms/SLPVectorizer/AMDGPU/
H A Dreduction.ll312 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], i16 [[ELT3]], i16 [[MIN2]]
313 ; VI-NEXT: ret i16 [[MIN3]]
361 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
362 ; VI-NEXT: [[CMP3:%.*]] = icmp ult i16 [[ELT4]], [[MIN3]]
363 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
443 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
444 ; VI-NEXT: [[CMP3:%.*]] = icmp slt i16 [[ELT4]], [[MIN3]]
445 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
661 ; GCN-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], half [[ELT3]], half [[MIN2]]
662 ; GCN-NEXT: ret half [[MIN3]]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/Transforms/SLPVectorizer/AMDGPU/
H A Dreduction.ll312 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], i16 [[ELT3]], i16 [[MIN2]]
313 ; VI-NEXT: ret i16 [[MIN3]]
361 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
362 ; VI-NEXT: [[CMP3:%.*]] = icmp ult i16 [[ELT4]], [[MIN3]]
363 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
443 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
444 ; VI-NEXT: [[CMP3:%.*]] = icmp slt i16 [[ELT4]], [[MIN3]]
445 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
661 ; GCN-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], half [[ELT3]], half [[MIN2]]
662 ; GCN-NEXT: ret half [[MIN3]]
/dports/devel/llvm80/llvm-8.0.1.src/test/Transforms/SLPVectorizer/AMDGPU/
H A Dreduction.ll312 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], i16 [[ELT3]], i16 [[MIN2]]
313 ; VI-NEXT: ret i16 [[MIN3]]
361 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
362 ; VI-NEXT: [[CMP3:%.*]] = icmp ult i16 [[ELT4]], [[MIN3]]
363 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
443 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
444 ; VI-NEXT: [[CMP3:%.*]] = icmp slt i16 [[ELT4]], [[MIN3]]
445 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
679 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], half [[ELT3]], half [[MIN2]]
680 ; VI-NEXT: ret half [[MIN3]]
/dports/devel/llvm70/llvm-7.0.1.src/test/Transforms/SLPVectorizer/AMDGPU/
H A Dreduction.ll312 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], i16 [[ELT3]], i16 [[MIN2]]
313 ; VI-NEXT: ret i16 [[MIN3]]
361 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
362 ; VI-NEXT: [[CMP3:%.*]] = icmp ult i16 [[ELT4]], [[MIN3]]
363 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
443 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP2]], i16 [[ELT3]], i16 [[MIN2]]
444 ; VI-NEXT: [[CMP3:%.*]] = icmp slt i16 [[ELT4]], [[MIN3]]
445 ; VI-NEXT: [[MIN4:%.*]] = select i1 [[CMP3]], i16 [[ELT4]], i16 [[MIN3]]
679 ; VI-NEXT: [[MIN3:%.*]] = select i1 [[CMP3]], half [[ELT3]], half [[MIN2]]
680 ; VI-NEXT: ret half [[MIN3]]
/dports/x11/tint/tint2-78313502d3b26c217f5583a23ef571bc9e0edc45/src/util/
H A Dcommon.h20 #define MIN3(a, b, c) MIN(MIN(a, b), c) macro
/dports/science/minc2/minc-release-2.2.00/volume_io/Include/volume_io/
H A Dbasic.h128 #define MIN3( x, y, z ) ( ((x) <= (y)) ? MIN( x, z ) : MIN( y, z ) ) macro
/dports/graphics/piglit/piglit-136a7f5fa0703603be1ffb338abe4865e76a8058/tests/spec/arb_point_sprite/
H A Dmipmap.c153 max_point_size = MIN3(point_size_range[1], piglit_width / 2, in piglit_display()
/dports/graphics/photoflow/PhotoFlow-8472024f/src/operations/
H A Dclipping_warning.hh115 if( opar->get_shadows_warning() && MIN3(p[x],p[x+1],p[x+2])<=min ) { in render()
/dports/x11/libX11/libX11-1.7.2/src/xcms/
H A DLRGB.c59 #ifndef MIN3
60 #define MIN3(x,y,z) ((x) > (MIN((y), (z))) ? (MIN((y), (z))) : (x)) macro
1521 if ((MIN3 (tmp[0], tmp[1], tmp[2]) < -EPS) || in XcmsCIEXYZToRGBi()
1551 if ((MIN3 (tmp[0], tmp[1], tmp[2]) < -EPS) || in XcmsCIEXYZToRGBi()
/dports/science/InsightToolkit/ITK-5.0.1/Modules/ThirdParty/HDF5/src/itkhdf5/src/
H A DH5Tbit.c73 size_t nbits = MIN3(size, 8 - dst_offset, 8 - src_offset); in H5T__bit_copy()
131 size_t nbits = (size_t)MIN3 (size, 8 - dst_offset, 8 - src_offset); in H5T__bit_copy()
/dports/science/hdf5-18/hdf5-1.8.21/src/
H A DH5Tbit.c79 size_t nbits = MIN3(size, 8 - dst_offset, 8 - src_offset); in H5T__bit_copy()
138 size_t nbits = (size_t)MIN3 (size, 8 - dst_offset, 8 - src_offset); in H5T__bit_copy()
/dports/science/hdf5/hdf5-1.10.6/src/
H A DH5Tbit.c73 size_t nbits = MIN3(size, 8 - dst_offset, 8 - src_offset); in H5T__bit_copy()
131 size_t nbits = (size_t)MIN3 (size, 8 - dst_offset, 8 - src_offset); in H5T__bit_copy()
/dports/math/vtk8/VTK-8.2.0/ThirdParty/hdf5/vtkhdf5/src/
H A DH5Tbit.c79 size_t nbits = MIN3(size, 8 - dst_offset, 8 - src_offset); in H5T__bit_copy()
138 size_t nbits = (size_t)MIN3 (size, 8 - dst_offset, 8 - src_offset); in H5T__bit_copy()
/dports/math/vtk6/VTK-6.2.0/ThirdParty/hdf5/vtkhdf5/src/
H A DH5Tbit.c81 unsigned nbits = MIN3(size, 8 - dst_offset, 8 - src_offset); in H5T__bit_copy()
140 unsigned nbits = (unsigned)MIN3 (size, 8 - dst_offset, 8 - src_offset); in H5T__bit_copy()
/dports/math/vtk9/VTK-9.1.0/ThirdParty/hdf5/vtkhdf5/src/
H A DH5Tbit.c69 size_t nbits = MIN3(size, 8 - dst_offset, 8 - src_offset); in H5T__bit_copy()
127 size_t nbits = (size_t)MIN3(size, 8 - dst_offset, 8 - src_offset); in H5T__bit_copy()
/dports/x11/fireflies/fireflies-2.07/src/
H A Dutils.cc35 min = MIN3(rgb[0], rgb[1], rgb[2]); in rgb_to_hsv()
/dports/graphics/photoflow/PhotoFlow-8472024f/src/gui/operations/
H A Dwhite_balance_config.cc305 #define MIN3( a, b, c ) MIN(a,MIN(b,c)) macro
416 double min_mul = MIN3(cam_mul[0], cam_mul[1], cam_mul[2]); in temp_tint_changed()
997 float norm_in = MIN3(wb_red_in,wb_green_in,wb_blue_in); in color_spot_wb()
1267 float scale = MIN3(wb_red_out,wb_green_out,wb_blue_out); in color_spot_wb()
/dports/math/onednn/oneDNN-2.5.1/tests/benchdnn/
H A Dcommon.hpp43 #define MIN3(a, b, c) MIN2(a, MIN2(b, c)) macro
/dports/www/firefox/firefox-99.0/third_party/rust/glslopt/glsl-optimizer/src/util/
H A Dmacros.h301 #define MIN3( A, B, C ) ((A) < (B) ? MIN2(A, C) : MIN2(B, C))
/dports/mail/thunderbird/thunderbird-91.8.0/third_party/rust/glslopt/glsl-optimizer/src/util/
H A Dmacros.h301 #define MIN3( A, B, C ) ((A) < (B) ? MIN2(A, C) : MIN2(B, C))
/dports/www/firefox-esr/firefox-91.8.0/third_party/rust/glslopt/glsl-optimizer/src/util/
H A Dmacros.h301 #define MIN3( A, B, C ) ((A) < (B) ? MIN2(A, C) : MIN2(B, C))

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