| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/mtd/nand/raw/ |
| H A D | pxa3xx_nand.c | 423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/mtd/nand/raw/ |
| H A D | pxa3xx_nand.c | 423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
|
| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/drivers/mtd/nand/raw/ |
| H A D | pxa3xx_nand.c | 423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
|
| /dports/sysutils/u-boot-pine64/u-boot-2021.07/drivers/mtd/nand/raw/ |
| H A D | pxa3xx_nand.c | 423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
|
| /dports/sysutils/u-boot-pine-h64/u-boot-2021.07/drivers/mtd/nand/raw/ |
| H A D | pxa3xx_nand.c | 423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
|
| /dports/sysutils/u-boot-pcduino3/u-boot-2021.07/drivers/mtd/nand/raw/ |
| H A D | pxa3xx_nand.c | 423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
|
| /dports/sysutils/u-boot-pinebookpro/u-boot-2021.07/drivers/mtd/nand/raw/ |
| H A D | pxa3xx_nand.c | 423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
|
| /dports/sysutils/u-boot-pinebook/u-boot-2021.07/drivers/mtd/nand/raw/ |
| H A D | pxa3xx_nand.c | 423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
|
| /dports/sysutils/u-boot-pine64-lts/u-boot-2021.07/drivers/mtd/nand/raw/ |
| H A D | pxa3xx_nand.c | 423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/mtd/nand/raw/ |
| H A D | pxa3xx_nand.c | 423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
|
| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/drivers/mtd/nand/raw/ |
| H A D | pxa3xx_nand.c | 423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
|
| /dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/drivers/mtd/nand/raw/ |
| H A D | pxa3xx_nand.c | 423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
|
| /dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/drivers/mtd/nand/raw/ |
| H A D | pxa3xx_nand.c | 423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
|
| /dports/emulators/qemu/qemu-6.2.0/roms/u-boot/drivers/mtd/nand/raw/ |
| H A D | pxa3xx_nand.c | 423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
|
| /dports/sysutils/u-boot-orangepi-pc2/u-boot-2021.07/drivers/mtd/nand/raw/ |
| H A D | pxa3xx_nand.c | 423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
|
| /dports/sysutils/u-boot-orangepi-plus-2e/u-boot-2021.07/drivers/mtd/nand/raw/ |
| H A D | pxa3xx_nand.c | 423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
|
| /dports/sysutils/u-boot-orangepi-pc/u-boot-2021.07/drivers/mtd/nand/raw/ |
| H A D | pxa3xx_nand.c | 423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
|
| /dports/sysutils/u-boot-orangepi-one/u-boot-2021.07/drivers/mtd/nand/raw/ |
| H A D | pxa3xx_nand.c | 423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
|
| /dports/sysutils/u-boot-orangepi-pc-plus/u-boot-2021.07/drivers/mtd/nand/raw/ |
| H A D | pxa3xx_nand.c | 423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
|
| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/drivers/mtd/nand/raw/ |
| H A D | pxa3xx_nand.c | 423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
|
| /dports/sysutils/u-boot-bananapim2/u-boot-2021.07/drivers/mtd/nand/raw/ |
| H A D | pxa3xx_nand.c | 423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
|
| /dports/sysutils/u-boot-bananapi/u-boot-2021.07/drivers/mtd/nand/raw/ |
| H A D | pxa3xx_nand.c | 423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/mtd/nand/raw/ |
| H A D | pxa3xx_nand.c | 423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/mtd/nand/raw/ |
| H A D | pxa3xx_nand.c | 423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
|
| /dports/sysutils/u-boot-rock64/u-boot-2021.07/drivers/mtd/nand/raw/ |
| H A D | pxa3xx_nand.c | 423 #define NDTR1_tR(c) (min((c), 65535) << 16) macro
461 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | in pxa3xx_nand_set_timing()
500 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | in pxa3xx_nand_set_sdr_timing()
|