| /dports/devel/llvm80/llvm-8.0.1.src/lib/Target/ARM/ |
| H A D | ARMCallLowering.cpp | 104 unsigned OffsetReg = MRI.createGenericVirtualRegister(s32); in getStackAddress() local
105 MIRBuilder.buildConstant(OffsetReg, Offset); in getStackAddress()
108 MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg); in getStackAddress()
|
| /dports/devel/llvm80/llvm-8.0.1.src/lib/Target/Mips/ |
| H A D | MipsCallLowering.cpp | 229 unsigned OffsetReg = MRI.createGenericVirtualRegister(s32); in getStackAddress() local
231 MIRBuilder.buildConstant(OffsetReg, Offset); in getStackAddress()
234 MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg); in getStackAddress()
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/ARM/ |
| H A D | ARMCallLowering.cpp | 104 unsigned OffsetReg = MRI.createGenericVirtualRegister(s32); in getStackAddress() local
105 MIRBuilder.buildConstant(OffsetReg, Offset); in getStackAddress()
108 MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg); in getStackAddress()
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 239 unsigned OffsetReg;
299 return Mem.OffsetReg;
468 Op->Mem.OffsetReg = offsetReg;
477 Op->Mem.OffsetReg = Sparc::G0; // always 0
489 Op->Mem.OffsetReg = 0;
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/X86/ |
| H A D | X86CallLowering.cpp | 99 auto OffsetReg = MIRBuilder.buildConstant(SType, Offset); in getStackAddress() local
101 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/X86/ |
| H A D | X86CallLowering.cpp | 99 auto OffsetReg = MIRBuilder.buildConstant(SType, Offset); in getStackAddress() local
101 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86CallLowering.cpp | 99 auto OffsetReg = MIRBuilder.buildConstant(SType, Offset); in getStackAddress() local
101 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/X86/ |
| H A D | X86CallLowering.cpp | 99 auto OffsetReg = MIRBuilder.buildConstant(SType, Offset); in getStackAddress() local
101 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/X86/ |
| H A D | X86CallLowering.cpp | 99 auto OffsetReg = MIRBuilder.buildConstant(SType, Offset); in getStackAddress() local
101 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/X86/ |
| H A D | X86CallLowering.cpp | 99 auto OffsetReg = MIRBuilder.buildConstant(SType, Offset);
101 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/ARM/ |
| H A D | Thumb2SizeReduction.cpp | 567 unsigned OffsetReg = 0; in ReduceLoadStore() local
571 OffsetReg = MI->getOperand(2).getReg(); in ReduceLoadStore()
606 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); in ReduceLoadStore()
609 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) | in ReduceLoadStore()
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/ARM/ |
| H A D | Thumb2SizeReduction.cpp | 557 unsigned OffsetReg = 0; in ReduceLoadStore() local
561 OffsetReg = MI->getOperand(2).getReg(); in ReduceLoadStore()
596 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); in ReduceLoadStore()
599 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) | in ReduceLoadStore()
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/ARM/ |
| H A D | Thumb2SizeReduction.cpp | 567 unsigned OffsetReg = 0; in ReduceLoadStore() local
571 OffsetReg = MI->getOperand(2).getReg(); in ReduceLoadStore()
606 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); in ReduceLoadStore()
609 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) | in ReduceLoadStore()
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/Target/ARM/ |
| H A D | Thumb2SizeReduction.cpp | 557 unsigned OffsetReg = 0; in ReduceLoadStore() local
561 OffsetReg = MI->getOperand(2).getReg(); in ReduceLoadStore()
596 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); in ReduceLoadStore()
599 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) | in ReduceLoadStore()
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
| H A D | Thumb2SizeReduction.cpp | 567 unsigned OffsetReg = 0; in ReduceLoadStore() local
571 OffsetReg = MI->getOperand(2).getReg(); in ReduceLoadStore()
606 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); in ReduceLoadStore()
609 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) | in ReduceLoadStore()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/ARM/ |
| H A D | Thumb2SizeReduction.cpp | 567 unsigned OffsetReg = 0; in ReduceLoadStore() local
571 OffsetReg = MI->getOperand(2).getReg(); in ReduceLoadStore()
606 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); in ReduceLoadStore()
609 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) | in ReduceLoadStore()
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
| H A D | Thumb2SizeReduction.cpp | 567 unsigned OffsetReg = 0; in ReduceLoadStore() local
571 OffsetReg = MI->getOperand(2).getReg(); in ReduceLoadStore()
606 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); in ReduceLoadStore()
609 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) | in ReduceLoadStore()
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/ARM/ |
| H A D | Thumb2SizeReduction.cpp | 567 unsigned OffsetReg = 0; in ReduceLoadStore() local
571 OffsetReg = MI->getOperand(2).getReg(); in ReduceLoadStore()
606 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); in ReduceLoadStore()
609 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) | in ReduceLoadStore()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/ARM/ |
| H A D | Thumb2SizeReduction.cpp | 567 unsigned OffsetReg = 0; in ReduceLoadStore() local
571 OffsetReg = MI->getOperand(2).getReg(); in ReduceLoadStore()
606 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); in ReduceLoadStore()
609 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) | in ReduceLoadStore()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | Thumb2SizeReduction.cpp | 557 unsigned OffsetReg = 0; in ReduceLoadStore() local
561 OffsetReg = MI->getOperand(2).getReg(); in ReduceLoadStore()
596 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); in ReduceLoadStore()
599 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) | in ReduceLoadStore()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/ARM/ |
| H A D | Thumb2SizeReduction.cpp | 567 unsigned OffsetReg = 0; in ReduceLoadStore() local
571 OffsetReg = MI->getOperand(2).getReg(); in ReduceLoadStore()
606 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); in ReduceLoadStore()
609 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) | in ReduceLoadStore()
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
| H A D | Thumb2SizeReduction.cpp | 567 unsigned OffsetReg = 0; in ReduceLoadStore() local
571 OffsetReg = MI->getOperand(2).getReg(); in ReduceLoadStore()
606 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); in ReduceLoadStore()
609 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) | in ReduceLoadStore()
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
| H A D | Thumb2SizeReduction.cpp | 567 unsigned OffsetReg = 0; in ReduceLoadStore() local
571 OffsetReg = MI->getOperand(2).getReg(); in ReduceLoadStore()
606 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); in ReduceLoadStore()
609 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) | in ReduceLoadStore()
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
| H A D | Thumb2SizeReduction.cpp | 567 unsigned OffsetReg = 0; in ReduceLoadStore() local
571 OffsetReg = MI->getOperand(2).getReg(); in ReduceLoadStore()
606 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); in ReduceLoadStore()
609 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) | in ReduceLoadStore()
|
| /dports/devel/llvm90/llvm-9.0.1.src/lib/Target/ARM/ |
| H A D | Thumb2SizeReduction.cpp | 557 unsigned OffsetReg = 0; in ReduceLoadStore() local
561 OffsetReg = MI->getOperand(2).getReg(); in ReduceLoadStore()
596 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); in ReduceLoadStore()
599 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) | in ReduceLoadStore()
|