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/dports/emulators/qemu5/qemu-5.2.0/capstone/suite/synctools/tablegen/X86/
H A DX86InstrInfo_reduce.td321 // X86 Operand Definitions.
437 def i32mem_TC : Operand<i32> {
448 def i64mem_TC : Operand<i64> {
617 def SSECC : Operand<i8> {
622 def AVXCC : Operand<i8> {
627 def AVX512ICC : Operand<i8> {
632 def XOPCC : Operand<i8> {
652 def AVX512RC : Operand<i32> {
726 def u8imm : Operand<i8> {
734 def i32u8imm : Operand<i32> {
[all …]
H A DX86InstrInfo.td321 // X86 Operand Definitions.
437 def i32mem_TC : Operand<i32> {
448 def i64mem_TC : Operand<i64> {
617 def SSECC : Operand<i8> {
622 def AVXCC : Operand<i8> {
627 def AVX512ICC : Operand<i8> {
632 def XOPCC : Operand<i8> {
652 def AVX512RC : Operand<i32> {
726 def u8imm : Operand<i8> {
734 def i32u8imm : Operand<i32> {
[all …]
/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/X86/
H A DX86InstrInfo.td310 // X86 Operand Definitions.
426 def i32mem_TC : Operand<i32> {
437 def i64mem_TC : Operand<i64> {
606 def SSECC : Operand<i8> {
611 def AVXCC : Operand<i8> {
616 def AVX512ICC : Operand<i8> {
621 def XOPCC : Operand<i8> {
641 def AVX512RC : Operand<i32> {
715 def u8imm : Operand<i8> {
723 def i32u8imm : Operand<i32> {
[all …]
/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/X86/
H A DX86InstrInfo.td321 // X86 Operand Definitions.
437 def i32mem_TC : Operand<i32> {
448 def i64mem_TC : Operand<i64> {
617 def SSECC : Operand<i8> {
622 def AVXCC : Operand<i8> {
627 def AVX512ICC : Operand<i8> {
632 def XOPCC : Operand<i8> {
652 def AVX512RC : Operand<i32> {
726 def u8imm : Operand<i8> {
734 def i32u8imm : Operand<i32> {
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
H A DPPCGenAsmMatcher.inc3348 PPCOperand &Operand = (PPCOperand&)GOp;
3361 DiagnosticPredicate DP(Operand.isImm());
3599 DiagnosticPredicate DP(Operand.isS5Imm());
3634 DiagnosticPredicate DP(Operand.isU1Imm());
3641 DiagnosticPredicate DP(Operand.isU2Imm());
3648 DiagnosticPredicate DP(Operand.isU3Imm());
3655 DiagnosticPredicate DP(Operand.isU4Imm());
3662 DiagnosticPredicate DP(Operand.isU5Imm());
3669 DiagnosticPredicate DP(Operand.isU6Imm());
3690 if (Operand.isReg()) {
[all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td181 def pcrel_imm : Operand<i32>;
182 def pcrel_imm_neg : Operand<i32> {
185 def brtarget : Operand<OtherVT>;
186 def brtarget_neg : Operand<OtherVT> {
194 def MEMii : Operand<i32> {
199 def InlineJT : Operand<i32> {
203 def InlineJT32 : Operand<i32> {
277 // Operand register - U6
614 // Operand register - U6
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td181 def pcrel_imm : Operand<i32>;
182 def pcrel_imm_neg : Operand<i32> {
185 def brtarget : Operand<OtherVT>;
186 def brtarget_neg : Operand<OtherVT> {
194 def MEMii : Operand<i32> {
199 def InlineJT : Operand<i32> {
203 def InlineJT32 : Operand<i32> {
277 // Operand register - U6
614 // Operand register - U6
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td181 def pcrel_imm : Operand<i32>;
182 def pcrel_imm_neg : Operand<i32> {
185 def brtarget : Operand<OtherVT>;
186 def brtarget_neg : Operand<OtherVT> {
194 def MEMii : Operand<i32> {
199 def InlineJT : Operand<i32> {
203 def InlineJT32 : Operand<i32> {
277 // Operand register - U6
614 // Operand register - U6
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/XCore/
H A DXCoreInstrInfo.td181 def pcrel_imm : Operand<i32>;
182 def pcrel_imm_neg : Operand<i32> {
185 def brtarget : Operand<OtherVT>;
186 def brtarget_neg : Operand<OtherVT> {
194 def MEMii : Operand<i32> {
199 def InlineJT : Operand<i32> {
203 def InlineJT32 : Operand<i32> {
277 // Operand register - U6
614 // Operand register - U6
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/XCore/
H A DXCoreInstrInfo.td181 def pcrel_imm : Operand<i32>;
182 def pcrel_imm_neg : Operand<i32> {
185 def brtarget : Operand<OtherVT>;
186 def brtarget_neg : Operand<OtherVT> {
194 def MEMii : Operand<i32> {
199 def InlineJT : Operand<i32> {
203 def InlineJT32 : Operand<i32> {
277 // Operand register - U6
614 // Operand register - U6
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td181 def pcrel_imm : Operand<i32>;
182 def pcrel_imm_neg : Operand<i32> {
185 def brtarget : Operand<OtherVT>;
186 def brtarget_neg : Operand<OtherVT> {
194 def MEMii : Operand<i32> {
199 def InlineJT : Operand<i32> {
203 def InlineJT32 : Operand<i32> {
277 // Operand register - U6
614 // Operand register - U6
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/XCore/
H A DXCoreInstrInfo.td181 def pcrel_imm : Operand<i32>;
182 def pcrel_imm_neg : Operand<i32> {
185 def brtarget : Operand<OtherVT>;
186 def brtarget_neg : Operand<OtherVT> {
194 def MEMii : Operand<i32> {
199 def InlineJT : Operand<i32> {
203 def InlineJT32 : Operand<i32> {
277 // Operand register - U6
614 // Operand register - U6
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td181 def pcrel_imm : Operand<i32>;
182 def pcrel_imm_neg : Operand<i32> {
185 def brtarget : Operand<OtherVT>;
186 def brtarget_neg : Operand<OtherVT> {
194 def MEMii : Operand<i32> {
199 def InlineJT : Operand<i32> {
203 def InlineJT32 : Operand<i32> {
277 // Operand register - U6
614 // Operand register - U6
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td181 def pcrel_imm : Operand<i32>;
182 def pcrel_imm_neg : Operand<i32> {
185 def brtarget : Operand<OtherVT>;
186 def brtarget_neg : Operand<OtherVT> {
194 def MEMii : Operand<i32> {
199 def InlineJT : Operand<i32> {
203 def InlineJT32 : Operand<i32> {
277 // Operand register - U6
614 // Operand register - U6
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td181 def pcrel_imm : Operand<i32>;
182 def pcrel_imm_neg : Operand<i32> {
185 def brtarget : Operand<OtherVT>;
186 def brtarget_neg : Operand<OtherVT> {
194 def MEMii : Operand<i32> {
199 def InlineJT : Operand<i32> {
203 def InlineJT32 : Operand<i32> {
277 // Operand register - U6
614 // Operand register - U6
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td181 def pcrel_imm : Operand<i32>;
182 def pcrel_imm_neg : Operand<i32> {
185 def brtarget : Operand<OtherVT>;
186 def brtarget_neg : Operand<OtherVT> {
194 def MEMii : Operand<i32> {
199 def InlineJT : Operand<i32> {
203 def InlineJT32 : Operand<i32> {
277 // Operand register - U6
614 // Operand register - U6
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td181 def pcrel_imm : Operand<i32>;
182 def pcrel_imm_neg : Operand<i32> {
185 def brtarget : Operand<OtherVT>;
186 def brtarget_neg : Operand<OtherVT> {
194 def MEMii : Operand<i32> {
199 def InlineJT : Operand<i32> {
203 def InlineJT32 : Operand<i32> {
277 // Operand register - U6
614 // Operand register - U6
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td181 def pcrel_imm : Operand<i32>;
182 def pcrel_imm_neg : Operand<i32> {
185 def brtarget : Operand<OtherVT>;
186 def brtarget_neg : Operand<OtherVT> {
194 def MEMii : Operand<i32> {
199 def InlineJT : Operand<i32> {
203 def InlineJT32 : Operand<i32> {
277 // Operand register - U6
614 // Operand register - U6
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td181 def pcrel_imm : Operand<i32>;
182 def pcrel_imm_neg : Operand<i32> {
185 def brtarget : Operand<OtherVT>;
186 def brtarget_neg : Operand<OtherVT> {
194 def MEMii : Operand<i32> {
199 def InlineJT : Operand<i32> {
203 def InlineJT32 : Operand<i32> {
277 // Operand register - U6
614 // Operand register - U6
/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/XCore/
H A DXCoreInstrInfo.td181 def pcrel_imm : Operand<i32>;
182 def pcrel_imm_neg : Operand<i32> {
185 def brtarget : Operand<OtherVT>;
186 def brtarget_neg : Operand<OtherVT> {
194 def MEMii : Operand<i32> {
199 def InlineJT : Operand<i32> {
203 def InlineJT32 : Operand<i32> {
277 // Operand register - U6
614 // Operand register - U6
/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/XCore/
H A DXCoreInstrInfo.td182 def pcrel_imm : Operand<i32>;
183 def pcrel_imm_neg : Operand<i32> {
186 def brtarget : Operand<OtherVT>;
187 def brtarget_neg : Operand<OtherVT> {
195 def MEMii : Operand<i32> {
200 def InlineJT : Operand<i32> {
204 def InlineJT32 : Operand<i32> {
278 // Operand register - U6
615 // Operand register - U6
/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/XCore/
H A DXCoreInstrInfo.td182 def pcrel_imm : Operand<i32>;
183 def pcrel_imm_neg : Operand<i32> {
186 def brtarget : Operand<OtherVT>;
187 def brtarget_neg : Operand<OtherVT> {
195 def MEMii : Operand<i32> {
200 def InlineJT : Operand<i32> {
204 def InlineJT32 : Operand<i32> {
278 // Operand register - U6
615 // Operand register - U6
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/tools/llvm-exegesis/lib/X86/
H A DTarget.cpp173 for (const Operand &Op : Instr.Operands) in isInvalidOpcode()
179 for (const Operand &Op : Instr.Operands) in isInvalidOpcode()
669 const Operand &Op = Instr.getPrimaryOperand(Var); in randomizeTargetMCOperand()
/dports/lang/mono/mono-5.10.1.57/mcs/class/referencesource/System.Core/Microsoft/Scripting/Compiler/
H A DLambdaCompiler.Logical.cs516 EmitExpressionAndBranch(!branch, node.Operand, label); in EmitBranchNot()
573 if (TypeUtils.AreReferenceAssignable(convert.Type, convert.Operand.Type)) { in GetEqualityOperand()
574 return convert.Operand; in GetEqualityOperand()
/dports/devel/llvm11/llvm-11.0.1.src/tools/llvm-exegesis/lib/X86/
H A DTarget.cpp173 for (const Operand &Op : Instr.Operands) in isInvalidOpcode()
179 for (const Operand &Op : Instr.Operands) in isInvalidOpcode()
669 const Operand &Op = Instr.getPrimaryOperand(Var); in randomizeTargetMCOperand()

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