| /dports/emulators/qemu/qemu-6.2.0/capstone/ |
| H A D | ChangeLog | 335 - All shifted instructions SHL, SHR, SAL, SAR, RCL, RCR, ROL & ROR now support
|
| /dports/emulators/qemu/qemu-6.2.0/capstone/suite/synctools/tablegen/X86/ |
| H A D | X86ScheduleAtom.td | 498 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
|
| /dports/emulators/qemu60/qemu-6.0.0/capstone/ |
| H A D | ChangeLog | 335 - All shifted instructions SHL, SHR, SAL, SAR, RCL, RCR, ROL & ROR now support
|
| /dports/emulators/qemu60/qemu-6.0.0/capstone/suite/synctools/tablegen/X86/back/ |
| H A D | X86ScheduleAtom.td | 498 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
|
| /dports/emulators/qemu60/qemu-6.0.0/capstone/suite/synctools/tablegen/X86/ |
| H A D | X86ScheduleAtom.td | 498 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/X86/ |
| H A D | X86ScheduleAtom.td | 506 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/X86/ |
| H A D | X86ScheduleAtom.td | 507 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/X86/ |
| H A D | X86ScheduleAtom.td | 507 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| H A D | X86ScheduleAtom.td | 504 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ScheduleAtom.td | 506 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/X86/ |
| H A D | X86ScheduleAtom.td | 513 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/X86/ |
| H A D | X86ScheduleAtom.td | 506 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
|
| /dports/emulators/dolphin-emu/dolphin-3152428/Source/UnitTests/Common/ |
| H A D | x64EmitterTest.cpp | 449 SHIFT_TEST(RCL)
|
| /dports/emulators/qemu5/qemu-5.2.0/capstone/suite/synctools/tablegen/X86/ |
| H A D | X86ScheduleAtom.td | 498 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
|
| /dports/emulators/qemu5/qemu-5.2.0/capstone/suite/synctools/tablegen/X86/back/ |
| H A D | X86ScheduleAtom.td | 498 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
|
| /dports/emulators/qemu5/qemu-5.2.0/capstone/ |
| H A D | ChangeLog | 335 - All shifted instructions SHL, SHR, SAL, SAR, RCL, RCR, ROL & ROR now support
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/X86/ |
| H A D | X86ScheduleAtom.td | 507 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
|
| /dports/devel/redasm/REDasm-2.1.1/LibREDasm/depends/capstone/ |
| H A D | ChangeLog | 349 - All shifted instructions SHL, SHR, SAL, SAR, RCL, RCR, ROL & ROR now support
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ScheduleAtom.td | 504 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/X86/ |
| H A D | X86ScheduleAtom.td | 507 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
|
| /dports/devel/llvm90/llvm-9.0.1.src/lib/Target/X86/ |
| H A D | X86ScheduleAtom.td | 502 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
|
| /dports/devel/llvm80/llvm-8.0.1.src/lib/Target/X86/ |
| H A D | X86ScheduleAtom.td | 502 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/X86/ |
| H A D | X86ScheduleAtom.td | 498 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/X86/ |
| H A D | X86ScheduleAtom.td | 506 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
|
| /dports/lang/luajit/LuaJIT-2.0.5/src/ |
| H A D | vm_x86.dasc | 57 |.define RCL, al
61 |.define RDL, RCL
280 |.macro ins_ABC; movzx RB, RCH; movzx RC, RCL; .endmacro
282 |.macro ins_A_C; movzx RC, RCL; .endmacro
289 | movzx OP, RCL
1266 | movzx OP, RCL
3049 | movzx OP, RCL
|