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Searched refs:RTC_CONTROL (Results 26 – 50 of 271) sorted by relevance

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/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/mips/mti-malta/
H A Dmalta-time.c98 ctrl = CMOS_READ(RTC_CONTROL); in estimate_frequencies()
189 ctrl = CMOS_READ(RTC_CONTROL); in init_rtc()
191 CMOS_WRITE(ctrl & ~RTC_SET, RTC_CONTROL); in init_rtc()
/dports/multimedia/libv4l/linux-5.13-rc2/arch/mips/mti-malta/
H A Dmalta-time.c98 ctrl = CMOS_READ(RTC_CONTROL); in estimate_frequencies()
189 ctrl = CMOS_READ(RTC_CONTROL); in init_rtc()
191 CMOS_WRITE(ctrl & ~RTC_SET, RTC_CONTROL); in init_rtc()
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gcc/libgloss/mips/
H A Dcma101.c54 #define RTC_CONTROL BYTEREG(RTCLOCK_BASE,0x3FC0) macro
276 *RTC_CONTROL |= RTC_CTL_LOCK_READ;
287 *RTC_CONTROL &= ~(RTC_CTL_LOCK_READ | RTC_CTL_LOCK_WRITE);
/dports/devel/arm-none-eabi-newlib/newlib-2.4.0/libgloss/mips/
H A Dcma101.c54 #define RTC_CONTROL BYTEREG(RTCLOCK_BASE,0x3FC0) macro
276 *RTC_CONTROL |= RTC_CTL_LOCK_READ;
287 *RTC_CONTROL &= ~(RTC_CTL_LOCK_READ | RTC_CTL_LOCK_WRITE);
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gcc/libgloss/mips/
H A Dcma101.c54 #define RTC_CONTROL BYTEREG(RTCLOCK_BASE,0x3FC0) macro
276 *RTC_CONTROL |= RTC_CTL_LOCK_READ;
287 *RTC_CONTROL &= ~(RTC_CTL_LOCK_READ | RTC_CTL_LOCK_WRITE);
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/rtc/
H A Dds164x.c40 #define RTC_CONTROL ( RTC_BASE + 0x00 ) macro
42 #define RTC_CONTROLA RTC_CONTROL /* W=bit6, R=bit5 */
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/drivers/rtc/
H A Dds164x.c59 #define RTC_CONTROL ( RTC_BASE + 0x00 ) macro
61 #define RTC_CONTROLA RTC_CONTROL /* W=bit6, R=bit5 */
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/drivers/rtc/
H A Dds164x.c59 #define RTC_CONTROL ( RTC_BASE + 0x00 ) macro
61 #define RTC_CONTROLA RTC_CONTROL /* W=bit6, R=bit5 */
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/rtc/
H A Dds164x.c40 #define RTC_CONTROL ( RTC_BASE + 0x00 ) macro
42 #define RTC_CONTROLA RTC_CONTROL /* W=bit6, R=bit5 */
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/rtc/
H A Dds164x.c40 #define RTC_CONTROL ( RTC_BASE + 0x00 ) macro
42 #define RTC_CONTROLA RTC_CONTROL /* W=bit6, R=bit5 */
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/rtc/
H A Dds164x.c40 #define RTC_CONTROL ( RTC_BASE + 0x00 ) macro
42 #define RTC_CONTROLA RTC_CONTROL /* W=bit6, R=bit5 */
/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/rtc/
H A Dds164x.c40 #define RTC_CONTROL ( RTC_BASE + 0x00 ) macro
42 #define RTC_CONTROLA RTC_CONTROL /* W=bit6, R=bit5 */
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/drivers/rtc/
H A Dds164x.c59 #define RTC_CONTROL ( RTC_BASE + 0x00 ) macro
61 #define RTC_CONTROLA RTC_CONTROL /* W=bit6, R=bit5 */
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/drivers/rtc/
H A Dds164x.c59 #define RTC_CONTROL ( RTC_BASE + 0x00 ) macro
61 #define RTC_CONTROLA RTC_CONTROL /* W=bit6, R=bit5 */
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/rtc/
H A Dds164x.c40 #define RTC_CONTROL ( RTC_BASE + 0x00 ) macro
42 #define RTC_CONTROLA RTC_CONTROL /* W=bit6, R=bit5 */
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/rtc/
H A Dds164x.c40 #define RTC_CONTROL ( RTC_BASE + 0x00 ) macro
42 #define RTC_CONTROLA RTC_CONTROL /* W=bit6, R=bit5 */
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/rtc/
H A Dds164x.c40 #define RTC_CONTROL ( RTC_BASE + 0x00 ) macro
42 #define RTC_CONTROLA RTC_CONTROL /* W=bit6, R=bit5 */
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/rtc/
H A Dds164x.c40 #define RTC_CONTROL ( RTC_BASE + 0x00 ) macro
42 #define RTC_CONTROLA RTC_CONTROL /* W=bit6, R=bit5 */
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/rtc/
H A Dds164x.c40 #define RTC_CONTROL ( RTC_BASE + 0x00 ) macro
42 #define RTC_CONTROLA RTC_CONTROL /* W=bit6, R=bit5 */
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/rtc/
H A Dds164x.c40 #define RTC_CONTROL ( RTC_BASE + 0x00 ) macro
42 #define RTC_CONTROLA RTC_CONTROL /* W=bit6, R=bit5 */
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/rtc/
H A Dds164x.c40 #define RTC_CONTROL ( RTC_BASE + 0x00 ) macro
42 #define RTC_CONTROLA RTC_CONTROL /* W=bit6, R=bit5 */
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/rtc/
H A Dds164x.c40 #define RTC_CONTROL ( RTC_BASE + 0x00 ) macro
42 #define RTC_CONTROLA RTC_CONTROL /* W=bit6, R=bit5 */
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/rtc/
H A Dds164x.c40 #define RTC_CONTROL ( RTC_BASE + 0x00 ) macro
42 #define RTC_CONTROLA RTC_CONTROL /* W=bit6, R=bit5 */
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/rtc/
H A Dds164x.c40 #define RTC_CONTROL ( RTC_BASE + 0x00 ) macro
42 #define RTC_CONTROLA RTC_CONTROL /* W=bit6, R=bit5 */
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/drivers/rtc/
H A Dds164x.c59 #define RTC_CONTROL ( RTC_BASE + 0x00 ) macro
61 #define RTC_CONTROLA RTC_CONTROL /* W=bit6, R=bit5 */

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