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Searched refs:SPR (Results 101 – 125 of 1979) sorted by relevance

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/dports/biology/biosig/biosig-2.3.3/biosig4matlab/t200_FileAccess/
H A Dsopen.m642 HDR.SPR = lcm(HDR.SPR,HDR.AS.SPR(k));
1285 HDR.AS.SPR(isnan(HDR.AS.SPR)) = HDR.SPR;
1290 HDR.SPR = lcm(HDR.SPR,HDR.AS.SPR(k));
3174 else HDR.SPR = lcm(HDR.SPR, HDR.AS.SPR(1));
5786 HDR.AS.SPR = HDR.AS.SPR*d;
5790 HDR.SPR = HDR.AS.SPR(1);
5792 HDR.SPR = lcm(HDR.SPR,HDR.AS.SPR(k));
6140 HDR.SPR = lcm(HDR.SPR, HDR.AS.SPR);
8117 HDR.AS.SPR = HDR.NEX.SPR(CH);
8121 HDR.SPR = lcm(HDR.SPR,HDR.AS.SPR(k));
[all …]
/dports/biology/iqtree/IQ-TREE-2.0.6/pll/
H A DsearchAlgo.c2174 rearr.SPR.removeNode = p; in pllTestInsertBIG()
2175 rearr.SPR.insertNode = q; in pllTestInsertBIG()
2628 p = rearr->SPR.removeNode; in pllCreateSprInfoRollback()
2647 sprRb->SPR.r = q->back; in pllCreateSprInfoRollback()
2648 sprRb->SPR.q = q; in pllCreateSprInfoRollback()
2649 sprRb->SPR.p = p; in pllCreateSprInfoRollback()
2742 hookup (ri->SPR.p->next, ri->SPR.pn, ri->SPR.zpn, numBranches); in pllRollbackSPR()
2743 hookup (ri->SPR.p->next->next, ri->SPR.pnn, ri->SPR.zpnn, numBranches); in pllRollbackSPR()
2744 hookup (ri->SPR.p, ri->SPR.p->back, ri->SPR.zp, numBranches); in pllRollbackSPR()
2745 hookup (ri->SPR.q, ri->SPR.r, ri->SPR.zqr, numBranches); in pllRollbackSPR()
[all …]
/dports/devel/gdb/gdb-11.1/gdb/testsuite/gdb.ada/bias/
H A Dbias.adb38 SPR : Some_Packed_Record := (R => -4, S => -5); variable
50 Do_Nothing (SPR'Address);
/dports/science/aircraft-datcom/aircraft-datcom-ed877bb/src/
H A Dinitz2.f6 COMMON /POWR/ SPR(59),FLA(45),FLP(189),TRM(22) local
16 EQUIVALENCE (PWW(1),SPR(1)), (DW(1),FHG(1))
/dports/cad/opencascade/opencascade-7.6.0/src/ShapeProcessAPI/
H A DShapeProcessAPI_ApplySequence.cxx151 Standard_Real SPR = 1, FPR = 1; in PrintPreparationResult() local
154 if (NbS > 0) SPR = 1. * (NbS - SN) / NbS; in PrintPreparationResult()
159 PMSG205.Arg ((Standard_Integer) (100 * SPR)); in PrintPreparationResult()
/dports/lang/gnatdroid-binutils-x86/binutils-2.27/cpu/
H A Dor1kcommon.cpu98 (or (sll UWI (enum UWI (.sym "SPR-GROUP-" spr-group)) spr-shift)
99 (enum UWI (.sym "SPR-INDEX-" spr-group "-" spr-index))))
140 SPR-GROUP-
194 SPR-INDEX-
274 "SPR field msb positions"
276 SPR-FIELD-MSB-
290 "SPR field lsb positions"
292 SPR-FIELD-SIZE-
306 "SPR field masks"
308 SPR-FIELD-MASK-
/dports/lang/gnatdroid-binutils/binutils-2.27/cpu/
H A Dor1kcommon.cpu98 (or (sll UWI (enum UWI (.sym "SPR-GROUP-" spr-group)) spr-shift)
99 (enum UWI (.sym "SPR-INDEX-" spr-group "-" spr-index))))
140 SPR-GROUP-
194 SPR-INDEX-
274 "SPR field msb positions"
276 SPR-FIELD-MSB-
290 "SPR field lsb positions"
292 SPR-FIELD-SIZE-
306 "SPR field masks"
308 SPR-FIELD-MASK-
/dports/net/openmpi3/openmpi-3.1.6/opal/mca/patcher/base/
H A Dpatcher_base_patch.c50 static unsigned int mtspr(unsigned int SPR, unsigned int RS) { in mtspr() argument
51 return (31<<26) + (RS<<21) + ((SPR&0x1f)<<16) + ((SPR>>5)<<11) + (467<<1); in mtspr()
/dports/net/openmpi/openmpi-4.1.1/opal/mca/patcher/base/
H A Dpatcher_base_patch.c50 static unsigned int mtspr(unsigned int SPR, unsigned int RS) { in mtspr() argument
51 return (31<<26) + (RS<<21) + ((SPR&0x1f)<<16) + ((SPR>>5)<<11) + (467<<1); in mtspr()
/dports/science/healpix/Healpix_3.50/src/idl/misc/
H A Dpix2xy.pro96 ; SPR 9741 Change PRINT statements to MESSAGE statements in
99 ; SPR 9749 Fix output array allocation statement for single face
102 ; SPR 9833 Allows user to designate sixpacked output using command
110 ; SPR 10059 Too large pixel number (for given resolution)
114 ; SPR 10212 Call RASTER to generate rasterized image.
118 ; SPR 10212 Change call from 'RASTER' to 'RASTR'
121 ; SPR 10729 REFORM pixel list if column vector
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td47 // SPR - One of the 32-bit special-purpose registers
48 class SPR<bits<10> num, string n> : PPCReg<n> {
218 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
220 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>;
223 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
224 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
227 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
233 def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>;
235 def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
238 // (which really is SPR register 1); this is the only bit interesting to a
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td47 // SPR - One of the 32-bit special-purpose registers
48 class SPR<bits<10> num, string n> : PPCReg<n> {
218 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
220 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>;
223 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
224 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
227 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
233 def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>;
235 def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
238 // (which really is SPR register 1); this is the only bit interesting to a
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/PowerPC/
H A DPPCRegisterInfo.td47 // SPR - One of the 32-bit special-purpose registers
48 class SPR<bits<10> num, string n> : PPCReg<n> {
218 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
220 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>;
223 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
224 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
227 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
233 def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>;
235 def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
238 // (which really is SPR register 1); this is the only bit interesting to a
[all …]
/dports/emulators/qemu/qemu-6.2.0/capstone/suite/synctools/tablegen/PPC/
H A DPPCRegisterInfo.td48 // SPR - One of the 32-bit special-purpose registers
49 class SPR<bits<10> num, string n> : PPCReg<n> {
213 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
215 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>;
218 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
219 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
222 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
228 def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>;
230 def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
233 // (which really is SPR register 1); this is the only bit interesting to a
[all …]
/dports/emulators/qemu60/qemu-6.0.0/capstone/suite/synctools/tablegen/PPC/
H A DPPCRegisterInfo.td48 // SPR - One of the 32-bit special-purpose registers
49 class SPR<bits<10> num, string n> : PPCReg<n> {
213 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
215 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>;
218 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
219 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
222 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
228 def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>;
230 def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
233 // (which really is SPR register 1); this is the only bit interesting to a
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/PowerPC/
H A DPPCRegisterInfo.td47 // SPR - One of the 32-bit special-purpose registers
48 class SPR<bits<10> num, string n> : PPCReg<n> {
218 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
220 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>;
223 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
224 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
227 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
233 def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>;
235 def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
238 // (which really is SPR register 1); this is the only bit interesting to a
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td47 // SPR - One of the 32-bit special-purpose registers
48 class SPR<bits<10> num, string n> : PPCReg<n> {
218 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
220 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>;
223 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
224 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
227 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
233 def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>;
235 def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
238 // (which really is SPR register 1); this is the only bit interesting to a
[all …]
/dports/emulators/qemu5/qemu-5.2.0/capstone/suite/synctools/tablegen/PPC/
H A DPPCRegisterInfo.td48 // SPR - One of the 32-bit special-purpose registers
49 class SPR<bits<10> num, string n> : PPCReg<n> {
213 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
215 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>;
218 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
219 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
222 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
228 def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>;
230 def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
233 // (which really is SPR register 1); this is the only bit interesting to a
[all …]
/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/PowerPC/
H A DPPCRegisterInfo.td47 // SPR - One of the 32-bit special-purpose registers
48 class SPR<bits<10> num, string n> : PPCReg<n> {
218 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
220 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>;
223 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
224 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
227 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
233 def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>;
235 def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
238 // (which really is SPR register 1); this is the only bit interesting to a
[all …]
/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/PowerPC/
H A DPPCRegisterInfo.td48 // SPR - One of the 32-bit special-purpose registers
49 class SPR<bits<10> num, string n> : PPCReg<n> {
219 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
221 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>;
224 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
225 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
228 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
234 def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>;
236 def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
239 // (which really is SPR register 1); this is the only bit interesting to a
[all …]
/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/PowerPC/
H A DPPCRegisterInfo.td48 // SPR - One of the 32-bit special-purpose registers
49 class SPR<bits<10> num, string n> : PPCReg<n> {
213 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
215 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>;
218 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
219 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
222 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
228 def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>;
230 def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
233 // (which really is SPR register 1); this is the only bit interesting to a
[all …]
/dports/devel/binutils/binutils-2.37/cpu/
H A Dor1kcommon.cpu88 (or (sll UWI (enum UWI (.sym "SPR-GROUP-" spr-group)) spr-shift)
89 (enum UWI (.sym "SPR-INDEX-" spr-group "-" spr-index))))
206 SPR-GROUP-
260 SPR-INDEX-
340 "SPR field msb positions"
342 SPR-FIELD-MSB-
356 "SPR field lsb positions"
358 SPR-FIELD-SIZE-
372 "SPR field masks"
374 SPR-FIELD-MASK-
/dports/devel/arm-elf-binutils/binutils-2.37/cpu/
H A Dor1kcommon.cpu88 (or (sll UWI (enum UWI (.sym "SPR-GROUP-" spr-group)) spr-shift)
89 (enum UWI (.sym "SPR-INDEX-" spr-group "-" spr-index))))
206 SPR-GROUP-
260 SPR-INDEX-
340 "SPR field msb positions"
342 SPR-FIELD-MSB-
356 "SPR field lsb positions"
358 SPR-FIELD-SIZE-
372 "SPR field masks"
374 SPR-FIELD-MASK-
/dports/devel/gnulibiberty/binutils-2.37/cpu/
H A Dor1kcommon.cpu88 (or (sll UWI (enum UWI (.sym "SPR-GROUP-" spr-group)) spr-shift)
89 (enum UWI (.sym "SPR-INDEX-" spr-group "-" spr-index))))
206 SPR-GROUP-
260 SPR-INDEX-
340 "SPR field msb positions"
342 SPR-FIELD-MSB-
356 "SPR field lsb positions"
358 SPR-FIELD-SIZE-
372 "SPR field masks"
374 SPR-FIELD-MASK-
/dports/devel/gdb/gdb-11.1/cpu/
H A Dor1kcommon.cpu88 (or (sll UWI (enum UWI (.sym "SPR-GROUP-" spr-group)) spr-shift)
89 (enum UWI (.sym "SPR-INDEX-" spr-group "-" spr-index))))
206 SPR-GROUP-
260 SPR-INDEX-
340 "SPR field msb positions"
342 SPR-FIELD-MSB-
356 "SPR field lsb positions"
358 SPR-FIELD-SIZE-
372 "SPR field masks"
374 SPR-FIELD-MASK-

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