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/dports/biology/biosig/biosig-2.3.3/biosig4matlab/t200_FileAccess/
H A Dcntopen.m449 CNT.SPR = h.pnts;
454 CNT.Dur = CNT.SPR/CNT.SampleRate;
460 CNT.SPR = h.pnts;
465 CNT.SPR = h.pnts;
474 CNT.SPR = h.pnts;
476 CNT.AS.spb = CNT.NS*CNT.SPR; % Samples per Block
515 CNT.Dur = CNT.SPR/CNT.SampleRate;
519 CNT.SPR = h.numsamples;
520 %CNT.SPR = h.pnts;
545 CNT.SPR = floor((CNT.FILE.size-CNT.HeadLen)/CNT.AS.bpb);
[all …]
H A Dopenxml.m92 HDR.SPR = 1;
95 HDR.AS.SPR(k) = str2double(CH.LeadSampleCountTotal);
96 HDR.SPR = lcm(HDR.SPR,HDR.AS.SPR(k));
218 HDR.SPR = size(HDR.data,1);
/dports/biology/biosig/biosig-2.3.3/biosig4matlab/t250_ArtifactPreProcessingQualityControl/
H A Deeg2hist.m126 NoBlks=ceil(60*HDR.SampleRate/HDR.SPR);
128 if isfield(HDR.AS,'SPR')
129 bi=[0;cumsum(HDR.AS.SPR)];
132 HDR.AS.spb = HDR.SPR;
151 …for k=reshape(S(bi(CHAN(l))+1:bi(CHAN(l)+1),:),1,HDR.SPR(l)*NoBlks)+2^15+1, h(k,l) = h(k,l)+1; end…
/dports/science/aircraft-datcom/aircraft-datcom-ed877bb/src/
H A Dptcp.f7 COMMON /POWR/ SPR(59) local
10 EQUIVALENCE(TANLLE,A(62)),(TANLTE,A(80)),(BETA,SPR(1)),
11 1 (TANLHL,SPR(14))
/dports/biology/biosig/biosig-2.3.3/biosig4c++/src/
H A Dttl2trig.c320 hdr->SPR = 1; in main()
329 hc->SPR = hdr->SPR; in main()
/dports/emulators/qemu-utils/qemu-4.2.1/target/ppc/
H A Dtrace-events4 kvm_failed_spr_set(int spr, const char *msg) "Warning: Unable to set SPR %d to KVM: %s"
5 kvm_failed_spr_get(int spr, const char *msg) "Warning: Unable to retrieve SPR %d from KVM: %s"
/dports/emulators/qemu5/qemu-5.2.0/target/ppc/
H A Dtrace-events4 kvm_failed_spr_set(int spr, const char *msg) "Warning: Unable to set SPR %d to KVM: %s"
5 kvm_failed_spr_get(int spr, const char *msg) "Warning: Unable to retrieve SPR %d from KVM: %s"
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/ppc/
H A Dtrace-events4 kvm_failed_spr_set(int spr, const char *msg) "Warning: Unable to set SPR %d to KVM: %s"
5 kvm_failed_spr_get(int spr, const char *msg) "Warning: Unable to retrieve SPR %d from KVM: %s"
/dports/emulators/qemu42/qemu-4.2.1/target/ppc/
H A Dtrace-events4 kvm_failed_spr_set(int spr, const char *msg) "Warning: Unable to set SPR %d to KVM: %s"
5 kvm_failed_spr_get(int spr, const char *msg) "Warning: Unable to retrieve SPR %d from KVM: %s"
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/ppc/
H A Dtrace-events4 kvm_failed_spr_set(int spr, const char *msg) "Warning: Unable to set SPR %d to KVM: %s"
5 kvm_failed_spr_get(int spr, const char *msg) "Warning: Unable to retrieve SPR %d from KVM: %s"
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/ppc/
H A Dtrace-events4 kvm_failed_spr_set(int spr, const char *msg) "Warning: Unable to set SPR %d to KVM: %s"
5 kvm_failed_spr_get(int spr, const char *msg) "Warning: Unable to retrieve SPR %d from KVM: %s"
/dports/emulators/qemu60/qemu-6.0.0/target/ppc/
H A Dtrace-events4 kvm_failed_spr_set(int spr, const char *msg) "Warning: Unable to set SPR %d to KVM: %s"
5 kvm_failed_spr_get(int spr, const char *msg) "Warning: Unable to retrieve SPR %d from KVM: %s"
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td398 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> {
399 let AltOrders = [(add (decimate SPR, 2), SPR),
400 (add (decimate SPR, 4),
401 (decimate SPR, 2),
402 (decimate (rotl SPR, 1), 4),
403 (decimate (rotl SPR, 1), 2))];
411 let AltOrders = [(add (decimate HPR, 2), SPR),
422 // Subset of SPR which can be used as a source of NEON scalars for 16-bit
447 def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> {
452 // 32-bit SPR subregs).
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/ARM/
H A DARMRegisterInfo.td398 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> {
399 let AltOrders = [(add (decimate SPR, 2), SPR),
400 (add (decimate SPR, 4),
401 (decimate SPR, 2),
402 (decimate (rotl SPR, 1), 4),
403 (decimate (rotl SPR, 1), 2))];
411 let AltOrders = [(add (decimate HPR, 2), SPR),
422 // Subset of SPR which can be used as a source of NEON scalars for 16-bit
447 def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> {
452 // 32-bit SPR subregs).
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td398 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> {
399 let AltOrders = [(add (decimate SPR, 2), SPR),
400 (add (decimate SPR, 4),
401 (decimate SPR, 2),
402 (decimate (rotl SPR, 1), 4),
403 (decimate (rotl SPR, 1), 2))];
411 let AltOrders = [(add (decimate HPR, 2), SPR),
422 // Subset of SPR which can be used as a source of NEON scalars for 16-bit
447 def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> {
452 // 32-bit SPR subregs).
[all …]
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td398 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> {
399 let AltOrders = [(add (decimate SPR, 2), SPR),
400 (add (decimate SPR, 4),
401 (decimate SPR, 2),
402 (decimate (rotl SPR, 1), 4),
403 (decimate (rotl SPR, 1), 2))];
411 let AltOrders = [(add (decimate HPR, 2), SPR),
422 // Subset of SPR which can be used as a source of NEON scalars for 16-bit
447 def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> {
452 // 32-bit SPR subregs).
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td400 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> {
401 let AltOrders = [(add (decimate SPR, 2), SPR),
402 (add (decimate SPR, 4),
403 (decimate SPR, 2),
404 (decimate (rotl SPR, 1), 4),
405 (decimate (rotl SPR, 1), 2))];
413 let AltOrders = [(add (decimate HPR, 2), SPR),
424 // Subset of SPR which can be used as a source of NEON scalars for 16-bit
449 def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> {
454 // 32-bit SPR subregs).
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td398 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> {
399 let AltOrders = [(add (decimate SPR, 2), SPR),
400 (add (decimate SPR, 4),
401 (decimate SPR, 2),
402 (decimate (rotl SPR, 1), 4),
403 (decimate (rotl SPR, 1), 2))];
411 let AltOrders = [(add (decimate HPR, 2), SPR),
422 // Subset of SPR which can be used as a source of NEON scalars for 16-bit
447 def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> {
452 // 32-bit SPR subregs).
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td398 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> {
399 let AltOrders = [(add (decimate SPR, 2), SPR),
400 (add (decimate SPR, 4),
401 (decimate SPR, 2),
402 (decimate (rotl SPR, 1), 4),
403 (decimate (rotl SPR, 1), 2))];
411 let AltOrders = [(add (decimate HPR, 2), SPR),
422 // Subset of SPR which can be used as a source of NEON scalars for 16-bit
447 def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> {
452 // 32-bit SPR subregs).
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td398 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> {
399 let AltOrders = [(add (decimate SPR, 2), SPR),
400 (add (decimate SPR, 4),
401 (decimate SPR, 2),
402 (decimate (rotl SPR, 1), 4),
403 (decimate (rotl SPR, 1), 2))];
411 let AltOrders = [(add (decimate HPR, 2), SPR),
422 // Subset of SPR which can be used as a source of NEON scalars for 16-bit
447 def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> {
452 // 32-bit SPR subregs).
[all …]
/dports/lang/gcc12-devel/gcc-12-20211205/gcc/testsuite/gnat.dg/
H A Dbias1.adb26 SPR : SomePackedRecord := (R => -4, S => -5); variable
/dports/lang/gcc10/gcc-10.3.0/gcc/testsuite/gnat.dg/
H A Dbias1.adb26 SPR : SomePackedRecord := (R => -4, S => -5); variable
/dports/lang/gcc11-devel/gcc-11-20211009/gcc/testsuite/gnat.dg/
H A Dbias1.adb26 SPR : SomePackedRecord := (R => -4, S => -5); variable
/dports/devel/avr-gcc/gcc-10.2.0/gcc/testsuite/gnat.dg/
H A Dbias1.adb26 SPR : SomePackedRecord := (R => -4, S => -5); variable
/dports/lang/gcc11/gcc-11.2.0/gcc/testsuite/gnat.dg/
H A Dbias1.adb26 SPR : SomePackedRecord := (R => -4, S => -5); variable

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