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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AArch64/
H A DAArch64SIMDInstrOpt.cpp441 Register SrcReg2 = MI.getOperand(3).getReg(); in optimizeVectElement() local
447 if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg2, LaneNumber, &DupDest)) { in optimizeVectElement()
450 .addReg(SrcReg2, Src2IsKill) in optimizeVectElement()
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AArch64/
H A DAArch64SIMDInstrOpt.cpp439 Register SrcReg2 = MI.getOperand(3).getReg(); in optimizeVectElement() local
445 if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg2, LaneNumber, &DupDest)) { in optimizeVectElement()
448 .addReg(SrcReg2, Src2IsKill) in optimizeVectElement()
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AArch64/
H A DAArch64SIMDInstrOpt.cpp438 Register SrcReg2 = MI.getOperand(3).getReg(); in optimizeVectElement() local
444 if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg2, LaneNumber, &DupDest)) { in optimizeVectElement()
447 .addReg(SrcReg2, Src2IsKill) in optimizeVectElement()
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64SIMDInstrOpt.cpp441 Register SrcReg2 = MI.getOperand(3).getReg(); in optimizeVectElement() local
447 if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg2, LaneNumber, &DupDest)) { in optimizeVectElement()
450 .addReg(SrcReg2, Src2IsKill) in optimizeVectElement()
H A DAArch64InstrInfo.h230 Register &SrcReg2, int &CmpMask,
235 Register SrcReg2, int CmpMask, int CmpValue,
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AArch64/
H A DAArch64SIMDInstrOpt.cpp441 Register SrcReg2 = MI.getOperand(3).getReg(); in optimizeVectElement() local
447 if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg2, LaneNumber, &DupDest)) { in optimizeVectElement()
450 .addReg(SrcReg2, Src2IsKill) in optimizeVectElement()
H A DAArch64InstrInfo.h230 Register &SrcReg2, int &CmpMask,
235 Register SrcReg2, int CmpMask, int CmpValue,
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64SIMDInstrOpt.cpp441 Register SrcReg2 = MI.getOperand(3).getReg(); in optimizeVectElement() local
447 if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg2, LaneNumber, &DupDest)) { in optimizeVectElement()
450 .addReg(SrcReg2, Src2IsKill) in optimizeVectElement()
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AArch64/
H A DAArch64SIMDInstrOpt.cpp439 Register SrcReg2 = MI.getOperand(3).getReg(); in optimizeVectElement() local
445 if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg2, LaneNumber, &DupDest)) { in optimizeVectElement()
448 .addReg(SrcReg2, Src2IsKill) in optimizeVectElement()
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SIMDInstrOpt.cpp441 Register SrcReg2 = MI.getOperand(3).getReg(); in optimizeVectElement() local
447 if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg2, LaneNumber, &DupDest)) { in optimizeVectElement()
450 .addReg(SrcReg2, Src2IsKill) in optimizeVectElement()
H A DAArch64InstrInfo.h230 Register &SrcReg2, int &CmpMask,
235 Register SrcReg2, int CmpMask, int CmpValue,
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64SIMDInstrOpt.cpp438 Register SrcReg2 = MI.getOperand(3).getReg(); in optimizeVectElement() local
444 if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg2, LaneNumber, &DupDest)) { in optimizeVectElement()
447 .addReg(SrcReg2, Src2IsKill) in optimizeVectElement()
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AArch64/
H A DAArch64SIMDInstrOpt.cpp441 Register SrcReg2 = MI.getOperand(3).getReg(); in optimizeVectElement() local
447 if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg2, LaneNumber, &DupDest)) { in optimizeVectElement()
450 .addReg(SrcReg2, Src2IsKill) in optimizeVectElement()
H A DAArch64InstrInfo.h230 Register &SrcReg2, int64_t &CmpMask,
235 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64SIMDInstrOpt.cpp441 Register SrcReg2 = MI.getOperand(3).getReg(); in optimizeVectElement() local
447 if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg2, LaneNumber, &DupDest)) { in optimizeVectElement()
450 .addReg(SrcReg2, Src2IsKill) in optimizeVectElement()
H A DAArch64InstrInfo.h230 Register &SrcReg2, int &CmpMask,
235 Register SrcReg2, int CmpMask, int CmpValue,
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SIMDInstrOpt.cpp438 Register SrcReg2 = MI.getOperand(3).getReg(); in optimizeVectElement() local
444 if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg2, LaneNumber, &DupDest)) { in optimizeVectElement()
447 .addReg(SrcReg2, Src2IsKill) in optimizeVectElement()
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64SIMDInstrOpt.cpp441 Register SrcReg2 = MI.getOperand(3).getReg(); in optimizeVectElement() local
447 if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg2, LaneNumber, &DupDest)) { in optimizeVectElement()
450 .addReg(SrcReg2, Src2IsKill) in optimizeVectElement()
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64SIMDInstrOpt.cpp441 Register SrcReg2 = MI.getOperand(3).getReg(); in optimizeVectElement() local
447 if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg2, LaneNumber, &DupDest)) { in optimizeVectElement()
450 .addReg(SrcReg2, Src2IsKill) in optimizeVectElement()
/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AArch64/
H A DAArch64SIMDInstrOpt.cpp438 unsigned SrcReg2 = MI.getOperand(3).getReg(); in optimizeVectElement() local
444 if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg2, LaneNumber, &DupDest)) { in optimizeVectElement()
447 .addReg(SrcReg2, Src2IsKill) in optimizeVectElement()
/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/AArch64/
H A DAArch64SIMDInstrOpt.cpp439 unsigned SrcReg2 = MI.getOperand(3).getReg(); in optimizeVectElement() local
445 if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg2, LaneNumber, &DupDest)) { in optimizeVectElement()
448 .addReg(SrcReg2, Src2IsKill) in optimizeVectElement()
/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/AArch64/
H A DAArch64SIMDInstrOpt.cpp439 unsigned SrcReg2 = MI.getOperand(3).getReg(); in optimizeVectElement() local
445 if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg2, LaneNumber, &DupDest)) { in optimizeVectElement()
448 .addReg(SrcReg2, Src2IsKill) in optimizeVectElement()
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.h473 unsigned &SrcReg2, int &CmpMask,
480 unsigned SrcReg2, int CmpMask, int CmpValue,
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/X86/
H A DX86InstrInfo.h473 unsigned &SrcReg2, int &CmpMask,
480 unsigned SrcReg2, int CmpMask, int CmpValue,
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A DX86InstrInfo.h473 unsigned &SrcReg2, int &CmpMask,
480 unsigned SrcReg2, int CmpMask, int CmpValue,

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