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Searched refs:VF4 (Results 51 – 75 of 114) sorted by relevance

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/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp98 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
146 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
165 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVSDPatterns.td413 defm : VPatExtendSDNode_V<[zext, anyext], "PseudoVZEXT", "VF4",
415 defm : VPatExtendSDNode_V<[sext], "PseudoVSEXT", "VF4",
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/RISCV/
H A DRISCVInstrInfoVSDPatterns.td413 defm : VPatExtendSDNode_V<[zext, anyext], "PseudoVZEXT", "VF4",
415 defm : VPatExtendSDNode_V<[sext], "PseudoVSEXT", "VF4",
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVSDPatterns.td413 defm : VPatExtendSDNode_V<[zext, anyext], "PseudoVZEXT", "VF4",
415 defm : VPatExtendSDNode_V<[sext], "PseudoVSEXT", "VF4",
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVSDPatterns.td407 defm : VPatExtendSDNode_V<[zext, anyext], "PseudoVZEXT", "VF4",
409 defm : VPatExtendSDNode_V<[sext], "PseudoVSEXT", "VF4",
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVSDPatterns.td413 defm : VPatExtendSDNode_V<[zext, anyext], "PseudoVZEXT", "VF4",
415 defm : VPatExtendSDNode_V<[sext], "PseudoVSEXT", "VF4",
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVSDPatterns.td413 defm : VPatExtendSDNode_V<[zext, anyext], "PseudoVZEXT", "VF4",
415 defm : VPatExtendSDNode_V<[sext], "PseudoVSEXT", "VF4",
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td331 (add VF2, VF3, VF4, VF5, VF0, VF1, VF6, VF7,
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td331 (add VF2, VF3, VF4, VF5, VF0, VF1, VF6, VF7,
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/PowerPC/
H A DPPCRegisterInfo.td331 (add VF2, VF3, VF4, VF5, VF0, VF1, VF6, VF7,
/dports/emulators/qemu/qemu-6.2.0/capstone/suite/synctools/tablegen/PPC/
H A DPPCRegisterInfo.td332 (add VF2, VF3, VF4, VF5, VF0, VF1, VF6, VF7,
/dports/emulators/qemu60/qemu-6.0.0/capstone/suite/synctools/tablegen/PPC/
H A DPPCRegisterInfo.td332 (add VF2, VF3, VF4, VF5, VF0, VF1, VF6, VF7,
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/PowerPC/
H A DPPCRegisterInfo.td331 (add VF2, VF3, VF4, VF5, VF0, VF1, VF6, VF7,
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td331 (add VF2, VF3, VF4, VF5, VF0, VF1, VF6, VF7,
/dports/emulators/qemu5/qemu-5.2.0/capstone/suite/synctools/tablegen/PPC/
H A DPPCRegisterInfo.td332 (add VF2, VF3, VF4, VF5, VF0, VF1, VF6, VF7,
/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/PowerPC/
H A DPPCRegisterInfo.td337 (add VF2, VF3, VF4, VF5, VF0, VF1, VF6, VF7,
/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/PowerPC/
H A DPPCRegisterInfo.td338 (add VF2, VF3, VF4, VF5, VF0, VF1, VF6, VF7,
/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/PowerPC/
H A DPPCRegisterInfo.td332 (add VF2, VF3, VF4, VF5, VF0, VF1, VF6, VF7,
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td360 (add VF2, VF3, VF4, VF5, VF0, VF1, VF6, VF7,
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td211 def W4 : Rd< 8, "v9:8", [V8, V9, VF4]>, DwarfRegNum<[107]>;
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td211 def W4 : Rd< 8, "v9:8", [V8, V9, VF4]>, DwarfRegNum<[107]>;
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td211 def W4 : Rd< 8, "v9:8", [V8, V9, VF4]>, DwarfRegNum<[107]>;
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td211 def W4 : Rd< 8, "v9:8", [V8, V9, VF4]>, DwarfRegNum<[107]>;
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td211 def W4 : Rd< 8, "v9:8", [V8, V9, VF4]>, DwarfRegNum<[107]>;
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td360 (add VF2, VF3, VF4, VF5, VF0, VF1, VF6, VF7,

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