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/dports/emulators/yuzu/yuzu-0b47f7a46/externals/dynarmic/src/frontend/A64/translate/impl/
H A Dsimd_scalar_pairwise.cpp38 v.V(128, Vd, v.ir.ZeroExtendToQuad(result)); in FPPairwiseMinMax()
43 bool TranslatorVisitor::ADDP_pair(Imm<2> size, Vec Vn, Vec Vd) { in ADDP_pair() argument
51 V(128, Vd, result); in ADDP_pair()
55 bool TranslatorVisitor::FADDP_pair_2(bool size, Vec Vn, Vec Vd) { in FADDP_pair_2() argument
61 V(128, Vd, result); in FADDP_pair_2()
65 bool TranslatorVisitor::FMAXNMP_pair_2(bool sz, Vec Vn, Vec Vd) { in FMAXNMP_pair_2() argument
69 bool TranslatorVisitor::FMAXP_pair_2(bool sz, Vec Vn, Vec Vd) { in FMAXP_pair_2() argument
70 return FPPairwiseMinMax(*this, sz, Vn, Vd, MinMaxOperation::Max); in FMAXP_pair_2()
73 bool TranslatorVisitor::FMINNMP_pair_2(bool sz, Vec Vn, Vec Vd) { in FMINNMP_pair_2() argument
77 bool TranslatorVisitor::FMINP_pair_2(bool sz, Vec Vn, Vec Vd) { in FMINP_pair_2() argument
[all …]
H A Dsimd_scalar_x_indexed_element.cpp27 Vec Vn, Vec Vd, ExtraBehavior extra_behavior) { in MultiplyByElement() argument
53 const IR::U32U64 operand2 = v.V_scalar(esize, Vd); in MultiplyByElement()
57 v.V_scalar(esize, Vd, result); in MultiplyByElement()
62 Vec Vn, Vec Vd, ExtraBehavior extra_behavior) { in MultiplyByElementHalfPrecision() argument
87 const IR::U16 operand2 = v.V_scalar(esize, Vd); in MultiplyByElementHalfPrecision()
91 v.V_scalar(esize, Vd, result); in MultiplyByElementHalfPrecision()
109 return MultiplyByElement(*this, sz, L, M, Vmlo, H, Vn, Vd, ExtraBehavior::Subtract); in FMLS_elt_2()
113 return MultiplyByElement(*this, sz, L, M, Vmlo, H, Vn, Vd, ExtraBehavior::None); in FMUL_elt_2()
134 V_scalar(esize, Vd, result.result); in SQDMULH_elt_1()
152 V(128, Vd, result); in SQRDMULH_elt_1()
[all …]
H A Dfloating_point_data_processing_two_register.cpp10 bool TranslatorVisitor::FMUL_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd) { in FMUL_float() argument
21 V_scalar(*datasize, Vd, result); in FMUL_float()
25 bool TranslatorVisitor::FDIV_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd) { in FDIV_float() argument
36 V_scalar(*datasize, Vd, result); in FDIV_float()
51 V_scalar(*datasize, Vd, result); in FADD_float()
66 V_scalar(*datasize, Vd, result); in FSUB_float()
81 V_scalar(*datasize, Vd, result); in FMAX_float()
96 V_scalar(*datasize, Vd, result); in FMIN_float()
111 V_scalar(*datasize, Vd, result); in FMAXNM_float()
126 V_scalar(*datasize, Vd, result); in FMINNM_float()
[all …]
H A Dsimd_permute.cpp28 v.V(datasize, Vd, result); in VectorTranspose()
51 v.V(datasize, Vd, result); in VectorUnzip()
56 bool TranslatorVisitor::TRN1(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { in TRN1() argument
60 bool TranslatorVisitor::TRN2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { in TRN2() argument
64 bool TranslatorVisitor::UZP1(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { in UZP1() argument
65 return VectorUnzip(*this, Q, size, Vm, Vn, Vd, UnzipType::Even); in UZP1()
68 bool TranslatorVisitor::UZP2(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { in UZP2() argument
69 return VectorUnzip(*this, Q, size, Vm, Vn, Vd, UnzipType::Odd); in UZP2()
72 bool TranslatorVisitor::ZIP1(bool Q, Imm<2> size, Vec Vm, Vec Vn, Vec Vd) { in ZIP1() argument
84 V(datasize, Vd, result); in ZIP1()
[all …]
H A Dsimd_aes.cpp10 bool TranslatorVisitor::AESD(Vec Vn, Vec Vd) { in AESD() argument
11 const IR::U128 operand1 = ir.GetQ(Vd); in AESD()
16 ir.SetQ(Vd, result); in AESD()
20 bool TranslatorVisitor::AESE(Vec Vn, Vec Vd) { in AESE() argument
21 const IR::U128 operand1 = ir.GetQ(Vd); in AESE()
26 ir.SetQ(Vd, result); in AESE()
30 bool TranslatorVisitor::AESIMC(Vec Vn, Vec Vd) { in AESIMC() argument
34 ir.SetQ(Vd, result); in AESIMC()
38 bool TranslatorVisitor::AESMC(Vec Vn, Vec Vd) { in AESMC() argument
42 ir.SetQ(Vd, result); in AESMC()
H A Dsimd_sha.cpp25 IR::U128 x = ir.GetQ(Vd); in SHA1HashUpdate()
114 ir.SetQ(Vd, result); in SHA1C()
120 ir.SetQ(Vd, result); in SHA1M()
126 ir.SetQ(Vd, result); in SHA1P()
146 ir.SetQ(Vd, result); in SHA1SU0()
163 ir.SetQ(Vd, result); in SHA1SU1()
173 ir.SetS(Vd, result); in SHA1H()
203 ir.SetQ(Vd, result); in SHA256SU0()
245 ir.SetQ(Vd, result); in SHA256SU1()
251 ir.SetQ(Vd, result); in SHA256H()
[all …]
/dports/emulators/citra/citra-ac98458e0/externals/dynarmic/src/frontend/A64/translate/impl/
H A Dsimd_scalar_pairwise.cpp38 v.V(128, Vd, v.ir.ZeroExtendToQuad(result)); in FPPairwiseMinMax()
43 bool TranslatorVisitor::ADDP_pair(Imm<2> size, Vec Vn, Vec Vd) { in ADDP_pair() argument
51 V(128, Vd, result); in ADDP_pair()
55 bool TranslatorVisitor::FADDP_pair_2(bool size, Vec Vn, Vec Vd) { in FADDP_pair_2() argument
61 V(128, Vd, result); in FADDP_pair_2()
65 bool TranslatorVisitor::FMAXNMP_pair_2(bool sz, Vec Vn, Vec Vd) { in FMAXNMP_pair_2() argument
69 bool TranslatorVisitor::FMAXP_pair_2(bool sz, Vec Vn, Vec Vd) { in FMAXP_pair_2() argument
70 return FPPairwiseMinMax(*this, sz, Vn, Vd, MinMaxOperation::Max); in FMAXP_pair_2()
73 bool TranslatorVisitor::FMINNMP_pair_2(bool sz, Vec Vn, Vec Vd) { in FMINNMP_pair_2() argument
77 bool TranslatorVisitor::FMINP_pair_2(bool sz, Vec Vn, Vec Vd) { in FMINP_pair_2() argument
[all …]
H A Dsimd_scalar_x_indexed_element.cpp27 Vec Vn, Vec Vd, ExtraBehavior extra_behavior) { in MultiplyByElement() argument
53 const IR::U32U64 operand2 = v.V_scalar(esize, Vd); in MultiplyByElement()
57 v.V_scalar(esize, Vd, result); in MultiplyByElement()
62 Vec Vn, Vec Vd, ExtraBehavior extra_behavior) { in MultiplyByElementHalfPrecision() argument
87 const IR::U16 operand2 = v.V_scalar(esize, Vd); in MultiplyByElementHalfPrecision()
91 v.V_scalar(esize, Vd, result); in MultiplyByElementHalfPrecision()
109 return MultiplyByElement(*this, sz, L, M, Vmlo, H, Vn, Vd, ExtraBehavior::Subtract); in FMLS_elt_2()
113 return MultiplyByElement(*this, sz, L, M, Vmlo, H, Vn, Vd, ExtraBehavior::None); in FMUL_elt_2()
134 V_scalar(esize, Vd, result.result); in SQDMULH_elt_1()
152 V(128, Vd, result); in SQRDMULH_elt_1()
[all …]
H A Dfloating_point_data_processing_two_register.cpp10 bool TranslatorVisitor::FMUL_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd) { in FMUL_float() argument
21 V_scalar(*datasize, Vd, result); in FMUL_float()
25 bool TranslatorVisitor::FDIV_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd) { in FDIV_float() argument
36 V_scalar(*datasize, Vd, result); in FDIV_float()
51 V_scalar(*datasize, Vd, result); in FADD_float()
66 V_scalar(*datasize, Vd, result); in FSUB_float()
81 V_scalar(*datasize, Vd, result); in FMAX_float()
96 V_scalar(*datasize, Vd, result); in FMIN_float()
111 V_scalar(*datasize, Vd, result); in FMAXNM_float()
126 V_scalar(*datasize, Vd, result); in FMINNM_float()
[all …]
H A Dsimd_aes.cpp10 bool TranslatorVisitor::AESD(Vec Vn, Vec Vd) { in AESD() argument
11 const IR::U128 operand1 = ir.GetQ(Vd); in AESD()
16 ir.SetQ(Vd, result); in AESD()
20 bool TranslatorVisitor::AESE(Vec Vn, Vec Vd) { in AESE() argument
21 const IR::U128 operand1 = ir.GetQ(Vd); in AESE()
26 ir.SetQ(Vd, result); in AESE()
30 bool TranslatorVisitor::AESIMC(Vec Vn, Vec Vd) { in AESIMC() argument
34 ir.SetQ(Vd, result); in AESIMC()
38 bool TranslatorVisitor::AESMC(Vec Vn, Vec Vd) { in AESMC() argument
42 ir.SetQ(Vd, result); in AESMC()
H A Dsimd_sha.cpp25 IR::U128 x = ir.GetQ(Vd); in SHA1HashUpdate()
114 ir.SetQ(Vd, result); in SHA1C()
120 ir.SetQ(Vd, result); in SHA1M()
126 ir.SetQ(Vd, result); in SHA1P()
146 ir.SetQ(Vd, result); in SHA1SU0()
163 ir.SetQ(Vd, result); in SHA1SU1()
173 ir.SetS(Vd, result); in SHA1H()
203 ir.SetQ(Vd, result); in SHA256SU0()
245 ir.SetQ(Vd, result); in SHA256SU1()
251 ir.SetQ(Vd, result); in SHA256H()
[all …]
/dports/emulators/citra-qt5/citra-ac98458e0/externals/dynarmic/src/frontend/A64/translate/impl/
H A Dsimd_scalar_pairwise.cpp38 v.V(128, Vd, v.ir.ZeroExtendToQuad(result)); in FPPairwiseMinMax()
43 bool TranslatorVisitor::ADDP_pair(Imm<2> size, Vec Vn, Vec Vd) { in ADDP_pair() argument
51 V(128, Vd, result); in ADDP_pair()
55 bool TranslatorVisitor::FADDP_pair_2(bool size, Vec Vn, Vec Vd) { in FADDP_pair_2() argument
61 V(128, Vd, result); in FADDP_pair_2()
65 bool TranslatorVisitor::FMAXNMP_pair_2(bool sz, Vec Vn, Vec Vd) { in FMAXNMP_pair_2() argument
69 bool TranslatorVisitor::FMAXP_pair_2(bool sz, Vec Vn, Vec Vd) { in FMAXP_pair_2() argument
70 return FPPairwiseMinMax(*this, sz, Vn, Vd, MinMaxOperation::Max); in FMAXP_pair_2()
73 bool TranslatorVisitor::FMINNMP_pair_2(bool sz, Vec Vn, Vec Vd) { in FMINNMP_pair_2() argument
77 bool TranslatorVisitor::FMINP_pair_2(bool sz, Vec Vn, Vec Vd) { in FMINP_pair_2() argument
[all …]
H A Dsimd_scalar_x_indexed_element.cpp27 Vec Vn, Vec Vd, ExtraBehavior extra_behavior) { in MultiplyByElement() argument
53 const IR::U32U64 operand2 = v.V_scalar(esize, Vd); in MultiplyByElement()
57 v.V_scalar(esize, Vd, result); in MultiplyByElement()
62 Vec Vn, Vec Vd, ExtraBehavior extra_behavior) { in MultiplyByElementHalfPrecision() argument
87 const IR::U16 operand2 = v.V_scalar(esize, Vd); in MultiplyByElementHalfPrecision()
91 v.V_scalar(esize, Vd, result); in MultiplyByElementHalfPrecision()
109 return MultiplyByElement(*this, sz, L, M, Vmlo, H, Vn, Vd, ExtraBehavior::Subtract); in FMLS_elt_2()
113 return MultiplyByElement(*this, sz, L, M, Vmlo, H, Vn, Vd, ExtraBehavior::None); in FMUL_elt_2()
134 V_scalar(esize, Vd, result.result); in SQDMULH_elt_1()
152 V(128, Vd, result); in SQRDMULH_elt_1()
[all …]
H A Dfloating_point_data_processing_two_register.cpp10 bool TranslatorVisitor::FMUL_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd) { in FMUL_float() argument
21 V_scalar(*datasize, Vd, result); in FMUL_float()
25 bool TranslatorVisitor::FDIV_float(Imm<2> type, Vec Vm, Vec Vn, Vec Vd) { in FDIV_float() argument
36 V_scalar(*datasize, Vd, result); in FDIV_float()
51 V_scalar(*datasize, Vd, result); in FADD_float()
66 V_scalar(*datasize, Vd, result); in FSUB_float()
81 V_scalar(*datasize, Vd, result); in FMAX_float()
96 V_scalar(*datasize, Vd, result); in FMIN_float()
111 V_scalar(*datasize, Vd, result); in FMAXNM_float()
126 V_scalar(*datasize, Vd, result); in FMINNM_float()
[all …]
H A Dsimd_aes.cpp10 bool TranslatorVisitor::AESD(Vec Vn, Vec Vd) { in AESD() argument
11 const IR::U128 operand1 = ir.GetQ(Vd); in AESD()
16 ir.SetQ(Vd, result); in AESD()
20 bool TranslatorVisitor::AESE(Vec Vn, Vec Vd) { in AESE() argument
21 const IR::U128 operand1 = ir.GetQ(Vd); in AESE()
26 ir.SetQ(Vd, result); in AESE()
30 bool TranslatorVisitor::AESIMC(Vec Vn, Vec Vd) { in AESIMC() argument
34 ir.SetQ(Vd, result); in AESIMC()
38 bool TranslatorVisitor::AESMC(Vec Vn, Vec Vd) { in AESMC() argument
42 ir.SetQ(Vd, result); in AESMC()
H A Dsimd_sha.cpp25 IR::U128 x = ir.GetQ(Vd); in SHA1HashUpdate()
114 ir.SetQ(Vd, result); in SHA1C()
120 ir.SetQ(Vd, result); in SHA1M()
126 ir.SetQ(Vd, result); in SHA1P()
146 ir.SetQ(Vd, result); in SHA1SU0()
163 ir.SetQ(Vd, result); in SHA1SU1()
173 ir.SetS(Vd, result); in SHA1H()
203 ir.SetQ(Vd, result); in SHA256SU0()
245 ir.SetQ(Vd, result); in SHA256SU1()
251 ir.SetQ(Vd, result); in SHA256H()
[all …]
/dports/cad/ngspice_rework/ngspice-35/examples/tclspice/tcl/
H A Dtest_vectoblt.sh10 spice::let Vd = V(5) - V(4)
23 if {[catch {spice::vectoblt Vd ibrahim} erreur] != 0} {puts "ERROR EXPECTED: TEST 3 OK:\n\t$erreur"…
25 if {[catch {spice::vectoblt Vd real} erreur] == 0} {puts "NO ERROR IN AFFECTATION. TEST 4 OK:\n\t (…
27 if {[catch {spice::vectoblt Vd ibrahim ector} erreur] != 0} {puts "ERROR EXPECTED: TEST 5 OK:\n\t$e…
29 if {[catch {spice::vectoblt Vd real ector} erreur] != 0} {puts "ERROR EXPECTED: TEST 6 OK:\n\t$erre…
33 if {[catch {spice::vectoblt Vd real imag karim} erreur] != 0} {puts "ERROR EXPECTED: TEST 8 OK:\n\t…
40 spice::let Vd = V(5) - V(4)
46 if {[catch {spice::vectoblt Vd ibrahim} erreur] != 0} {puts "ERROR EXPECTED: TEST 3 OK:\n\t$erreur"…
50 if {[catch {spice::vectoblt Vd ibrahim ector} erreur] != 0} {puts "ERROR EXPECTED: TEST 5 OK:\n\t$e…
52 if {[catch {spice::vectoblt Vd real ector} erreur] != 0} {puts "ERROR EXPECTED: TEST 6 OK:\n\t$erre…
[all …]
/dports/emulators/citra/citra-ac98458e0/externals/dynarmic/src/frontend/A32/translate/impl/
H A Dasimd_two_regs_misc.cpp17 if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { in asimd_VCLS()
21 const auto d = ToVector(Q, Vd, D); in asimd_VCLS()
41 if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { in asimd_VCLZ()
45 const auto d = ToVector(Q, Vd, D); in asimd_VCLZ()
63 if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { in asimd_VCNT()
67 const auto d = ToVector(Q, Vd, D); in asimd_VCNT()
81 if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { in asimd_VNEG()
85 const auto d = ToVector(Q, Vd, D); in asimd_VNEG()
102 bool ArmTranslatorVisitor::asimd_VSWP(bool D, size_t Vd, bool Q, bool M, size_t Vm) { in asimd_VSWP() argument
103 if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { in asimd_VSWP()
[all …]
/dports/emulators/citra-qt5/citra-ac98458e0/externals/dynarmic/src/frontend/A32/translate/impl/
H A Dasimd_two_regs_misc.cpp17 if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { in asimd_VCLS()
21 const auto d = ToVector(Q, Vd, D); in asimd_VCLS()
41 if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { in asimd_VCLZ()
45 const auto d = ToVector(Q, Vd, D); in asimd_VCLZ()
63 if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { in asimd_VCNT()
67 const auto d = ToVector(Q, Vd, D); in asimd_VCNT()
81 if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { in asimd_VNEG()
85 const auto d = ToVector(Q, Vd, D); in asimd_VNEG()
102 bool ArmTranslatorVisitor::asimd_VSWP(bool D, size_t Vd, bool Q, bool M, size_t Vm) { in asimd_VSWP() argument
103 if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vm))) { in asimd_VSWP()
[all …]
/dports/www/qt5-webengine/qtwebengine-everywhere-src-5.15.2/src/3rdparty/chromium/v8/src/diagnostics/arm/
H A Ddisasm-arm.cc85 void FormatNeonList(int Vd, int type);
365 SNPrintF(out_buffer_ + out_buffer_pos_, "{d%d, d%d}", Vd, Vd + 1); in FormatNeonList()
368 "{d%d, d%d, d%d}", Vd, Vd + 1, Vd + 2); in FormatNeonList()
372 Vd + 1, Vd + 2, Vd + 3); in FormatNeonList()
1829 int Vd, Vm, Vn; in DecodeSpecialCondition() local
2035 Vd, Vn, Vm, imm4); in DecodeSpecialCondition()
2063 int Vd, Vm, Vn; in DecodeSpecialCondition() local
2268 int Vd, Vm; in DecodeSpecialCondition() local
2407 size, Vd, Vn, Vm); in DecodeSpecialCondition()
2433 FormatNeonList(Vd, type); in DecodeSpecialCondition()
[all …]
/dports/math/gnuplot/gnuplot-5.4.1/demo/
H A Delectron.dem31 Ida(Vd)=Ido*(1-Vg/Vp)**2
33 Idb(Vd)=Ido*(2*Vd*(Vg-Vp)-Vd*Vd)/(Vp*Vp)
35 Id(Vd)= (Vd>Vg-Vp) ? Ida(Vd) : Idb(Vd)
42 set dummy Vd
47 set xlabel "Drain voltage Vd (V)"
56 plot Vg=0.5*Vp,Id(Vd),Vg=0.25*Vp,Id(Vd),Vg=0,Id(Vd),Vg=-0.25*Vp,Id(Vd)
/dports/math/gnuplot-lite/gnuplot-5.4.1/demo/
H A Delectron.dem31 Ida(Vd)=Ido*(1-Vg/Vp)**2
33 Idb(Vd)=Ido*(2*Vd*(Vg-Vp)-Vd*Vd)/(Vp*Vp)
35 Id(Vd)= (Vd>Vg-Vp) ? Ida(Vd) : Idb(Vd)
42 set dummy Vd
47 set xlabel "Drain voltage Vd (V)"
56 plot Vg=0.5*Vp,Id(Vd),Vg=0.25*Vp,Id(Vd),Vg=0,Id(Vd),Vg=-0.25*Vp,Id(Vd)
/dports/math/gnuplot-tex-extras/gnuplot-5.2.8/demo/
H A Delectron.dem34 Ida(Vd)=Ido*(1-Vg/Vp)**2
36 Idb(Vd)=Ido*(2*Vd*(Vg-Vp)-Vd*Vd)/(Vp*Vp)
38 Id(Vd)= (Vd>Vg-Vp) ? Ida(Vd) : Idb(Vd)
45 set dummy Vd
50 set xlabel "Drain voltage Vd (V)"
59 plot Vg=0.5*Vp,Id(Vd),Vg=0.25*Vp,Id(Vd),Vg=0,Id(Vd),Vg=-0.25*Vp,Id(Vd)
/dports/emulators/yuzu/yuzu-0b47f7a46/externals/dynarmic/src/frontend/A32/translate/impl/
H A Dasimd_two_regs_scalar.cpp42 if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn))) { in ScalarMultiply()
47 const auto d = ToVector(Q, Vd, D); in ScalarMultiply()
80 if (sz == 0b00 || Common::Bit<0>(Vd)) { in ScalarMultiplyLong()
85 const auto d = ToVector(true, Vd, D); in ScalarMultiplyLong()
122 if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn))) { in ScalarMultiplyReturnHigh()
127 const auto d = ToVector(Q, Vd, D); in ScalarMultiplyReturnHigh()
152 return ScalarMultiply(*this, Q, D, sz, Vn, Vd, F, N, M, Vm, behavior); in asimd_VMLA_scalar()
158 return ScalarMultiplyLong(*this, U, D, sz, Vn, Vd, N, M, Vm, behavior); in asimd_VMLAL_scalar()
174 if (sz == 0b00 || Common::Bit<0>(Vd)) { in asimd_VQDMULL_scalar()
179 const auto d = ToVector(true, Vd, D); in asimd_VQDMULL_scalar()
[all …]
/dports/lang/v8/v8-9.6.180.12/src/execution/arm/
H A Dsimulator-arm.cc4145 Binop<T, SIZE>(simulator, Vd, Vm, Vd, in ShiftRightAccumulate()
4152 Binop<T, SIZE>(simulator, Vd, Vm, Vd, [shift](T a, T x) { in ArithmeticShiftRightAccumulate()
4376 set_neon_register(Vd, dst); in DecodeAdvancedSIMDTwoOrThreeRegisters()
4849 set_neon_register(Vd, src); in DecodeAdvancedSIMDTwoOrThreeRegisters()
5030 int Vd, Vm, Vn; in DecodeAdvancedSIMDDataProcessing() local
5270 set_neon_register(Vd, dst); in DecodeAdvancedSIMDDataProcessing()
5320 get_neon_register(Vd, dst); in DecodeAdvancedSIMDDataProcessing()
5333 set_d_register(Vd, &src1); in DecodeAdvancedSIMDDataProcessing()
5854 get_d_register(Vd, &dreg); in DecodeAdvancedSIMDLoadStoreSingleStructureToOneLane()
5882 set_d_register(Vd, &dreg); in DecodeAdvancedSIMDLoadStoreSingleStructureToOneLane()
[all …]

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