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Searched refs:clk_sel (Results 126 – 150 of 348) sorted by relevance

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/dports/sysutils/u-boot-rpi3/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c324 static u32 get_standard_pll_sel_clk(u32 clk_sel) in get_standard_pll_sel_clk() argument
328 switch (clk_sel & 0x3) { in get_standard_pll_sel_clk()
351 unsigned int clk_sel, freq, reg, pred, podf; in get_uart_clk() local
354 clk_sel = MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg); in get_uart_clk()
355 freq = get_standard_pll_sel_clk(clk_sel); in get_uart_clk()
370 u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq; in imx_get_cspiclk() local
377 freq = get_standard_pll_sel_clk(clk_sel); in imx_get_cspiclk()
387 u32 clk_sel = 0, pred = 0, podf = 0, freq = 0; in get_esdhc_clk() local
799 s32 shift = 0, clk_sel, div = 1; in config_ddr_clk() local
810 clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr); in config_ddr_clk()
[all …]
/dports/sysutils/u-boot-rpi3-32/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c324 static u32 get_standard_pll_sel_clk(u32 clk_sel) in get_standard_pll_sel_clk() argument
328 switch (clk_sel & 0x3) { in get_standard_pll_sel_clk()
351 unsigned int clk_sel, freq, reg, pred, podf; in get_uart_clk() local
354 clk_sel = MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg); in get_uart_clk()
355 freq = get_standard_pll_sel_clk(clk_sel); in get_uart_clk()
370 u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq; in imx_get_cspiclk() local
377 freq = get_standard_pll_sel_clk(clk_sel); in imx_get_cspiclk()
387 u32 clk_sel = 0, pred = 0, podf = 0, freq = 0; in get_esdhc_clk() local
799 s32 shift = 0, clk_sel, div = 1; in config_ddr_clk() local
810 clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr); in config_ddr_clk()
[all …]
/dports/sysutils/u-boot-rock64/u-boot-2021.07/arch/arm/mach-imx/mx5/
H A Dclock.c324 static u32 get_standard_pll_sel_clk(u32 clk_sel) in get_standard_pll_sel_clk() argument
328 switch (clk_sel & 0x3) { in get_standard_pll_sel_clk()
351 unsigned int clk_sel, freq, reg, pred, podf; in get_uart_clk() local
354 clk_sel = MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg); in get_uart_clk()
355 freq = get_standard_pll_sel_clk(clk_sel); in get_uart_clk()
370 u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq; in imx_get_cspiclk() local
377 freq = get_standard_pll_sel_clk(clk_sel); in imx_get_cspiclk()
387 u32 clk_sel = 0, pred = 0, podf = 0, freq = 0; in get_esdhc_clk() local
799 s32 shift = 0, clk_sel, div = 1; in config_ddr_clk() local
810 clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr); in config_ddr_clk()
[all …]
/dports/sysutils/u-boot-tools/u-boot-2020.07/arch/x86/cpu/apollolake/
H A Duart.c37 u32 clk_sel; in lpss_clk_update() local
39 clk_sel = clk_n_val << LPSS_CLOCK_DIV_N_SHIFT | in lpss_clk_update()
41 clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN; in lpss_clk_update()
43 writel(clk_sel, regs + LPSS_CLOCK_CTL_REG); in lpss_clk_update()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/x86/cpu/apollolake/
H A Duart.c39 u32 clk_sel; in lpss_clk_update() local
41 clk_sel = clk_n_val << LPSS_CLOCK_DIV_N_SHIFT | in lpss_clk_update()
43 clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN; in lpss_clk_update()
45 writel(clk_sel, regs + LPSS_CLOCK_CTL_REG); in lpss_clk_update()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/x86/cpu/apollolake/
H A Duart.c39 u32 clk_sel; in lpss_clk_update() local
41 clk_sel = clk_n_val << LPSS_CLOCK_DIV_N_SHIFT | in lpss_clk_update()
43 clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN; in lpss_clk_update()
45 writel(clk_sel, regs + LPSS_CLOCK_CTL_REG); in lpss_clk_update()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/x86/cpu/apollolake/
H A Duart.c39 u32 clk_sel; in lpss_clk_update() local
41 clk_sel = clk_n_val << LPSS_CLOCK_DIV_N_SHIFT | in lpss_clk_update()
43 clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN; in lpss_clk_update()
45 writel(clk_sel, regs + LPSS_CLOCK_CTL_REG); in lpss_clk_update()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/x86/cpu/apollolake/
H A Duart.c39 u32 clk_sel; in lpss_clk_update() local
41 clk_sel = clk_n_val << LPSS_CLOCK_DIV_N_SHIFT | in lpss_clk_update()
43 clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN; in lpss_clk_update()
45 writel(clk_sel, regs + LPSS_CLOCK_CTL_REG); in lpss_clk_update()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/x86/cpu/apollolake/
H A Duart.c39 u32 clk_sel; in lpss_clk_update() local
41 clk_sel = clk_n_val << LPSS_CLOCK_DIV_N_SHIFT | in lpss_clk_update()
43 clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN; in lpss_clk_update()
45 writel(clk_sel, regs + LPSS_CLOCK_CTL_REG); in lpss_clk_update()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/x86/cpu/apollolake/
H A Duart.c39 u32 clk_sel; in lpss_clk_update() local
41 clk_sel = clk_n_val << LPSS_CLOCK_DIV_N_SHIFT | in lpss_clk_update()
43 clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN; in lpss_clk_update()
45 writel(clk_sel, regs + LPSS_CLOCK_CTL_REG); in lpss_clk_update()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/x86/cpu/apollolake/
H A Duart.c39 u32 clk_sel; in lpss_clk_update() local
41 clk_sel = clk_n_val << LPSS_CLOCK_DIV_N_SHIFT | in lpss_clk_update()
43 clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN; in lpss_clk_update()
45 writel(clk_sel, regs + LPSS_CLOCK_CTL_REG); in lpss_clk_update()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/x86/cpu/apollolake/
H A Duart.c39 u32 clk_sel; in lpss_clk_update() local
41 clk_sel = clk_n_val << LPSS_CLOCK_DIV_N_SHIFT | in lpss_clk_update()
43 clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN; in lpss_clk_update()
45 writel(clk_sel, regs + LPSS_CLOCK_CTL_REG); in lpss_clk_update()
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/arch/x86/cpu/apollolake/
H A Duart.c39 u32 clk_sel; in lpss_clk_update() local
41 clk_sel = clk_n_val << LPSS_CLOCK_DIV_N_SHIFT | in lpss_clk_update()
43 clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN; in lpss_clk_update()
45 writel(clk_sel, regs + LPSS_CLOCK_CTL_REG); in lpss_clk_update()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/x86/cpu/apollolake/
H A Duart.c39 u32 clk_sel; in lpss_clk_update() local
41 clk_sel = clk_n_val << LPSS_CLOCK_DIV_N_SHIFT | in lpss_clk_update()
43 clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN; in lpss_clk_update()
45 writel(clk_sel, regs + LPSS_CLOCK_CTL_REG); in lpss_clk_update()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/x86/cpu/apollolake/
H A Duart.c39 u32 clk_sel; in lpss_clk_update() local
41 clk_sel = clk_n_val << LPSS_CLOCK_DIV_N_SHIFT | in lpss_clk_update()
43 clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN; in lpss_clk_update()
45 writel(clk_sel, regs + LPSS_CLOCK_CTL_REG); in lpss_clk_update()
/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/x86/cpu/apollolake/
H A Duart.c39 u32 clk_sel; in lpss_clk_update() local
41 clk_sel = clk_n_val << LPSS_CLOCK_DIV_N_SHIFT | in lpss_clk_update()
43 clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN; in lpss_clk_update()
45 writel(clk_sel, regs + LPSS_CLOCK_CTL_REG); in lpss_clk_update()
/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/x86/cpu/apollolake/
H A Duart.c39 u32 clk_sel; in lpss_clk_update() local
41 clk_sel = clk_n_val << LPSS_CLOCK_DIV_N_SHIFT | in lpss_clk_update()
43 clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN; in lpss_clk_update()
45 writel(clk_sel, regs + LPSS_CLOCK_CTL_REG); in lpss_clk_update()
/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/x86/cpu/apollolake/
H A Duart.c39 u32 clk_sel; in lpss_clk_update() local
41 clk_sel = clk_n_val << LPSS_CLOCK_DIV_N_SHIFT | in lpss_clk_update()
43 clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN; in lpss_clk_update()
45 writel(clk_sel, regs + LPSS_CLOCK_CTL_REG); in lpss_clk_update()
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/x86/cpu/apollolake/
H A Duart.c39 u32 clk_sel; in lpss_clk_update() local
41 clk_sel = clk_n_val << LPSS_CLOCK_DIV_N_SHIFT | in lpss_clk_update()
43 clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN; in lpss_clk_update()
45 writel(clk_sel, regs + LPSS_CLOCK_CTL_REG); in lpss_clk_update()
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/x86/cpu/apollolake/
H A Duart.c39 u32 clk_sel; in lpss_clk_update() local
41 clk_sel = clk_n_val << LPSS_CLOCK_DIV_N_SHIFT | in lpss_clk_update()
43 clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN; in lpss_clk_update()
45 writel(clk_sel, regs + LPSS_CLOCK_CTL_REG); in lpss_clk_update()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/x86/cpu/apollolake/
H A Duart.c39 u32 clk_sel; in lpss_clk_update() local
41 clk_sel = clk_n_val << LPSS_CLOCK_DIV_N_SHIFT | in lpss_clk_update()
43 clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN; in lpss_clk_update()
45 writel(clk_sel, regs + LPSS_CLOCK_CTL_REG); in lpss_clk_update()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/x86/cpu/apollolake/
H A Duart.c39 u32 clk_sel; in lpss_clk_update() local
41 clk_sel = clk_n_val << LPSS_CLOCK_DIV_N_SHIFT | in lpss_clk_update()
43 clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN; in lpss_clk_update()
45 writel(clk_sel, regs + LPSS_CLOCK_CTL_REG); in lpss_clk_update()
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/x86/cpu/apollolake/
H A Duart.c39 u32 clk_sel; in lpss_clk_update() local
41 clk_sel = clk_n_val << LPSS_CLOCK_DIV_N_SHIFT | in lpss_clk_update()
43 clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN; in lpss_clk_update()
45 writel(clk_sel, regs + LPSS_CLOCK_CTL_REG); in lpss_clk_update()
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/x86/cpu/apollolake/
H A Duart.c39 u32 clk_sel; in lpss_clk_update() local
41 clk_sel = clk_n_val << LPSS_CLOCK_DIV_N_SHIFT | in lpss_clk_update()
43 clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN; in lpss_clk_update()
45 writel(clk_sel, regs + LPSS_CLOCK_CTL_REG); in lpss_clk_update()
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/x86/cpu/apollolake/
H A Duart.c39 u32 clk_sel; in lpss_clk_update() local
41 clk_sel = clk_n_val << LPSS_CLOCK_DIV_N_SHIFT | in lpss_clk_update()
43 clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN; in lpss_clk_update()
45 writel(clk_sel, regs + LPSS_CLOCK_CTL_REG); in lpss_clk_update()

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