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Searched refs:div_dmc1 (Results 201 – 225 of 252) sorted by relevance

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/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/board/samsung/trats/
H A Dtrats.c328 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); in board_clock_init()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/board/samsung/trats/
H A Dtrats.c328 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); in board_clock_init()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/board/samsung/trats/
H A Dtrats.c328 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); in board_clock_init()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/board/samsung/trats/
H A Dtrats.c328 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); in board_clock_init()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/board/samsung/trats/
H A Dtrats.c328 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); in board_clock_init()
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/board/samsung/trats/
H A Dtrats.c328 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); in board_clock_init()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/board/samsung/trats/
H A Dtrats.c328 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); in board_clock_init()
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/board/samsung/trats/
H A Dtrats.c328 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); in board_clock_init()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/board/samsung/trats/
H A Dtrats.c328 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); in board_clock_init()
/dports/sysutils/u-boot-chip/u-boot-2021.07/board/samsung/trats/
H A Dtrats.c328 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); in board_clock_init()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/board/samsung/trats/
H A Dtrats.c325 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); in board_clock_init()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/board/samsung/trats/
H A Dtrats.c325 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); in board_clock_init()
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/board/samsung/trats/
H A Dtrats.c328 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); in board_clock_init()
/dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/board/samsung/trats/
H A Dtrats.c328 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); in board_clock_init()
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/board/samsung/trats/
H A Dtrats.c328 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); in board_clock_init()
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/board/samsung/trats/
H A Dtrats.c328 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); in board_clock_init()
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/board/samsung/trats/
H A Dtrats.c328 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); in board_clock_init()
/dports/sysutils/u-boot-pcduino3/u-boot-2021.07/board/samsung/trats/
H A Dtrats.c328 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); in board_clock_init()
/dports/sysutils/u-boot-pine64/u-boot-2021.07/board/samsung/trats/
H A Dtrats.c328 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); in board_clock_init()
/dports/sysutils/u-boot-pine-h64/u-boot-2021.07/board/samsung/trats/
H A Dtrats.c328 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); in board_clock_init()
/dports/sysutils/u-boot-pinebook/u-boot-2021.07/board/samsung/trats/
H A Dtrats.c328 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); in board_clock_init()
/dports/sysutils/u-boot-pine64-lts/u-boot-2021.07/board/samsung/trats/
H A Dtrats.c328 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); in board_clock_init()
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/board/samsung/trats/
H A Dtrats.c328 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); in board_clock_init()
/dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/board/samsung/trats/
H A Dtrats.c328 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); in board_clock_init()
/dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/board/samsung/trats/
H A Dtrats.c328 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); in board_clock_init()

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