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Searched refs:dpll_hz (Results 26 – 50 of 114) sorted by relevance

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/dports/sysutils/u-boot-pcduino3/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3308.c117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate()
155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk()
164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk()
390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk()
399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk()
434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk()
443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk()
470 parent = priv->dpll_hz; in rk3308_vop_get_clk()
500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk()
548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk()
[all …]
/dports/sysutils/u-boot-pinebook/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3308.c117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate()
155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk()
164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk()
390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk()
399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk()
434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk()
443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk()
470 parent = priv->dpll_hz; in rk3308_vop_get_clk()
500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk()
548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk()
[all …]
/dports/sysutils/u-boot-pinebookpro/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3308.c117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate()
155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk()
164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk()
390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk()
399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk()
434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk()
443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk()
470 parent = priv->dpll_hz; in rk3308_vop_get_clk()
500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk()
548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk()
[all …]
/dports/sysutils/u-boot-pine64-lts/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3308.c117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate()
155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk()
164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk()
390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk()
399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk()
434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk()
443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk()
470 parent = priv->dpll_hz; in rk3308_vop_get_clk()
500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk()
548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk()
[all …]
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3308.c117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate()
155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk()
164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk()
390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk()
399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk()
434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk()
443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk()
470 parent = priv->dpll_hz; in rk3308_vop_get_clk()
500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk()
548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk()
[all …]
/dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3308.c117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate()
155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk()
164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk()
390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk()
399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk()
434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk()
443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk()
470 parent = priv->dpll_hz; in rk3308_vop_get_clk()
500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk()
548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk()
[all …]
/dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3308.c117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate()
155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk()
164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk()
390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk()
399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk()
434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk()
443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk()
470 parent = priv->dpll_hz; in rk3308_vop_get_clk()
500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk()
548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk()
[all …]
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot/drivers/clk/rockchip/
H A Dclk_rk3308.c117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate()
155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk()
164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk()
390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk()
399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk()
434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk()
443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk()
470 parent = priv->dpll_hz; in rk3308_vop_get_clk()
500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk()
548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk()
[all …]
/dports/sysutils/u-boot-orangepi-pc2/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3308.c117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate()
155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk()
164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk()
390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk()
399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk()
434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk()
443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk()
470 parent = priv->dpll_hz; in rk3308_vop_get_clk()
500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk()
548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk()
[all …]
/dports/sysutils/u-boot-orangepi-plus-2e/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3308.c117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate()
155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk()
164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk()
390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk()
399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk()
434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk()
443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk()
470 parent = priv->dpll_hz; in rk3308_vop_get_clk()
500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk()
548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk()
[all …]
/dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3308.c117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate()
155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk()
164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk()
390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk()
399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk()
434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk()
443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk()
470 parent = priv->dpll_hz; in rk3308_vop_get_clk()
500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk()
548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk()
[all …]
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3308.c117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate()
155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk()
164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk()
390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk()
399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk()
434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk()
443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk()
470 parent = priv->dpll_hz; in rk3308_vop_get_clk()
500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk()
548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk()
[all …]
/dports/sysutils/u-boot-orangepi-pc/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3308.c117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate()
155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk()
164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk()
390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk()
399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk()
434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk()
443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk()
470 parent = priv->dpll_hz; in rk3308_vop_get_clk()
500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk()
548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk()
[all …]
/dports/sysutils/u-boot-orangepi-one/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3308.c117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate()
155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk()
164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk()
390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk()
399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk()
434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk()
443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk()
470 parent = priv->dpll_hz; in rk3308_vop_get_clk()
500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk()
548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk()
[all …]
/dports/sysutils/u-boot-orangepi-pc-plus/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3308.c117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate()
155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk()
164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk()
390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk()
399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk()
434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk()
443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk()
470 parent = priv->dpll_hz; in rk3308_vop_get_clk()
500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk()
548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk()
[all …]
/dports/sysutils/u-boot-bananapi/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3308.c117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate()
155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk()
164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk()
390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk()
399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk()
434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk()
443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk()
470 parent = priv->dpll_hz; in rk3308_vop_get_clk()
500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk()
548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk()
[all …]
/dports/sysutils/u-boot-tools/u-boot-2020.07/drivers/clk/rockchip/
H A Dclk_rk3308.c115 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate()
153 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk()
162 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk()
388 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk()
397 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk()
432 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk()
441 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk()
468 parent = priv->dpll_hz; in rk3308_vop_get_clk()
498 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk()
546 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk()
[all …]
/dports/sysutils/u-boot-bananapim2/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3308.c117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate()
155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk()
164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk()
390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk()
399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk()
434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk()
443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk()
470 parent = priv->dpll_hz; in rk3308_vop_get_clk()
500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk()
548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk()
[all …]
/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3308.c117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate()
155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk()
164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk()
390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk()
399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk()
434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk()
443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk()
470 parent = priv->dpll_hz; in rk3308_vop_get_clk()
500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk()
548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk()
[all …]
/dports/sysutils/u-boot-rockpro64/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3308.c117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate()
155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk()
164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk()
390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk()
399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk()
434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk()
443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk()
470 parent = priv->dpll_hz; in rk3308_vop_get_clk()
500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk()
548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk()
[all …]
/dports/sysutils/u-boot-rpi3-32/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3308.c117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate()
155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk()
164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk()
390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk()
399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk()
434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk()
443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk()
470 parent = priv->dpll_hz; in rk3308_vop_get_clk()
500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk()
548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk()
[all …]
/dports/sysutils/u-boot-rpi4/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3308.c117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate()
155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk()
164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk()
390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk()
399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk()
434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk()
443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk()
470 parent = priv->dpll_hz; in rk3308_vop_get_clk()
500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk()
548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk()
[all …]
/dports/sysutils/u-boot-sifive-fu540/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3308.c117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate()
155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk()
164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk()
390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk()
399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk()
434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk()
443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk()
470 parent = priv->dpll_hz; in rk3308_vop_get_clk()
500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk()
548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk()
[all …]
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3308.c117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate()
155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk()
164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk()
390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk()
399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk()
434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk()
443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk()
470 parent = priv->dpll_hz; in rk3308_vop_get_clk()
500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk()
548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk()
[all …]
/dports/sysutils/u-boot-qemu-arm/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3308.c117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate()
155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk()
164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk()
390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk()
399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk()
434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk()
443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk()
470 parent = priv->dpll_hz; in rk3308_vop_get_clk()
500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk()
548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk()
[all …]

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