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/dports/games/gcompris-qt/gcompris-qt-2.0/src/activities/renewable_energy/
H A DActivityInfo.qml17 …description: qsTr("Tux has come back from fishing on his boat. Bring the electrical system back up…
20 goal: qsTr("Learn about an electrical system based on renewable energy.")
22 …r array, wind farm and transformers, in order to reactivate the entire electrical system. When the…
/dports/cad/ghdl/ghdl-1.0.0/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/
H A Dinline_07a.vhd23 port ( terminal anode, cathode : electrical );
31 port ( terminal a : electrical;
42 port ( terminal p, m : electrical;
/dports/cad/ghdl/ghdl-1.0.0/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/
H A Dtb_CS5_Amp_Lim.vhd28 terminal output: electrical);
50 port ( terminal input : electrical;
51 terminal output: electrical);
75 terminal input: electrical;
76 terminal output: electrical);
120 terminal output: electrical);
157 terminal error : electrical;
158 terminal ll_in : electrical;
159 terminal ll_out : electrical;
918 terminal pos, neg : electrical
[all …]
H A Dtb_CS5_HCL.vhd27 port ( terminal in1, in2: electrical;
28 terminal output: electrical);
50 port ( terminal input : electrical;
51 terminal output: electrical);
75 terminal input: electrical;
76 terminal output: electrical);
120 terminal output: electrical);
156 terminal error : electrical;
157 terminal ll_in : electrical;
158 terminal ll_out : electrical;
[all …]
/dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/bug031/
H A Dams1.vhdl5 nature electrical is real across real through ground reference;
6 -- terminal nx : electrical;
/dports/cad/ghdl/ghdl-1.0.0/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/
H A Dtest151.ams53 NATURE electrical IS real ACROSS real THROUGH ground reference;
63 terminal T1:electrical;
64 quantity V1 across I1 through T1 to electrical'reference;
65 quantity V2 across I2 through T1 to electrical'reference;
/dports/cad/ghdl/ghdl-1.0.0/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/
H A Dtest186.ams38 NATURE electrical IS voltage ACROSS current THROUGH Ground reference;
39 --NATURE electrical IS real ACROSS real THROUGH Ground reference;
40 NATURE electrical_vector is array(natural range<>) of electrical ;
59 terminal n1 : electrical;
H A Dtest107.ams53 NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
59 terminal T1, T2: electrical); --terminal declarations
102 terminal tout : electrical;
104 terminal T1, T2: electrical);
110 unit:dac port map (myinputvector, tout, electrical'reference);
/dports/cad/ghdl/ghdl-1.0.0/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/
H A Dtest151.ams53 NATURE electrical IS real ACROSS real THROUGH ground reference;
63 terminal T1:electrical;
64 quantity V1 across I1 through T1 to electrical'reference;
65 quantity V2 across I2 through T1 to electrical'reference;
H A Dtest107.ams53 NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
59 terminal T1, T2: electrical); --terminal declarations
102 terminal tout : electrical;
104 terminal T1, T2: electrical);
110 unit:dac port map (myinputvector, tout, electrical'reference);
/dports/cad/lepton-eda/lepton-eda-1.9.17/utils/netlist/examples/vams/vhdl/basic-vhdl/
H A Dresistor.vhdl10 PORT ( terminal LT : electrical;
11 terminal RT : electrical );
H A Dcapacitor.vhdl11 PORT ( terminal RT : electrical;
12 terminal LT : electrical );
H A Dcurrent_source.vhdl12 PORT ( terminal RT : electrical;
13 terminal LT : electrical );
H A Dvoltage_source.vhdl14 PORT ( terminal RT : electrical;
15 terminal LT : electrical );
/dports/cad/lepton-eda/lepton-eda-1.9.17/utils/netlist/examples/vams/vhdl/new-vhdl/
H A Dresistor.vhdl10 PORT ( terminal LT : electrical;
11 terminal RT : electrical );
/dports/cad/geda/geda-gaf-1.8.2/gnetlist/examples/vams/vhdl/basic-vhdl/
H A Dresistor.vhdl10 PORT ( terminal LT : electrical;
11 terminal RT : electrical );
H A Dcapacitor.vhdl11 PORT ( terminal RT : electrical;
12 terminal LT : electrical );
H A Dcurrent_source.vhdl12 PORT ( terminal RT : electrical;
13 terminal LT : electrical );
H A Dvoltage_source.vhdl14 PORT ( terminal RT : electrical;
15 terminal LT : electrical );
/dports/cad/geda/geda-gaf-1.8.2/gnetlist/examples/vams/vhdl/new-vhdl/
H A Dresistor.vhdl10 PORT ( terminal LT : electrical;
11 terminal RT : electrical );
/dports/cad/lepton-eda/lepton-eda-1.9.17/utils/netlist/examples/vams/sym/
H A Dresistor.sym17 port_type=electrical
28 port_type=electrical
H A Dcapacitor.sym9 port_type=electrical
16 port_type=electrical
/dports/cad/geda/geda-gaf-1.8.2/gnetlist/examples/vams/sym/
H A Dcapacitor.sym9 port_type=electrical
16 port_type=electrical
H A Dresistor.sym19 port_type=electrical
30 port_type=electrical
/dports/games/avp/avp-20170505/src/avp/
H A Dbh_ais.h183 int hurtiness,HIT_FACING *facing,int burning,int crouching,int electrical);
185 int hurtiness,HIT_FACING *facing,int burning,int crouching,int electrical);
187 int hurtiness,HIT_FACING *facing,int burning,int crouching,int electrical);
189 int hurtiness,HIT_FACING *facing,int burning,int crouching,int electrical);
191 int hurtiness,HIT_FACING *facing,int burning,int crouching,int electrical);

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