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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/SPARC/
H A D2008-10-10-InlineAsmMemoryOperand.ll9 %fsr = alloca i32 ; <i32*> [#uses=4]
10 call void asm "st %fsr, $0", "=*m"(i32* %fsr) nounwind
11 %0 = load i32, i32* %fsr, align 4 ; <i32> [#uses=1]
13 store i32 %1, i32* %fsr, align 4
14 call void asm sideeffect "ld $0, %fsr", "*m"(i32* %fsr) nounwind
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/SPARC/
H A D2008-10-10-InlineAsmMemoryOperand.ll9 %fsr = alloca i32 ; <i32*> [#uses=4]
10 call void asm "st %fsr, $0", "=*m"(i32* %fsr) nounwind
11 %0 = load i32, i32* %fsr, align 4 ; <i32> [#uses=1]
13 store i32 %1, i32* %fsr, align 4
14 call void asm sideeffect "ld $0, %fsr", "*m"(i32* %fsr) nounwind
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/SPARC/
H A D2008-10-10-InlineAsmMemoryOperand.ll9 %fsr = alloca i32 ; <i32*> [#uses=4]
10 call void asm "st %fsr, $0", "=*m"(i32* %fsr) nounwind
11 %0 = load i32, i32* %fsr, align 4 ; <i32> [#uses=1]
13 store i32 %1, i32* %fsr, align 4
14 call void asm sideeffect "ld $0, %fsr", "*m"(i32* %fsr) nounwind
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/SPARC/
H A D2008-10-10-InlineAsmMemoryOperand.ll9 %fsr = alloca i32 ; <i32*> [#uses=4]
10 call void asm "st %fsr, $0", "=*m"(i32* %fsr) nounwind
11 %0 = load i32, i32* %fsr, align 4 ; <i32> [#uses=1]
13 store i32 %1, i32* %fsr, align 4
14 call void asm sideeffect "ld $0, %fsr", "*m"(i32* %fsr) nounwind
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/SPARC/
H A D2008-10-10-InlineAsmMemoryOperand.ll9 %fsr = alloca i32 ; <i32*> [#uses=4]
10 call void asm "st %fsr, $0", "=*m"(i32* %fsr) nounwind
11 %0 = load i32, i32* %fsr, align 4 ; <i32> [#uses=1]
13 store i32 %1, i32* %fsr, align 4
14 call void asm sideeffect "ld $0, %fsr", "*m"(i32* %fsr) nounwind
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/SPARC/
H A D2008-10-10-InlineAsmMemoryOperand.ll9 %fsr = alloca i32 ; <i32*> [#uses=4]
10 call void asm "st %fsr, $0", "=*m"(i32* %fsr) nounwind
11 %0 = load i32, i32* %fsr, align 4 ; <i32> [#uses=1]
13 store i32 %1, i32* %fsr, align 4
14 call void asm sideeffect "ld $0, %fsr", "*m"(i32* %fsr) nounwind
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/SPARC/
H A D2008-10-10-InlineAsmMemoryOperand.ll9 %fsr = alloca i32 ; <i32*> [#uses=4]
10 call void asm "st %fsr, $0", "=*m"(i32* %fsr) nounwind
11 %0 = load i32, i32* %fsr, align 4 ; <i32> [#uses=1]
13 store i32 %1, i32* %fsr, align 4
14 call void asm sideeffect "ld $0, %fsr", "*m"(i32* %fsr) nounwind
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/SPARC/
H A D2008-10-10-InlineAsmMemoryOperand.ll9 %fsr = alloca i32 ; <i32*> [#uses=4]
10 call void asm "st %fsr, $0", "=*m"(i32* %fsr) nounwind
11 %0 = load i32, i32* %fsr, align 4 ; <i32> [#uses=1]
13 store i32 %1, i32* %fsr, align 4
14 call void asm sideeffect "ld $0, %fsr", "*m"(i32* %fsr) nounwind
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/SPARC/
H A D2008-10-10-InlineAsmMemoryOperand.ll9 %fsr = alloca i32 ; <i32*> [#uses=4]
10 call void asm "st %fsr, $0", "=*m"(i32* %fsr) nounwind
11 %0 = load i32, i32* %fsr, align 4 ; <i32> [#uses=1]
13 store i32 %1, i32* %fsr, align 4
14 call void asm sideeffect "ld $0, %fsr", "*m"(i32* %fsr) nounwind
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/SPARC/
H A D2008-10-10-InlineAsmMemoryOperand.ll9 %fsr = alloca i32 ; <i32*> [#uses=4]
10 call void asm "st %fsr, $0", "=*m"(i32* %fsr) nounwind
11 %0 = load i32, i32* %fsr, align 4 ; <i32> [#uses=1]
13 store i32 %1, i32* %fsr, align 4
14 call void asm sideeffect "ld $0, %fsr", "*m"(i32* %fsr) nounwind
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/SPARC/
H A D2008-10-10-InlineAsmMemoryOperand.ll9 %fsr = alloca i32 ; <i32*> [#uses=4]
10 call void asm "st %fsr, $0", "=*m"(i32* %fsr) nounwind
11 %0 = load i32, i32* %fsr, align 4 ; <i32> [#uses=1]
13 store i32 %1, i32* %fsr, align 4
14 call void asm sideeffect "ld $0, %fsr", "*m"(i32* %fsr) nounwind
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/SPARC/
H A D2008-10-10-InlineAsmMemoryOperand.ll9 %fsr = alloca i32 ; <i32*> [#uses=4]
10 call void asm "st %fsr, $0", "=*m"(i32* %fsr) nounwind
11 %0 = load i32, i32* %fsr, align 4 ; <i32> [#uses=1]
13 store i32 %1, i32* %fsr, align 4
14 call void asm sideeffect "ld $0, %fsr", "*m"(i32* %fsr) nounwind
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/SPARC/
H A D2008-10-10-InlineAsmMemoryOperand.ll9 %fsr = alloca i32 ; <i32*> [#uses=4]
10 call void asm "st %fsr, $0", "=*m"(i32* %fsr) nounwind
11 %0 = load i32, i32* %fsr, align 4 ; <i32> [#uses=1]
13 store i32 %1, i32* %fsr, align 4
14 call void asm sideeffect "ld $0, %fsr", "*m"(i32* %fsr) nounwind
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/SPARC/
H A D2008-10-10-InlineAsmMemoryOperand.ll9 %fsr = alloca i32 ; <i32*> [#uses=4]
10 call void asm "st %fsr, $0", "=*m"(i32* %fsr) nounwind
11 %0 = load i32, i32* %fsr, align 4 ; <i32> [#uses=1]
13 store i32 %1, i32* %fsr, align 4
14 call void asm sideeffect "ld $0, %fsr", "*m"(i32* %fsr) nounwind
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/sparc/kernel/
H A Dtraps_32.c173 fpsave(&fptask->thread.float_regs[0], &fptask->thread.fsr, in do_fpd_trap()
204 unsigned long fsr; local
226 fpsave(&fpt->thread.float_regs[0], &fpt->thread.fsr,
232 switch ((fpt->thread.fsr & 0x1c000)) {
280 fsr = fpt->thread.fsr;
282 if ((fsr & 0x1c000) == (1 << 14)) {
283 if (fsr & 0x10)
285 else if (fsr & 0x08)
287 else if (fsr & 0x04)
289 else if (fsr & 0x02)
[all …]
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/sparc/kernel/
H A Dtraps_32.c173 fpsave(&fptask->thread.float_regs[0], &fptask->thread.fsr, in do_fpd_trap()
204 unsigned long fsr; local
226 fpsave(&fpt->thread.float_regs[0], &fpt->thread.fsr,
232 switch ((fpt->thread.fsr & 0x1c000)) {
280 fsr = fpt->thread.fsr;
282 if ((fsr & 0x1c000) == (1 << 14)) {
283 if (fsr & 0x10)
285 else if (fsr & 0x08)
287 else if (fsr & 0x04)
289 else if (fsr & 0x02)
[all …]
/dports/multimedia/libv4l/linux-5.13-rc2/arch/sparc/kernel/
H A Dtraps_32.c173 fpsave(&fptask->thread.float_regs[0], &fptask->thread.fsr, in do_fpd_trap()
204 unsigned long fsr; local
226 fpsave(&fpt->thread.float_regs[0], &fpt->thread.fsr,
232 switch ((fpt->thread.fsr & 0x1c000)) {
280 fsr = fpt->thread.fsr;
282 if ((fsr & 0x1c000) == (1 << 14)) {
283 if (fsr & 0x10)
285 else if (fsr & 0x08)
287 else if (fsr & 0x04)
289 else if (fsr & 0x02)
[all …]
/dports/math/opensolaris-libm/opensolaris-libm-2017.01.31/usr/src/libm/src/m9x/
H A Dfma.c109 __fenv_getfsr32(&fsr); in __fma()
300 rm = fsr >> 30; in __fma()
301 fsr &= ~FSR_CEXC; in __fma()
326 fsr |= FSR_NXC; in __fma()
363 fsr |= FSR_UFC; in __fma()
368 if ((fsr & FSR_CEXC) & (fsr >> 23)) { in __fma()
369 __fenv_setfsr32(&fsr); in __fma()
370 if (fsr & FSR_OFC) { in __fma()
375 if (fsr & FSR_NXC) in __fma()
384 fsr |= (fsr & 0x1f) << 5; in __fma()
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/MC/Sparc/
H A Dsparc-special-registers.s43 ! CHECK: ld [%g2+20], %fsr ! encoding: [0xc1,0x08,0xa0,0x14]
44 ld [%g2 + 20],%fsr
46 ! CHECK: ld [%g2+%i5], %fsr ! encoding: [0xc1,0x08,0x80,0x1d]
47 ld [%g2 + %i5],%fsr
49 ! CHECK: st %fsr, [%g2+20] ! encoding: [0xc1,0x28,0xa0,0x14]
50 st %fsr,[%g2 + 20]
52 ! CHECK: st %fsr, [%g2+%i5] ! encoding: [0xc1,0x28,0x80,0x1d]
53 st %fsr,[%g2 + %i5]
/dports/devel/llvm11/llvm-11.0.1.src/test/MC/Sparc/
H A Dsparc-special-registers.s43 ! CHECK: ld [%g2+20], %fsr ! encoding: [0xc1,0x08,0xa0,0x14]
44 ld [%g2 + 20],%fsr
46 ! CHECK: ld [%g2+%i5], %fsr ! encoding: [0xc1,0x08,0x80,0x1d]
47 ld [%g2 + %i5],%fsr
49 ! CHECK: st %fsr, [%g2+20] ! encoding: [0xc1,0x28,0xa0,0x14]
50 st %fsr,[%g2 + 20]
52 ! CHECK: st %fsr, [%g2+%i5] ! encoding: [0xc1,0x28,0x80,0x1d]
53 st %fsr,[%g2 + %i5]
/dports/devel/llvm10/llvm-10.0.1.src/test/MC/Sparc/
H A Dsparc-special-registers.s43 ! CHECK: ld [%g2+20], %fsr ! encoding: [0xc1,0x08,0xa0,0x14]
44 ld [%g2 + 20],%fsr
46 ! CHECK: ld [%g2+%i5], %fsr ! encoding: [0xc1,0x08,0x80,0x1d]
47 ld [%g2 + %i5],%fsr
49 ! CHECK: st %fsr, [%g2+20] ! encoding: [0xc1,0x28,0xa0,0x14]
50 st %fsr,[%g2 + 20]
52 ! CHECK: st %fsr, [%g2+%i5] ! encoding: [0xc1,0x28,0x80,0x1d]
53 st %fsr,[%g2 + %i5]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/MC/Sparc/
H A Dsparc-special-registers.s43 ! CHECK: ld [%g2+20], %fsr ! encoding: [0xc1,0x08,0xa0,0x14]
44 ld [%g2 + 20],%fsr
46 ! CHECK: ld [%g2+%i5], %fsr ! encoding: [0xc1,0x08,0x80,0x1d]
47 ld [%g2 + %i5],%fsr
49 ! CHECK: st %fsr, [%g2+20] ! encoding: [0xc1,0x28,0xa0,0x14]
50 st %fsr,[%g2 + 20]
52 ! CHECK: st %fsr, [%g2+%i5] ! encoding: [0xc1,0x28,0x80,0x1d]
53 st %fsr,[%g2 + %i5]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/MC/Sparc/
H A Dsparc-special-registers.s43 ! CHECK: ld [%g2+20], %fsr ! encoding: [0xc1,0x08,0xa0,0x14]
44 ld [%g2 + 20],%fsr
46 ! CHECK: ld [%g2+%i5], %fsr ! encoding: [0xc1,0x08,0x80,0x1d]
47 ld [%g2 + %i5],%fsr
49 ! CHECK: st %fsr, [%g2+20] ! encoding: [0xc1,0x28,0xa0,0x14]
50 st %fsr,[%g2 + 20]
52 ! CHECK: st %fsr, [%g2+%i5] ! encoding: [0xc1,0x28,0x80,0x1d]
53 st %fsr,[%g2 + %i5]
/dports/devel/llvm90/llvm-9.0.1.src/test/MC/Sparc/
H A Dsparc-special-registers.s43 ! CHECK: ld [%g2+20], %fsr ! encoding: [0xc1,0x08,0xa0,0x14]
44 ld [%g2 + 20],%fsr
46 ! CHECK: ld [%g2+%i5], %fsr ! encoding: [0xc1,0x08,0x80,0x1d]
47 ld [%g2 + %i5],%fsr
49 ! CHECK: st %fsr, [%g2+20] ! encoding: [0xc1,0x28,0xa0,0x14]
50 st %fsr,[%g2 + 20]
52 ! CHECK: st %fsr, [%g2+%i5] ! encoding: [0xc1,0x28,0x80,0x1d]
53 st %fsr,[%g2 + %i5]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/MC/Sparc/
H A Dsparc-special-registers.s43 ! CHECK: ld [%g2+20], %fsr ! encoding: [0xc1,0x08,0xa0,0x14]
44 ld [%g2 + 20],%fsr
46 ! CHECK: ld [%g2+%i5], %fsr ! encoding: [0xc1,0x08,0x80,0x1d]
47 ld [%g2 + %i5],%fsr
49 ! CHECK: st %fsr, [%g2+20] ! encoding: [0xc1,0x28,0xa0,0x14]
50 st %fsr,[%g2 + 20]
52 ! CHECK: st %fsr, [%g2+%i5] ! encoding: [0xc1,0x28,0x80,0x1d]
53 st %fsr,[%g2 + %i5]

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